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Commit cb2fc48f authored by Andrey Filippov's avatar Andrey Filippov
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eliminating use of PLL with GTX

parent 36c295d8
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.project
View file @ cb2fc48f
......@@ -52,87 +52,87 @@
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<name>vivado_logs/VivadoBitstream.log</name>
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<location>/home/andrey/git/x393_sata/vivado_logs/VivadoBitstream-20160312151407716.log</location>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoBitstream-20160312231527798.log</location>
</link>
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<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOpt-20160312151407716.log</location>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOpt-20160312231527798.log</location>
</link>
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<name>vivado_logs/VivadoOptPhys.log</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPhys-20160312151407716.log</location>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPhys-20160312231527798.log</location>
</link>
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<name>vivado_logs/VivadoOptPower.log</name>
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<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPower-20160312151407716.log</location>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPower-20160312231527798.log</location>
</link>
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<name>vivado_logs/VivadoPlace.log</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoPlace-20160312151407716.log</location>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoPlace-20160312231527798.log</location>
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<location>/home/andrey/git/x393_sata/vivado_logs/VivadoRoute-20160312231527798.log</location>
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<location>/home/andrey/git/x393_sata/vivado_logs/VivadoSynthesis-20160312231356578.log</location>
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<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
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<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-20160312231527798.dcp</location>
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<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-place-20160312231527798.dcp</location>
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host/gtx_wrap.v
View file @ cb2fc48f
This diff is collapsed.
host/sata_phy.v
View file @ cb2fc48f
......@@ -227,7 +227,7 @@ wire txp;
wire txn;
wire rxp;
wire rxn;
wire txoutclk;
wire txoutclk; // comes out global from gtx_wrap
wire txpmareset_done;
wire rxeyereset_done;
......@@ -377,7 +377,7 @@ always @ (posedge clk or posedge extrst)
`endif // OLD_TXPCSRESET
// issue rx reset to restore functionality after oob sequence. Let it lasts 8 clock lycles
// issue rx reset to restore functionality after oob sequence. Let it last 8 clock cycles
reg [3:0] rxreset_oob_cnt;
wire rxreset_oob_stop;
......@@ -395,73 +395,89 @@ always @ (posedge clk or posedge extrst)
* USRCLKs generation. USRCLK @ 150MHz, same as TXOUTCLK; USRCLK2 @ 75Mhz -> sata_clk === sclk
* It's recommended to use MMCM instead of PLL, whatever
*/
wire usrpll_fb_clk;
wire usrclk;
wire usrclk2;
wire usrclk_global;
BUFG bufg_usrclk (.O(usrclk_global),.I(usrclk));
wire usrclk2;
//`define GTX_USE_PLL
`ifdef GTX_USE_PLL
wire usrpll_fb_clk;
wire usrclk;
select_clk_buf #(
.BUFFER_TYPE("BUFG")
) bufg_usrclk (
.o (usrclk_global), // output
.i (usrclk), // input
.clr (1'b0) // input
);
PLLE2_ADV #(
.BANDWIDTH ("OPTIMIZED"),
.CLKFBOUT_MULT (8),
.CLKFBOUT_PHASE (0.000),
.CLKIN1_PERIOD (6.666),
.CLKIN2_PERIOD (0.000),
.CLKOUT0_DIVIDE (8),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_PHASE (0.000),
.CLKOUT1_DIVIDE (16),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT1_PHASE (0.000),
.COMPENSATION ("ZHOLD"),
.DIVCLK_DIVIDE (1),
.IS_CLKINSEL_INVERTED (1'b0),
.IS_PWRDWN_INVERTED (1'b0),
.IS_RST_INVERTED (1'b0),
.REF_JITTER1 (0.010),
.REF_JITTER2 (0.010),
.STARTUP_WAIT ("FALSE")
)
usrclk_pll(
.CLKFBOUT (usrpll_fb_clk),
.CLKOUT0 (usrclk), //150Mhz
.CLKOUT1 (usrclk2), // 75MHz
.CLKOUT2 (),
.CLKOUT3 (),
.CLKOUT4 (),
.CLKOUT5 (),
.DO (),
.DRDY (),
.LOCKED (usrpll_locked),
.CLKFBIN (usrpll_fb_clk),
.CLKIN1 (txoutclk),
.CLKIN2 (1'b0),
.CLKINSEL (1'b1),
.DADDR (7'h0),
.DCLK (drpclk),
.DEN (1'b0),
.DI (16'h0),
.DWE (1'b0),
.PWRDWN (1'b0),
.RST (~cplllock)
);
`else // GTX_USE_PLL
// divide txoutclk (global) by 2, then make global. Does not need to be phase-aligned - will use FIFO
reg usrclk2_r;
always @ (posedge txoutclk) begin
if (~cplllock) usrclk2_r <= 0;
else usrclk2_r <= ~usrclk2;
end
assign txusrclk = txoutclk; // 150MHz, was already global
assign usrclk_global = txoutclk; // 150MHz, was already global
assign usrclk2 = usrclk2_r;
assign usrpll_locked = cplllock;
`endif // else // GTX_USE_PLL
assign txusrclk = usrclk_global; // 150MHz
assign txusrclk2 = clk; // usrclk2; // should not use non-buffered clock!
assign txusrclk2 = clk; // usrclk2;
assign rxusrclk = usrclk_global; // 150MHz
assign rxusrclk2 = clk; // usrclk2; // should not use non-buffered clock!
PLLE2_ADV #(
.BANDWIDTH ("OPTIMIZED"),
.CLKFBOUT_MULT (8),
.CLKFBOUT_PHASE (0.000),
.CLKIN1_PERIOD (6.666),
.CLKIN2_PERIOD (0.000),
.CLKOUT0_DIVIDE (8),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_PHASE (0.000),
.CLKOUT1_DIVIDE (16),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT1_PHASE (0.000),
/* .CLKOUT2_DIVIDE = 1,
.CLKOUT2_DUTY_CYCLE = 0.500,
.CLKOUT2_PHASE = 0.000,
.CLKOUT3_DIVIDE = 1,
.CLKOUT3_DUTY_CYCLE = 0.500,
.CLKOUT3_PHASE = 0.000,
.CLKOUT4_DIVIDE = 1,
.CLKOUT4_DUTY_CYCLE = 0.500,
.CLKOUT4_PHASE = 0.000,
.CLKOUT5_DIVIDE = 1,
.CLKOUT5_DUTY_CYCLE = 0.500,
.CLKOUT5_PHASE = 0.000,*/
.COMPENSATION ("ZHOLD"),
.DIVCLK_DIVIDE (1),
.IS_CLKINSEL_INVERTED (1'b0),
.IS_PWRDWN_INVERTED (1'b0),
.IS_RST_INVERTED (1'b0),
.REF_JITTER1 (0.010),
.REF_JITTER2 (0.010),
.STARTUP_WAIT ("FALSE")
)
usrclk_pll(
.CLKFBOUT (usrpll_fb_clk),
.CLKOUT0 (usrclk), //150Mhz
.CLKOUT1 (usrclk2), // 75MHz
.CLKOUT2 (),
.CLKOUT3 (),
.CLKOUT4 (),
.CLKOUT5 (),
.DO (),
.DRDY (),
.LOCKED (usrpll_locked),
.CLKFBIN (usrpll_fb_clk),
.CLKIN1 (txoutclk),
.CLKIN2 (1'b0),
.CLKINSEL (1'b1),
.DADDR (7'h0),
.DCLK (drpclk),
.DEN (1'b0),
.DI (16'h0),
.DWE (1'b0),
.PWRDWN (1'b0),
.RST (~cplllock)
assign rxusrclk2 = clk; // usrclk2;
select_clk_buf #(
.BUFFER_TYPE("BUFG")
) bufg_sclk (
.o (clk), // output
.i (usrclk2), // input
.clr (1'b0) // input
);
/*
......@@ -528,7 +544,7 @@ gtx_wrap
.txelecidle (txelecidle), // input wire
.txp (txp), // output wire
.txn (txn), // output wire
.txoutclk (txoutclk), // output wire
.txoutclk (txoutclk), // output wire // made global inside
.txpcsreset (txpcsreset), // input wire
.txresetdone (txresetdone), // output wire
.txcominit (txcominit), // input wire
......@@ -547,7 +563,7 @@ gtx_wrap
.dbg_rxcdrlock (dbg_rxcdrlock) ,
.dbg_rxdlysresetdone(dbg_rxdlysresetdone),
.txbufstatus (txbufstatus[1:0]),
.xclk (xclk) // output receive clock, just to measure frequency
.xclk (xclk) // output receive clock, just to measure frequency // global
`ifdef USE_DATASCOPE
,.datascope_clk (datascope_clk), // output
.datascope_waddr (datascope_waddr), // output[9:0]
......@@ -580,8 +596,6 @@ gtx_wrap
assign cplllockdetclk = reliable_clk; //gtrefclk;
assign drpclk = reliable_clk; //gtrefclk;
//assign clk = usrclk2;
BUFG bufg_sclk (.O(clk),.I(usrclk2));
assign rxn = rxn_in;
assign rxp = rxp_in;
assign txn_out = txn;
......
system_defines.vh
View file @ cb2fc48f
......@@ -3,7 +3,7 @@
`define SYSTEM_DEFINES
`define USE_DRP
`define ALIGN_CLOCKS
`define STRAIGHT_XCLK
// `define STRAIGHT_XCLK
`define USE_DATASCOPE
// `define DATASCOPE_INCOMING_RAW
`define PRELOAD_BRAMS
......
top.v
View file @ cb2fc48f
......@@ -40,7 +40,7 @@
`include "system_defines.vh"
module top #(
//`include "includes/x393_parameters.vh" // SuppressThisWarning VEditor - partially used
`include "includes/x393_parameters.vh" // SuppressThisWarning VEditor - partially used
)
(
// sata serial data iface
......@@ -149,11 +149,31 @@ always @(posedge comb_rst or posedge axi_aclk0) begin
else axi_rst_pre <= 1'b0;
end
//BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(/*fclk[0]*/ sclk));
//assign axi_aclk = sclk;
BUFG bufg_axi_aclk0_i (.O(axi_aclk0),.I(fclk[0]));
BUFG bufg_axi_rst_i (.O(axi_rst),.I(axi_rst_pre));
BUFG bufg_extrst_i (.O(extrst),.I(axi_rst_pre));
select_clk_buf #(
.BUFFER_TYPE("BUFG")
) bufg_axi_aclk0_i (
.o (axi_aclk0), // output
.i (fclk[0]), // input
.clr (1'b0) // input
);
select_clk_buf #(
.BUFFER_TYPE("BUFG")
) bufg_axi_rst_i (
.o (axi_rst), // output
.i (axi_rst_pre), // input
.clr (1'b0) // input
);
select_clk_buf #(
.BUFFER_TYPE("BUFG")
) bufg_extrst_i (
.o (extrst), // output
.i (axi_rst_pre), // input
.clr (1'b0) // input
);
axi_hp_clk #(
.CLKIN_PERIOD(20.000),
.CLKFBOUT_MULT_AXIHP(18),
......@@ -164,6 +184,7 @@ axi_hp_clk #(
.clk_axihp (hclk), // output
.locked_axihp () // output // not controlled?
);
sata_ahci_top sata_top(
.sata_clk (sclk),
// reliable clock to source drp and cpll lock det circuits
......
x393/wrap/select_clk_buf.v 0 → 100644
View file @ cb2fc48f
/*******************************************************************************
* Module: select_clk_buf
* Date:2015-11-07
* Author: andrey
* Description: Select one of the clock buffers primitives by parameter
*
* Copyright (c) 2015 Elphel, Inc .
* select_clk_buf.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* select_clk_buf.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
`timescale 1ns/1ps
module select_clk_buf #(
parameter BUFFER_TYPE = "BUFR" // to use clr
)(
output o,
input i,
input clr // for BUFR_only
);
generate
if (BUFFER_TYPE == "BUFG") BUFG clk1x_i (.O(o), .I(i));
else if (BUFFER_TYPE == "BUFH") BUFH clk1x_i (.O(o), .I(i));
else if (BUFFER_TYPE == "BUFR") BUFR clk1x_i (.O(o), .I(i), .CE(1'b1), .CLR(clr));
else if (BUFFER_TYPE == "BUFMR") BUFMR clk1x_i (.O(o), .I(i));
else if (BUFFER_TYPE == "BUFIO") BUFIO clk1x_i (.O(o), .I(i));
else assign o = i;
endgenerate
endmodule
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