Finished initial code, starting verification

ahci/ahci_sata_layers.v

@@ -52,7 +52,7 @@ module  ahci_sata_layers #(
     output             x_rdy_collision, // X_RDY/X_RDY collision on interface 
     output             syncesc_recv,    // Where to get it?
 
-    input              pcmd_cleared,      // PxCMD.ST 1->0 transition by software
+    input              pcmd_st_cleared,      // PxCMD.ST 1->0 transition by software
     input              syncesc_send,      // Send sync escape
     output             syncesc_send_done, // "SYNC escape until the interface is quiescent..."
     input              comreset_send,     // Not possible yet?
@@ -231,7 +231,7 @@ module  ahci_sata_layers #(
         .link_reset       (ll_link_reset),         // input wire  // oob sequence is reinitiated and link now is not established or rxelecidle
         .sync_escape_req  (syncesc_send),          // input wire  // TL demands to brutally cancel current transaction
         .sync_escape_ack  (syncesc_send_done),     // output wire // acknowlegement of a successful reception?
-        .incom_stop_req   (pcmd_cleared),          // input wire  // TL demands to stop current recieving session
+        .incom_stop_req   (pcmd_st_cleared),          // input wire  // TL demands to stop current recieving session
         // inputs from phy
         .phy_ready        (phy_ready),             // input wire        // phy is ready - link is established
         // data-primitives stream from phy

dma/sata_top.v

@@ -42,9 +42,10 @@
  * Takes commands from axi iface as a slave, transfers data with another axi iface as a master
  */
  module sata_top(
-    output  wire    sclk,
+    output  wire    sata_clk,
     output  wire    sata_rst,
-    input   wire    extrst,
+//    input   wire    extrst,
+    input   wire    arst,
     
     // reliable clock to source drp and cpll lock det circuits
     input   wire    reliable_clk,
@@ -147,6 +148,8 @@
     input   wire    [2:0]   afi_racount,
     output  wire            afi_rdissuecap1en,
 
+    output  wire            irq, // not used here, for compatibility with AHCI branch
+
 /*
  * PHY
  */
@@ -158,7 +161,7 @@
     input   wire            EXTCLK_P,
     input   wire            EXTCLK_N
  );
-
+assign irq = 0;
 //wire    sata_rst;
 // dma_regs <-> sata host
 // tmp to cmd control
@@ -238,7 +241,7 @@ wire                bram_regen;
 // sata logic reset
 //wire            rst;
 // sata clk
-//wire            sclk;
+//wire            sata_clk;
 // dma_regs <-> dma_control
 wire    [31:7]  mem_address;
 wire    [31:0]  lba;
@@ -354,7 +357,7 @@ axi_regs axi_regs(
 dma_regs dma_regs(
     .rst            (ARESETN),                     // input wire 
     .ACLK           (ACLK),                        // input wire
-    .sclk           (sclk),                        // input wire
+    .sclk           (sata_clk),                        // input wire
 // control iface
     .mem_address    (mem_address[31:7]),           // output[31:7] wire
     .lba            (lba),                         // output[31:0] wire
@@ -442,7 +445,7 @@ dma_regs dma_regs(
 
 
 dma_control dma_control(
-    .sclk               (sclk),               // input wire
+    .sclk               (sata_clk),               // input wire
     .hclk               (hclk),               // input wire
     .rst                (sata_rst),           // input wire
 
@@ -545,9 +548,9 @@ V    .MEMBRIDGE_ADDR         (),
     .FRAME_HEIGHT_BITS      (),
     .FRAME_WIDTH_BITS       ()
 )*/ membridge(
-    .mrst                   (sata_rst), // hrst),   // input Andrey: Wrong, should be @sclk
+    .mrst                   (sata_rst), // hrst),   // input Andrey: Wrong, should be @sata_clk
     .hrst                   (hrst),                 // input
-    .mclk                   (sclk),                 // input
+    .mclk                   (sata_clk),                 // input
     .hclk                   (hclk),                 // input
     .cmd_ad                 (cmd_ad),               // input[7:0]
     .cmd_stb                (cmd_stb),              // input // Nothing here
@@ -619,11 +622,11 @@ V    .MEMBRIDGE_ADDR         (),
 assign rdata_done = 1'b0;
 
 sata_host sata_host(
-    .extrst                     (extrst),
+    .extrst                     (arst),
     // sata rst
     .rst                        (sata_rst),
     // sata clk
-    .clk                        (sclk),
+    .clk                        (sata_clk),
     // reliable clock to source drp and cpll lock det circuits
     .reliable_clk               (reliable_clk),
 // temporary

dma/top.v

@@ -54,12 +54,12 @@ module top #(
 );
 
 wire            axi_aclk0;
-wire            sclk;
-wire            sata_rst;
+wire            sclk    ; // Just output from SATA subsystem SuppressThisWarning VEditor Not used
+wire            sata_rst; // Just output from SATA subsystem SuppressThisWarning VEditor Not used
 wire            extrst;
 wire    [3:0]   fclk;
 wire    [3:0]   frst;
-wire            axi_aclk;
+//wire            axi_aclk;
 wire            axi_rst;
 wire            hclk;
 wire            comb_rst;
@@ -141,6 +141,8 @@ wire [ 7:0] afi3_rcount;     // input[7:0]
 wire [ 2:0] afi3_racount;     // input[2:0] 
 wire        afi3_rdissuecap1en; // output
 
+wire        irq;              // ps7 IRQ
+
 assign comb_rst=~frst[0] | frst[1];
 always @(posedge comb_rst or posedge axi_aclk0) begin
     if (comb_rst) axi_rst_pre <= 1'b1;
@@ -148,7 +150,7 @@ always @(posedge comb_rst or posedge axi_aclk0) begin
 end
 
 //BUFG bufg_axi_aclk_i  (.O(axi_aclk),.I(/*fclk[0]*/ sclk));
-assign  axi_aclk = sclk;
+//assign  axi_aclk = sclk;
 BUFG bufg_axi_aclk0_i  (.O(axi_aclk0),.I(fclk[0]));
 BUFG bufg_axi_rst_i    (.O(axi_rst),.I(axi_rst_pre));
 BUFG bufg_extrst_i     (.O(extrst),.I(axi_rst_pre));
@@ -162,14 +164,17 @@ axi_hp_clk #(
     .clk_axihp    (hclk), // output
     .locked_axihp () // output // not controlled?
 );
-
+`ifdef AHCI_SATA
+sata_ahci_top sata_top(
+`else
 sata_top sata_top(
-    .sclk                       (sclk),
+`endif
+    .sata_clk                   (sclk),
     // reliable clock to source drp and cpll lock det circuits
     .reliable_clk               (axi_aclk0),
     .hclk                       (hclk),
     .sata_rst                   (sata_rst),
-    .extrst                     (extrst),
+    .arst                       (extrst),
     .ACLK                       (axi_aclk0),
     .ARESETN                    (axi_rst/* | sata_rst*/),
 // AXI PS Master GP1: Read Address    
@@ -263,6 +268,8 @@ sata_top sata_top(
     .afi_racount                (afi3_racount),
     .afi_rdissuecap1en          (afi3_rdissuecap1en),
 
+    .irq                        (irq), // output wire 
+
 /*
  * PHY
  */
@@ -502,8 +509,8 @@ PS7 ps7_i (
     .DMA3DATYPE(),               // DMAC 3 DMA Ackbowledge TYpe (completed single AXI, completed burst AXI, flush request), output
     .DMA3RSTN(),                 // DMAC 3 RESET output (reserved, do not use), output
  // Interrupt signals
-    .IRQF2P(),                   // Interrupts, OL to PS [19:0], input
-    .IRQP2F(),                   // Interrupts, OL to PS [28:0], output
+    .IRQF2P({19'b0,irq}),        // Interrupts, PL to PS [19:0], input
+    .IRQP2F(),                   // Interrupts, PS to PL [28:0], output
  // Event Signals
     .EVENTEVENTI(),              // EVENT Wake up one or both CPU from WFE state, input
     .EVENTEVENTO(),              // EVENT Asserted when one of the COUs executed SEV instruction, output

system_defines.vh

@@ -2,6 +2,7 @@
 `ifndef SYSTEM_DEFINES
   `define SYSTEM_DEFINES
   `define PRELOAD_BRAMS
+  `define AHCI_SATA 1
 // Enviroment-dependent options
   `ifdef IVERILOG
     `define SIMULATION