regular commit (b2f9de10) · Commits · Elphel / x393_sata

device/sata_phy_dev.v

+53 −11

Original line number	Original line	Diff line number	Diff line
	@@ -292,13 +292,13 @@ ext_clock_buf(

	GTXE2_CHANNEL #(		GTXE2_CHANNEL #(
	.SIM_RECEIVER_DETECT_PASS ("TRUE"),		.SIM_RECEIVER_DETECT_PASS ("TRUE"),
	.SIM_TX_EIDLE_DRIVE_LEVEL ("X"),		.SIM_TX_EIDLE_DRIVE_LEVEL ("Z"),
	.SIM_RESET_SPEEDUP ("FALSE"),		.SIM_RESET_SPEEDUP ("FALSE"),
	.SIM_CPLLREFCLK_SEL (3'b001),		.SIM_CPLLREFCLK_SEL (3'b001),
	.SIM_VERSION ("4.0"),		.SIM_VERSION ("4.0"),
	.ALIGN_COMMA_DOUBLE ("FALSE"),		.ALIGN_COMMA_DOUBLE ("FALSE"),
	.ALIGN_COMMA_ENABLE (10'b1111111111),		.ALIGN_COMMA_ENABLE (10'b1111111111),
	.ALIGN_COMMA_WORD (1),		.ALIGN_COMMA_WORD (2),
	.ALIGN_MCOMMA_DET ("TRUE"),		.ALIGN_MCOMMA_DET ("TRUE"),
	.ALIGN_MCOMMA_VALUE (10'b1010000011),		.ALIGN_MCOMMA_VALUE (10'b1010000011),
	.ALIGN_PCOMMA_DET ("TRUE"),		.ALIGN_PCOMMA_DET ("TRUE"),
	@@ -418,9 +418,9 @@ GTXE2_CHANNEL #(
	.PD_TRANS_TIME_TO_P2 (8'h64),		.PD_TRANS_TIME_TO_P2 (8'h64),
	.SAS_MAX_COM (64),		.SAS_MAX_COM (64),
	.SAS_MIN_COM (36),		.SAS_MIN_COM (36),
	.SATA_BURST_SEQ_LEN (4'b0111),		.SATA_BURST_SEQ_LEN (4'b0101),
	.SATA_BURST_VAL (3'b110),		.SATA_BURST_VAL (3'b100),
	.SATA_EIDLE_VAL (3'b110),		.SATA_EIDLE_VAL (3'b100),
	.SATA_MAX_BURST (8),		.SATA_MAX_BURST (8),
	.SATA_MAX_INIT (21),		.SATA_MAX_INIT (21),
	.SATA_MAX_WAKE (7),		.SATA_MAX_WAKE (7),
	@@ -729,13 +729,55 @@ gtx(

	// align to 4-byte boundary		// align to 4-byte boundary
	reg twobytes_shift;		reg twobytes_shift;
			reg onebyte_shift;
	always @ (posedge clk)		always @ (posedge clk)
	twobytes_shift <= rst ? 1'b0 : rxchariscomma_gtx[0] === 1'bx ? 1'b0 : rxchariscomma_gtx[2] === 1'bx ? 1'b0 : rxchariscomma_gtx[2] ? 1'b1 : rxchariscomma_gtx[0] ? 1'b0 : twobytes_shift;		twobytes_shift <= rst ? 1'b0 : rxchariscomma_gtx[0] === 1'bx \| rxchariscomma_gtx[1] === 1'bx \| rxchariscomma_gtx[2] === 1'bx \| rxchariscomma_gtx[3] === 1'bx ? 1'b0
	assign rxdata = twobytes_shift ? {rxdata_gtx[63:32] , rxdata_gtx[15:0] , rxdata_gtx[31:16] } : rxdata_gtx;		: rxchariscomma_gtx[2] \| rxchariscomma_gtx[3] ? 1'b1 : rxchariscomma_gtx[0] \| rxchariscomma_gtx[1] ? 1'b0 : twobytes_shift;
	assign rxcharisk = twobytes_shift ? {rxcharisk_gtx[7:4] , rxcharisk_gtx[1:0] , rxcharisk_gtx[3:2] } : rxcharisk_gtx;		always @ (posedge clk)
	assign rxchariscomma = twobytes_shift ? {rxchariscomma_gtx[7:4], rxchariscomma_gtx[1:0], rxchariscomma_gtx[3:2]} : rxchariscomma_gtx;		onebyte_shift <= rst ? 1'b0 : rxchariscomma_gtx[0] === 1'bx \| rxchariscomma_gtx[1] === 1'bx \| rxchariscomma_gtx[2] === 1'bx \| rxchariscomma_gtx[3] === 1'bx ? 1'b0
	assign rxdisperr = twobytes_shift ? {rxdisperr_gtx[7:4] , rxdisperr_gtx[1:0] , rxdisperr_gtx[3:2] } : rxdisperr_gtx;		: rxchariscomma_gtx[1] \| rxchariscomma_gtx[3] ? 1'b1 : rxchariscomma_gtx[0] \| rxchariscomma_gtx[2] ? 1'b0 : onebyte_shift;
	assign rxnotintable = twobytes_shift ? {rxnotintable_gtx[7:4] , rxnotintable_gtx[1:0] , rxnotintable_gtx[3:2] } : rxnotintable_gtx;
			wire [31:0] shifted_rxdata;
			wire [ 7:0] shifted_rxcharisk;
			wire [ 7:0] shifted_rxchariscomma;
			wire [ 7:0] shifted_rxdisperr;
			wire [ 7:0] shifted_rxnotintable;
			wire [ 1:0] shift_val = {twobytes_shift, onebyte_shift};
			reg [31:0] rxdata_gtx_r ;
			reg [ 7:0] rxcharisk_gtx_r ;
			reg [ 7:0] rxchariscomma_gtx_r;
			reg [ 7:0] rxdisperr_gtx_r ;
			reg [ 7:0] rxnotintable_gtx_r ;
			always @ (posedge clk)
			begin
			rxdata_gtx_r <= rxdata_gtx [31:0];
			rxcharisk_gtx_r <= rxcharisk_gtx [ 3:0];
			rxchariscomma_gtx_r <= rxchariscomma_gtx [ 3:0];
			rxdisperr_gtx_r <= rxdisperr_gtx [ 3:0];
			rxnotintable_gtx_r <= rxnotintable_gtx [ 3:0];
			end
			wire [63:0] rxdata_d = {rxdata_gtx [31:0], rxdata_gtx_r [31:0]};
			wire [ 7:0] rxcharisk_d = {rxcharisk_gtx [ 3:0], rxcharisk_gtx_r [ 3:0]};
			wire [ 7:0] rxchariscomma_d = {rxchariscomma_gtx[ 3:0], rxchariscomma_gtx_r [ 3:0]};
			wire [ 7:0] rxdisperr_d = {rxdisperr_gtx [ 3:0], rxdisperr_gtx_r [ 3:0]};
			wire [ 7:0] rxnotintable_d = {rxnotintable_gtx [ 3:0], rxnotintable_gtx_r [ 3:0]};
			genvar ii;
			generate
			for (ii = 0; ii < 4; ii = ii + 1)
			begin: ads
			assign shifted_rxdata [ii8 + 7:ii8] = shift_val == 2'b11 ? rxdata_d[(ii + 3)8 + 7:(ii + 3)8] : shift_val == 2'b10 ? rxdata_d[(ii + 2)8 + 7:(ii + 2)8] : shift_val == 2'b01 ? rxdata_d[(ii + 1)8 + 7:(ii + 1)8] : rxdata_d[ii8 + 7:ii8];
			assign shifted_rxcharisk [ii] = shift_val == 2'b11 ? rxcharisk_d [(ii + 3)] : shift_val == 2'b10 ? rxcharisk_d [(ii + 2)] : shift_val == 2'b01 ? rxcharisk_d [(ii + 1)] : rxcharisk_d [ii];
			assign shifted_rxchariscomma[ii] = shift_val == 2'b11 ? rxchariscomma_d[(ii + 3)] : shift_val == 2'b10 ? rxchariscomma_d[(ii + 2)] : shift_val == 2'b01 ? rxchariscomma_d[(ii + 1)] : rxchariscomma_d[ii];
			assign shifted_rxdisperr [ii] = shift_val == 2'b11 ? rxdisperr_d [(ii + 3)] : shift_val == 2'b10 ? rxdisperr_d [(ii + 2)] : shift_val == 2'b01 ? rxdisperr_d [(ii + 1)] : rxdisperr_d [ii];
			assign shifted_rxnotintable [ii] = shift_val == 2'b11 ? rxnotintable_d [(ii + 3)] : shift_val == 2'b10 ? rxnotintable_d [(ii + 2)] : shift_val == 2'b01 ? rxnotintable_d [(ii + 1)] : rxnotintable_d [ii];
			end
			endgenerate

			assign rxdata = {rxdata_gtx[63:32] , shifted_rxdata };
			assign rxcharisk = {rxcharisk_gtx[7:4] , shifted_rxcharisk };
			assign rxchariscomma = {rxchariscomma_gtx[7:4], shifted_rxchariscomma};
			assign rxdisperr = {rxdisperr_gtx[7:4] , shifted_rxdisperr };
			assign rxnotintable = {rxnotintable_gtx[7:4] , shifted_rxnotintable };

	assign ll_err_out = rxdisperr[3:0] \| rxnotintable[3:0];		assign ll_err_out = rxdisperr[3:0] \| rxnotintable[3:0];

dma/dma_regs.v

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -166,7 +166,7 @@ begin
	reg04 <= rst ? 32'h0 : bram_wen & (bram_waddr[7:0] == 8'hf1) ? wdata : reg04;		reg04 <= rst ? 32'h0 : bram_wen & (bram_waddr[7:0] == 8'hf1) ? wdata : reg04;
	reg08 <= rst ? 32'h0 : bram_wen & (bram_waddr[7:0] == 8'hf2) ? wdata : reg08;		reg08 <= rst ? 32'h0 : bram_wen & (bram_waddr[7:0] == 8'hf2) ? wdata : reg08;
	reg0c <= rst ? 32'h0 : bram_wen & (bram_waddr[7:0] == 8'hf3) ? wdata : reg0c;		reg0c <= rst ? 32'h0 : bram_wen & (bram_waddr[7:0] == 8'hf3) ? wdata : reg0c;
	reg10 <= rst ? 32'h0 : dma_start_aclk ? 32'h0 : dma_done_aclk ? 32'hffffffff : reg10; // status reg		reg10 <= rst ? 32'h0 : dma_start_aclk ? 32'h0 : {31'h0, dma_done_aclk} ? 32'hffffffff : reg10; // status reg
	reg14 <= rst ? 32'h0 : dma_done_aclk ? reg00 : reg14;		reg14 <= rst ? 32'h0 : dma_done_aclk ? reg00 : reg14;
	end		end

dma/sata_top.v

+8 −8

Original line number	Original line	Diff line number	Diff line
	@@ -36,6 +36,7 @@
	// reliable clock to source drp and cpll lock det circuits		// reliable clock to source drp and cpll lock det circuits
	input wire reliable_clk,		input wire reliable_clk,

			input wire hclk,
	/*		/*
	* Commands interface		* Commands interface
	*/		*/
	@@ -232,7 +233,7 @@ wire dma_type;
	wire dma_start;		wire dma_start;
	wire dma_done;		wire dma_done;
	// axi-hp clock		// axi-hp clock
	wire hclk;		//wire hclk;
	// dma_control <-> dma_adapter command iface		// dma_control <-> dma_adapter command iface
	wire adp_busy;		wire adp_busy;
	wire [31:7] adp_addr;		wire [31:7] adp_addr;
	@@ -283,10 +284,9 @@ wire [63:0] buf_rdata;
	wire rdata_done; // = membridge.is_last_in_page & membridge.afi_rready;		wire rdata_done; // = membridge.is_last_in_page & membridge.afi_rready;

	//assign rst = ARESETN;		//assign rst = ARESETN;
			reg hrst;
	// TODO		always @ (posedge hclk)
	assign hclk = ACLK;		hrst <= sata_rst;


	axi_regs axi_regs(		axi_regs axi_regs(
	// axi iface		// axi iface
	@@ -477,7 +477,7 @@ dma_control dma_control(

	dma_adapter dma_adapter(		dma_adapter dma_adapter(
	.clk (hclk),		.clk (hclk),
	.rst (sata_rst),		.rst (hrst),
	// command iface		// command iface
	.cmd_type (adp_type),		.cmd_type (adp_type),
	.cmd_val (adp_val),		.cmd_val (adp_val),
	@@ -530,8 +530,8 @@ V .MEMBRIDGE_ADDR (),
	.FRAME_HEIGHT_BITS (),		.FRAME_HEIGHT_BITS (),
	.FRAME_WIDTH_BITS ()		.FRAME_WIDTH_BITS ()
	)*/ membridge(		)*/ membridge(
	.mrst (sata_rst), // input		.mrst (hrst), // input
	.hrst (ARESETN), // input		.hrst (hrst), // input
	.mclk (hclk), // input		.mclk (hclk), // input
	.hclk (hclk), // input		.hclk (hclk), // input
	.cmd_ad (cmd_ad),		.cmd_ad (cmd_ad),

dma/top.v

+4 −3

Original line number	Original line	Diff line number	Diff line
	@@ -153,10 +153,11 @@ sata_top sata_top(
	.sclk (sclk),		.sclk (sclk),
	// reliable clock to source drp and cpll lock det circuits		// reliable clock to source drp and cpll lock det circuits
	.reliable_clk (axi_aclk0),		.reliable_clk (axi_aclk0),
			.hclk (hclk),
	.sata_rst (sata_rst),		.sata_rst (sata_rst),
	.extrst (extrst),		.extrst (extrst),
	.ACLK (axi_aclk),		.ACLK (axi_aclk0),
	.ARESETN (axi_rst \| sata_rst),		.ARESETN (axi_rst/* \| sata_rst*/),
	// AXI PS Master GP1: Read Address		// AXI PS Master GP1: Read Address
	.ARADDR (ARADDR),		.ARADDR (ARADDR),
	.ARVALID (ARVALID),		.ARVALID (ARVALID),
	@@ -571,7 +572,7 @@ PS7 ps7_i (

	// AXI PS Master GP1		// AXI PS Master GP1
	// AXI PS Master GP1: Clock, Reset		// AXI PS Master GP1: Clock, Reset
	.MAXIGP1ACLK (axi_aclk), // AXI PS Master GP1 Clock , input		.MAXIGP1ACLK (axi_aclk0), // AXI PS Master GP1 Clock , input
	.MAXIGP1ARESETN (), // AXI PS Master GP1 Reset, output		.MAXIGP1ARESETN (), // AXI PS Master GP1 Reset, output
	// AXI PS Master GP1: Read Address		// AXI PS Master GP1: Read Address
	.MAXIGP1ARADDR (ARADDR), // AXI PS Master GP1 ARADDR[31:0], output		.MAXIGP1ARADDR (ARADDR), // AXI PS Master GP1 ARADDR[31:0], output

host/gtx_elastic.v

+10 −5

Original line number	Original line	Diff line number	Diff line
	@@ -64,7 +64,7 @@ localparam HI = DEPTH_LOG2 - 1; // hi bus index
	reg [22:0] ram [(1 << DEPTH_LOG2) - 1:0];		reg [22:0] ram [(1 << DEPTH_LOG2) - 1:0];
	// data to/from fifo		// data to/from fifo
	wire [22:0] inram;		wire [22:0] inram;
	wire [22:0] outram;		reg [22:0] outram;
	// adresses in their natural clock domains		// adresses in their natural clock domains
	reg [HI:0] rd_addr;		reg [HI:0] rd_addr;
	reg [HI:0] wr_addr;		reg [HI:0] wr_addr;
	@@ -142,7 +142,8 @@ endgenerate
	assign full = wr_addr == rd_addr_r + 1'b1;		assign full = wr_addr == rd_addr_r + 1'b1;
	assign empty = wr_addr_r == rd_addr;		assign empty = wr_addr_r == rd_addr;

	assign outram = ram[rd_addr];		always @ (posedge rclk)
			outram <= ram[rd_addr];

	always @ (posedge wclk)		always @ (posedge wclk)
	if (we)		if (we)
	@@ -283,7 +284,7 @@ wire clr_skip2_align;
	wire clr_wait_next_p;		wire clr_wait_next_p;
	wire clr_send_ack;		wire clr_send_ack;

	always @ (wclk)		always @ (posedge wclk)
	next_prim_loaded <= state_wait_next_p;		next_prim_loaded <= state_wait_next_p;

	assign state_bypass_rmv = ~state_wait1_align & ~state_skip1_align & ~state_wait2_align & ~state_skip2_align & ~state_wait_next_p & ~state_send_ack;		assign state_bypass_rmv = ~state_wait1_align & ~state_skip1_align & ~state_wait2_align & ~state_skip2_align & ~state_wait_next_p & ~state_send_ack;
	@@ -388,11 +389,15 @@ always @ (posedge rclk)

	// choose 1 of 2 words of ALIGNP		// choose 1 of 2 words of ALIGNP
	wire [22:0] align_word;		wire [22:0] align_word;
	assign align_word = {outram[22], 22'h007B4A} & {23{~align_altern}} \| {outram[22], 22'h014ABC} & {23{align_altern}};		assign align_word = {outram[22], 22'h007B4A} & {23{align_altern}} \| {outram[22], 22'h014ABC} & {23{~align_altern}};

			// output data would be valid the next clock they are issued
			reg pause_read_r;
			always @ (posedge rclk)
			pause_read_r <= pause_read;
	// read when compensation is not issued and when fifo gets required fullfillment		// read when compensation is not issued and when fifo gets required fullfillment
	assign re = ~pause_read & fifo_stable;		assign re = ~pause_read & fifo_stable;
	assign outdata = {23{~pause_read}} & outram \| {23{pause_read}} & align_word;		assign outdata = {23{~pause_read_r}} & outram \| {23{pause_read_r}} & align_word;
	// indicates last cycle before the next primitive		// indicates last cycle before the next primitive
	wire fword_strobe_correction;		wire fword_strobe_correction;
	reg fword_strobe;		reg fword_strobe;

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