Loading .eclipse_project_setup/.pydevproject 0 → 100644 +5 −0 Original line number Diff line number Diff line <?xml version="1.0" encoding="UTF-8" standalone="no"?> <?eclipse-pydev version="1.0"?><pydev_project> <pydev_property name="org.python.pydev.PYTHON_PROJECT_INTERPRETER">Default</pydev_property> <pydev_property name="org.python.pydev.PYTHON_PROJECT_VERSION">python 2.7</pydev_property> </pydev_project> .eclipse_project_setup/.settings/com.elphel.vdt.FPGA_project.prefs 0 → 100644 +8 −0 Original line number Diff line number Diff line FPGA_project_0_SimulationTopFile=tb/tb_top.v FPGA_project_1_SimulationTopModule=tb FPGA_project_2_ImplementationTopFile=top.v FPGA_project_3_ImplementationTopModule=top FPGA_project_4_part=xc7z030fbg484-1 FPGA_project_5_part=xc7z030fbg484-1 com.elphel.store.context.FPGA_project=FPGA_project_2_ImplementationTopFile<-@\#\#@->FPGA_project_4_part<-@\#\#@->FPGA_project_0_SimulationTopFile<-@\#\#@->FPGA_project_1_SimulationTopModule<-@\#\#@->FPGA_project_3_ImplementationTopModule<-@\#\#@->FPGA_project_5_part<-@\#\#@-> eclipse.preferences.version=1 .eclipse_project_setup/.settings/com.elphel.vdt.ISExst.prefs 0 → 100644 +4 −0 Original line number Diff line number Diff line ISExst_170_constraints=ddrc_test01.xcf ISExst_96_OtherProblems=HDLCompiler\:413<-@\#\#@-> com.elphel.store.context.ISExst=ISExst_170_constraints<-@\#\#@->ISExst_96_OtherProblems<-@\#\#@-> eclipse.preferences.version=1 .eclipse_project_setup/.settings/com.elphel.vdt.VivadoBitstream.prefs 0 → 100644 +7 −0 Original line number Diff line number Diff line VivadoBitstream_103_PreBitstreamTCL=set_property BITSTREAM.STARTUP.MATCH_CYCLE NoWait [current_design]<-@\#\#@-> VivadoBitstream_105_force=true VivadoBitstream_123_PreBitstreamTCL=set_property "BITSTREAM.STARTUP.MATCH_CYCLE" NoWait [current_design]<-@\#\#@-> VivadoBitstream_124_force=true VivadoBitstream_125_force=true com.elphel.store.context.VivadoBitstream=VivadoBitstream_105_force<-@\#\#@->VivadoBitstream_103_PreBitstreamTCL<-@\#\#@->VivadoBitstream_125_force<-@\#\#@->VivadoBitstream_124_force<-@\#\#@->VivadoBitstream_123_PreBitstreamTCL<-@\#\#@-> eclipse.preferences.version=1 .eclipse_project_setup/.settings/com.elphel.vdt.VivadoPlace.prefs 0 → 100644 +3 −0 Original line number Diff line number Diff line VivadoPlace_111_verbose_place=true com.elphel.store.context.VivadoPlace=VivadoPlace_111_verbose_place<-@\#\#@-> eclipse.preferences.version=1 Loading
.eclipse_project_setup/.pydevproject 0 → 100644 +5 −0 Original line number Diff line number Diff line <?xml version="1.0" encoding="UTF-8" standalone="no"?> <?eclipse-pydev version="1.0"?><pydev_project> <pydev_property name="org.python.pydev.PYTHON_PROJECT_INTERPRETER">Default</pydev_property> <pydev_property name="org.python.pydev.PYTHON_PROJECT_VERSION">python 2.7</pydev_property> </pydev_project>
.eclipse_project_setup/.settings/com.elphel.vdt.FPGA_project.prefs 0 → 100644 +8 −0 Original line number Diff line number Diff line FPGA_project_0_SimulationTopFile=tb/tb_top.v FPGA_project_1_SimulationTopModule=tb FPGA_project_2_ImplementationTopFile=top.v FPGA_project_3_ImplementationTopModule=top FPGA_project_4_part=xc7z030fbg484-1 FPGA_project_5_part=xc7z030fbg484-1 com.elphel.store.context.FPGA_project=FPGA_project_2_ImplementationTopFile<-@\#\#@->FPGA_project_4_part<-@\#\#@->FPGA_project_0_SimulationTopFile<-@\#\#@->FPGA_project_1_SimulationTopModule<-@\#\#@->FPGA_project_3_ImplementationTopModule<-@\#\#@->FPGA_project_5_part<-@\#\#@-> eclipse.preferences.version=1
.eclipse_project_setup/.settings/com.elphel.vdt.ISExst.prefs 0 → 100644 +4 −0 Original line number Diff line number Diff line ISExst_170_constraints=ddrc_test01.xcf ISExst_96_OtherProblems=HDLCompiler\:413<-@\#\#@-> com.elphel.store.context.ISExst=ISExst_170_constraints<-@\#\#@->ISExst_96_OtherProblems<-@\#\#@-> eclipse.preferences.version=1
.eclipse_project_setup/.settings/com.elphel.vdt.VivadoBitstream.prefs 0 → 100644 +7 −0 Original line number Diff line number Diff line VivadoBitstream_103_PreBitstreamTCL=set_property BITSTREAM.STARTUP.MATCH_CYCLE NoWait [current_design]<-@\#\#@-> VivadoBitstream_105_force=true VivadoBitstream_123_PreBitstreamTCL=set_property "BITSTREAM.STARTUP.MATCH_CYCLE" NoWait [current_design]<-@\#\#@-> VivadoBitstream_124_force=true VivadoBitstream_125_force=true com.elphel.store.context.VivadoBitstream=VivadoBitstream_105_force<-@\#\#@->VivadoBitstream_103_PreBitstreamTCL<-@\#\#@->VivadoBitstream_125_force<-@\#\#@->VivadoBitstream_124_force<-@\#\#@->VivadoBitstream_123_PreBitstreamTCL<-@\#\#@-> eclipse.preferences.version=1
.eclipse_project_setup/.settings/com.elphel.vdt.VivadoPlace.prefs 0 → 100644 +3 −0 Original line number Diff line number Diff line VivadoPlace_111_verbose_place=true com.elphel.store.context.VivadoPlace=VivadoPlace_111_verbose_place<-@\#\#@-> eclipse.preferences.version=1