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Commit 8ce6dc0e authored by Andrey Filippov's avatar Andrey Filippov
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more debugging with the AHCI driver

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.project
View file @ 8ce6dc0e
...@@ -52,87 +52,87 @@ ...@@ -52,87 +52,87 @@
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ahci/ahci_ctrl_stat.v
View file @ 8ce6dc0e
...@@ -101,6 +101,7 @@ module ahci_ctrl_stat #( ...@@ -101,6 +101,7 @@ module ahci_ctrl_stat #(
input serr_DI, // RWC: PHY Internal Error input serr_DI, // RWC: PHY Internal Error
// sirq_PRC, // sirq_PRC,
// sirq_IF || // sirq_INF // sirq_IF || // sirq_INF
input serr_EE, // RWC: Internal error (such as elastic buffer overflow or primitive mis-alignment)
input serr_EP, // RWC: Protocol Error - a violation of SATA protocol detected input serr_EP, // RWC: Protocol Error - a violation of SATA protocol detected
input serr_EC, // RWC: Persistent Communication or Data Integrity Error input serr_EC, // RWC: Persistent Communication or Data Integrity Error
input serr_ET, // RWC: Transient Data Integrity Error (error not recovered by the interface) input serr_ET, // RWC: Transient Data Integrity Error (error not recovered by the interface)
...@@ -204,7 +205,8 @@ module ahci_ctrl_stat #( ...@@ -204,7 +205,8 @@ module ahci_ctrl_stat #(
{32{serr_DW }} & HBA_PORT__PxSERR__DIAG__W__MASK | // 'h40000; {32{serr_DW }} & HBA_PORT__PxSERR__DIAG__W__MASK | // 'h40000;
{32{serr_DI }} & HBA_PORT__PxSERR__DIAG__I__MASK | // 'h20000; {32{serr_DI }} & HBA_PORT__PxSERR__DIAG__I__MASK | // 'h20000;
{32{sirq_PRC}} & HBA_PORT__PxSERR__DIAG__N__MASK | // 'h10000; {32{sirq_PRC}} & HBA_PORT__PxSERR__DIAG__N__MASK | // 'h10000;
{32{sirq_IF | sirq_INF }} & HBA_PORT__PxSERR__ERR__E__MASK | // 'h800; // {32{sirq_IF | sirq_INF }} & HBA_PORT__PxSERR__ERR__E__MASK | // 'h800;
{32{serr_EE}} & HBA_PORT__PxSERR__ERR__E__MASK | // 'h800;
{32{serr_EP }} & HBA_PORT__PxSERR__ERR__P__MASK | // 'h400; {32{serr_EP }} & HBA_PORT__PxSERR__ERR__P__MASK | // 'h400;
{32{serr_EC }} & HBA_PORT__PxSERR__ERR__C__MASK | // 'h200; {32{serr_EC }} & HBA_PORT__PxSERR__ERR__C__MASK | // 'h200;
......
ahci/ahci_fsm.v
View file @ 8ce6dc0e
...@@ -56,7 +56,7 @@ module ahci_fsm ...@@ -56,7 +56,7 @@ module ahci_fsm
// Communication with ahci_ctrl_stat (some are not needed) // Communication with ahci_ctrl_stat (some are not needed)
// update register inputs (will write to register memory current value of the corresponding register) // update register inputs (will write to register memory current value of the corresponding register)
output pfsm_started, // H: FSM doene, P: FSM started (enable sensing pcmd_st_cleared) output pfsm_started, // H: FSM done, P: FSM started (enable sensing pcmd_st_cleared)
// update register inputs (will write to register memory current value of the corresponding register) // update register inputs (will write to register memory current value of the corresponding register)
// Removing - such updates are always done when startimng new state // Removing - such updates are always done when startimng new state
/// input update_pending, /// input update_pending,
...@@ -281,7 +281,7 @@ module ahci_fsm ...@@ -281,7 +281,7 @@ module ahci_fsm
reg [1:0] async_pend_r; // waiting to process cominit_got reg [1:0] async_pend_r; // waiting to process cominit_got
reg async_from_st; // chnge to multi-bit if there will be more sources for async transitions reg async_from_st; // chnge to multi-bit if there will be more sources for async transitions
wire asynq_rq = cominit_got || pcmd_st_cleared; wire asynq_rq = (cominit_got && unsolicited_cominit_en) || pcmd_st_cleared;
// OK to wait for some time fsm_act_busy is supposed to never hang up // OK to wait for some time fsm_act_busy is supposed to never hang up
wire async_ackn = !fsm_preload && async_pend_r[0] && ((fsm_actions && !update_busy && !fsm_act_busy) || fsm_transitions[0]); // OK to process async jump wire async_ackn = !fsm_preload && async_pend_r[0] && ((fsm_actions && !update_busy && !fsm_act_busy) || fsm_transitions[0]); // OK to process async jump
// reg x_rdy_collision_pend; // reg x_rdy_collision_pend;
...@@ -297,7 +297,8 @@ module ahci_fsm ...@@ -297,7 +297,8 @@ module ahci_fsm
wire conditions_ce = // copy all conditions to the register so they will not change while iterating through them wire conditions_ce = // copy all conditions to the register so they will not change while iterating through them
!fsm_transitions_w && !fsm_transitions[0]; !fsm_transitions_w && !fsm_transitions[0];
reg unsolicited_cominit_en; // allow unsolicited COMINITs
wire en_cominit; // en_cominit
assign fsm_next = (fsm_preload || (fsm_actions && !update_busy && !fsm_act_busy) || fsm_transitions[0]) && !async_pend_r[0]; // quiet if received cominit is pending assign fsm_next = (fsm_preload || (fsm_actions && !update_busy && !fsm_act_busy) || fsm_transitions[0]) && !async_pend_r[0]; // quiet if received cominit is pending
assign update_all = fsm_jump[0]; assign update_all = fsm_jump[0];
...@@ -336,6 +337,10 @@ module ahci_fsm ...@@ -336,6 +337,10 @@ module ahci_fsm
localparam LABEL_ST_CLEARED = 11'h008; localparam LABEL_ST_CLEARED = 11'h008;
always @ (posedge mclk) begin always @ (posedge mclk) begin
if (hba_rst) unsolicited_cominit_en <= !was_port_rst;
// else if (en_cominit || comreset_send) unsolicited_cominit_en <= en_cominit;
if (hba_rst) pgm_jump_addr <= (was_hba_rst || was_port_rst) ? (was_hba_rst? LABEL_HBA_RST:LABEL_PORT_RST) : LABEL_POR; if (hba_rst) pgm_jump_addr <= (was_hba_rst || was_port_rst) ? (was_hba_rst? LABEL_HBA_RST:LABEL_PORT_RST) : LABEL_POR;
// else if (async_pend_r[1]) pgm_jump_addr <= async_from_st? LABEL_ST_CLEARED : LABEL_COMINIT; // else if (async_pend_r[1]) pgm_jump_addr <= async_from_st? LABEL_ST_CLEARED : LABEL_COMINIT;
else if (async_pend_r[0]) pgm_jump_addr <= async_from_st? LABEL_ST_CLEARED : LABEL_COMINIT; else if (async_pend_r[0]) pgm_jump_addr <= async_from_st? LABEL_ST_CLEARED : LABEL_COMINIT;
...@@ -462,6 +467,7 @@ module ahci_fsm ...@@ -462,6 +467,7 @@ module ahci_fsm
.SET_OFFLINE (set_offline), // output reg .SET_OFFLINE (set_offline), // output reg
.R_OK (send_R_OK), // output reg .R_OK (send_R_OK), // output reg
.R_ERR (send_R_ERR), // output reg .R_ERR (send_R_ERR), // output reg
.EN_COMINIT (en_cominit), // output reg
// FIS TRANSMIT/WAIT DONE // FIS TRANSMIT/WAIT DONE
.FETCH_CMD (fetch_cmd), // output reg .FETCH_CMD (fetch_cmd), // output reg
.ATAPI_XMIT (atapi_xmit), // output reg .ATAPI_XMIT (atapi_xmit), // output reg
......
ahci/ahci_sata_layers.v
View file @ 8ce6dc0e
...@@ -81,7 +81,7 @@ module ahci_sata_layers #( ...@@ -81,7 +81,7 @@ module ahci_sata_layers #(
output serr_DW, // RWC: COMMWAKE signal was detected output serr_DW, // RWC: COMMWAKE signal was detected
output serr_DI, // RWC: PHY Internal Error output serr_DI, // RWC: PHY Internal Error
// sirq_PRC, // sirq_PRC,
// sirq_IF || // sirq_INF output serr_EE, // RWC: Internal error (such as elastic buffer overflow or primitive mis-alignment)
output serr_EP, // RWC: Protocol Error - a violation of SATA protocol detected output serr_EP, // RWC: Protocol Error - a violation of SATA protocol detected
output serr_EC, // RWC: Persistent Communication or Data Integrity Error output serr_EC, // RWC: Persistent Communication or Data Integrity Error
output serr_ET, // RWC: Transient Data Integrity Error (error not recovered by the interface) output serr_ET, // RWC: Transient Data Integrity Error (error not recovered by the interface)
...@@ -246,8 +246,9 @@ module ahci_sata_layers #( ...@@ -246,8 +246,9 @@ module ahci_sata_layers #(
// assign serr_DS = phy_ready && (0); // RWC: Link sequence error // assign serr_DS = phy_ready && (0); // RWC: Link sequence error
// assign serr_DC = phy_ready && (0); // RWC: CRC error in Link layer // assign serr_DC = phy_ready && (0); // RWC: CRC error in Link layer
// assign serr_DB = phy_ready && (0); // RWC: 10B to 8B decode error // assign serr_DB = phy_ready && (0); // RWC: 10B to 8B decode error
assign serr_DI = phy_ready && (rxelsfull); // RWC: PHY Internal Error // just debugging assign serr_EE = phy_ready && (rxelsfull || rxelsempty);
assign serr_EP = phy_ready && (rxelsempty); // RWC: Protocol Error - a violation of SATA protocol detected // just debugging assign serr_DI = phy_ready && (0); // rxelsfull); // RWC: PHY Internal Error // just debugging
assign serr_EP = phy_ready && (0); // rxelsempty); // RWC: Protocol Error - a violation of SATA protocol detected // just debugging
assign serr_EC = phy_ready && (0); // RWC: Persistent Communication or Data Integrity Error assign serr_EC = phy_ready && (0); // RWC: Persistent Communication or Data Integrity Error
assign serr_ET = phy_ready && (0); // RWC: Transient Data Integrity Error (error not recovered by the interface) assign serr_ET = phy_ready && (0); // RWC: Transient Data Integrity Error (error not recovered by the interface)
assign serr_EM = phy_ready && (0); // RWC: Communication between the device and host was lost but re-established assign serr_EM = phy_ready && (0); // RWC: Communication between the device and host was lost but re-established
......
ahci/ahci_top.v
View file @ 8ce6dc0e
...@@ -172,6 +172,7 @@ module ahci_top#( ...@@ -172,6 +172,7 @@ module ahci_top#(
input serr_DI, // RWC: PHY Internal Error input serr_DI, // RWC: PHY Internal Error
// sirq_PRC, // sirq_PRC,
// sirq_IF || // sirq_INF // sirq_IF || // sirq_INF
input serr_EE, // RWC: Internal error (such as elastic buffer overflow or primitive mis-alignment)
input serr_EP, // RWC: Protocol Error - a violation of SATA protocol detected input serr_EP, // RWC: Protocol Error - a violation of SATA protocol detected
input serr_EC, // RWC: Persistent Communication or Data Integrity Error input serr_EC, // RWC: Persistent Communication or Data Integrity Error
input serr_ET, // RWC: Transient Data Integrity Error (error not recovered by the interface) input serr_ET, // RWC: Transient Data Integrity Error (error not recovered by the interface)
...@@ -476,10 +477,16 @@ module ahci_top#( ...@@ -476,10 +477,16 @@ module ahci_top#(
wire pxci0; // pxCI current value wire pxci0; // pxCI current value
wire hba_rst_done; // HBA reset done - clear GHC.HR (and some other regs) wire hba_rst_done; // HBA reset done - clear GHC.HR (and some other regs)
wire comreset_send0; // just disabling it
wire [9:0] last_jump_addr; wire [9:0] last_jump_addr;
wire [31:0] debug_dma; wire [31:0] debug_dma;
wire [31:0] debug_dma1; wire [31:0] debug_dma1;
wire [31:0] debug_dma_h2d; wire [31:0] debug_dma_h2d;
assign comreset_send = comreset_send0 && 0;
// Async FF // Async FF
always @ (posedge mrst or posedge mclk) begin always @ (posedge mrst or posedge mclk) begin
if (mrst) en_port <= 0; if (mrst) en_port <= 0;
...@@ -518,7 +525,7 @@ module ahci_top#( ...@@ -518,7 +525,7 @@ module ahci_top#(
.phy_ready (phy_ready), // input .phy_ready (phy_ready), // input
.syncesc_send (syncesc_send), // output .syncesc_send (syncesc_send), // output
.comreset_send (comreset_send), // output .comreset_send (comreset_send0), // output
.syncesc_send_done (syncesc_send_done), // input .syncesc_send_done (syncesc_send_done), // input
.cominit_got (cominit_got), // input .cominit_got (cominit_got), // input
.set_offline (set_offline), // output .set_offline (set_offline), // output
...@@ -834,6 +841,7 @@ wire[1:0] debug_get_fis_busy_r; // output[1:0] ...@@ -834,6 +841,7 @@ wire[1:0] debug_get_fis_busy_r; // output[1:0]
.serr_DB (serr_DB), // input .serr_DB (serr_DB), // input
.serr_DW (serr_DW), // input .serr_DW (serr_DW), // input
.serr_DI (serr_DI), // input .serr_DI (serr_DI), // input
.serr_EE (serr_EE), // input
.serr_EP (serr_EP), // input .serr_EP (serr_EP), // input
.serr_EC (serr_EC), // input .serr_EC (serr_EC), // input
.serr_ET (serr_ET), // input .serr_ET (serr_ET), // input
......
ahci/sata_ahci_top.v
View file @ 8ce6dc0e
...@@ -222,7 +222,7 @@ ...@@ -222,7 +222,7 @@
wire serr_DW; // RWC: COMMWAKE signal was detected wire serr_DW; // RWC: COMMWAKE signal was detected
wire serr_DI; // RWC: PHY Internal Error wire serr_DI; // RWC: PHY Internal Error
// sirq_PRC, // sirq_PRC,
// sirq_IF || // sirq_INF wire serr_EE; // RWC: Internal error (such as elastic buffer overflow or primitive mis-alignment)
wire serr_EP; // RWC: Protocol Error - a violation of SATA protocol detected wire serr_EP; // RWC: Protocol Error - a violation of SATA protocol detected
wire serr_EC; // RWC: Persistent Communication or Data Integrity Error wire serr_EC; // RWC: Persistent Communication or Data Integrity Error
wire serr_ET; // RWC: Transient Data Integrity Error (error not recovered by the interface) wire serr_ET; // RWC: Transient Data Integrity Error (error not recovered by the interface)
...@@ -389,6 +389,7 @@ ...@@ -389,6 +389,7 @@
.serr_DB (serr_DB), // input .serr_DB (serr_DB), // input
.serr_DW (serr_DW), // input .serr_DW (serr_DW), // input
.serr_DI (serr_DI), // input .serr_DI (serr_DI), // input
.serr_EE (serr_EE), // input
.serr_EP (serr_EP), // input .serr_EP (serr_EP), // input
.serr_EC (serr_EC), // input .serr_EC (serr_EC), // input
.serr_ET (serr_ET), // input .serr_ET (serr_ET), // input
...@@ -469,6 +470,7 @@ ...@@ -469,6 +470,7 @@
.serr_DB (serr_DB), // output .serr_DB (serr_DB), // output
.serr_DW (serr_DW), // output .serr_DW (serr_DW), // output
.serr_DI (serr_DI), // output .serr_DI (serr_DI), // output
.serr_EE (serr_EE), // output
.serr_EP (serr_EP), // output .serr_EP (serr_EP), // output
.serr_EC (serr_EC), // output .serr_EC (serr_EC), // output
.serr_ET (serr_ET), // output .serr_ET (serr_ET), // output
......
generated/action_decoder.v
View file @ 8ce6dc0e
/******************************************************************************* /*******************************************************************************
* Module: action_decoder * Module: action_decoder
* Date:2016-02-20 * Date:2016-02-22
* Author: auto-generated file, see ahci_fsm_sequence.py * Author: auto-generated file, see ahci_fsm_sequence.py
* Description: Decode sequencer code to 1-hot actions * Description: Decode sequencer code to 1-hot actions
*******************************************************************************/ *******************************************************************************/
...@@ -51,6 +51,7 @@ module action_decoder ( ...@@ -51,6 +51,7 @@ module action_decoder (
output reg SET_OFFLINE, output reg SET_OFFLINE,
output reg R_OK, output reg R_OK,
output reg R_ERR, output reg R_ERR,
output reg EN_COMINIT,
output reg FETCH_CMD, output reg FETCH_CMD,
output reg ATAPI_XMIT, output reg ATAPI_XMIT,
output reg CFIS_XMIT, output reg CFIS_XMIT,
...@@ -104,16 +105,17 @@ module action_decoder ( ...@@ -104,16 +105,17 @@ module action_decoder (
SET_OFFLINE <= enable && data[ 8] && data[ 4]; SET_OFFLINE <= enable && data[ 8] && data[ 4];
R_OK <= enable && data[ 9] && data[ 4]; R_OK <= enable && data[ 9] && data[ 4];
R_ERR <= enable && data[10] && data[ 4]; R_ERR <= enable && data[10] && data[ 4];
FETCH_CMD <= enable && data[ 6] && data[ 5]; EN_COMINIT <= enable && data[ 6] && data[ 5];
ATAPI_XMIT <= enable && data[ 7] && data[ 5]; FETCH_CMD <= enable && data[ 7] && data[ 5];
CFIS_XMIT <= enable && data[ 8] && data[ 5]; ATAPI_XMIT <= enable && data[ 8] && data[ 5];
DX_XMIT <= enable && data[ 9] && data[ 5]; CFIS_XMIT <= enable && data[ 9] && data[ 5];
GET_DATA_FIS <= enable && data[10] && data[ 5]; DX_XMIT <= enable && data[10] && data[ 5];
GET_DSFIS <= enable && data[ 7] && data[ 6]; GET_DATA_FIS <= enable && data[ 7] && data[ 6];
GET_IGNORE <= enable && data[ 8] && data[ 6]; GET_DSFIS <= enable && data[ 8] && data[ 6];
GET_PSFIS <= enable && data[ 9] && data[ 6]; GET_IGNORE <= enable && data[ 9] && data[ 6];
GET_RFIS <= enable && data[10] && data[ 6]; GET_PSFIS <= enable && data[10] && data[ 6];
GET_SDBFIS <= enable && data[ 8] && data[ 7]; GET_RFIS <= enable && data[ 8] && data[ 7];
GET_UFIS <= enable && data[ 9] && data[ 7]; GET_SDBFIS <= enable && data[ 9] && data[ 7];
GET_UFIS <= enable && data[10] && data[ 7];
end end
endmodule endmodule
generated/condition_mux.v
View file @ 8ce6dc0e
/******************************************************************************* /*******************************************************************************
* Module: condition_mux * Module: condition_mux
* Date:2016-02-20 * Date:2016-02-22
* Author: auto-generated file, see ahci_fsm_sequence.py * Author: auto-generated file, see ahci_fsm_sequence.py
* Description: Select condition * Description: Select condition
*******************************************************************************/ *******************************************************************************/
......
helpers/ahci_fsm_sequence.py
View file @ 8ce6dc0e
...@@ -56,7 +56,10 @@ actions = ['NOP', ...@@ -56,7 +56,10 @@ actions = ['NOP',
# DMA # DMA
'DMA_ABORT*', 'DMA_PRD_IRQ_CLEAR', 'DMA_ABORT*', 'DMA_PRD_IRQ_CLEAR',
# SATA TRANSPORT/LINK/PHY # SATA TRANSPORT/LINK/PHY
'XMIT_COMRESET', 'SEND_SYNC_ESC*', 'SET_OFFLINE', 'R_OK', 'R_ERR', 'XMIT_COMRESET', # temporary - just disables unsolicited COMINIT
'SEND_SYNC_ESC*', 'SET_OFFLINE', 'R_OK', 'R_ERR',
'EN_COMINIT',
# FIS TRANSMIT/WAIT DONE # FIS TRANSMIT/WAIT DONE
'FETCH_CMD*', 'ATAPI_XMIT*', 'CFIS_XMIT*', 'DX_XMIT*', 'FETCH_CMD*', 'ATAPI_XMIT*', 'CFIS_XMIT*', 'DX_XMIT*',
#FIS RECEIVE/WAIT DONE #FIS RECEIVE/WAIT DONE
...@@ -119,7 +122,7 @@ sequence = [{LBL:'POR', ADDR: 0x0, ACT: NOP}, ...@@ -119,7 +122,7 @@ sequence = [{LBL:'POR', ADDR: 0x0, ACT: NOP},
#TODO - add to some error? Now silently skips #TODO - add to some error? Now silently skips
{ GOTO:'P:NotRunning'}, { GOTO:'P:NotRunning'},
{LBL:'P:NotRunning', ACT: 'NOP'}, # 'PXCI0_CLEAR'}, # pxci0_clear, - should not be here as it updates soft registers? {LBL:'P:NotRunning', ACT: 'EN_COMINIT'}, # Enable unsolicited cominit 'PXCI0_CLEAR'}, # pxci0_clear, - should not be here as it updates soft registers?
{IF: 'FIS_FIRST_INVALID', GOTO:'P:NotRunningGarbage'}, {IF: 'FIS_FIRST_INVALID', GOTO:'P:NotRunningGarbage'},
{IF:'SCTL_DET_CHANGED_TO_4',GOTO:'P:Offline'}, #4 {IF:'SCTL_DET_CHANGED_TO_4',GOTO:'P:Offline'}, #4
{IF:'SCTL_DET_CHANGED_TO_1',GOTO:'P:StartComm'}, #5 {IF:'SCTL_DET_CHANGED_TO_1',GOTO:'P:StartComm'}, #5
......
includes/ahxi_fsm_code.vh
View file @ 8ce6dc0e
, .INIT_00 (256'h00100000000E0000000C02020035000000220000000C0000000A0000000C0000) , .INIT_00 (256'h00100000000E0000000C02020035000000220000000C0000000A0000000C0000)
, .INIT_01 (256'h1C3B9448543244190000001B0108001B00500402040401040022000600120000) , .INIT_01 (256'h1C3B9448543244190060001B0108001B00500402040401040022000600120000)
, .INIT_02 (256'h001BC8300014000C0210002B24FD25050440001B0003004200180000001B4454) , .INIT_02 (256'h001BC8300014000C0210002B24FD25050180001B0003004200180000001B4454)
, .INIT_03 (256'h44394C6A2C44141B0012003B01080028000A04080022001B01020110001B0005) , .INIT_03 (256'h44394C6A2C44141B0012003B01080028000A04080022001B01020110001B0005)
, .INIT_04 (256'h003B0210001B14480102005004020404003BB07F707C0060003B8C6D845484C0) , .INIT_04 (256'h003B0210001B14480102005004020404003BB07F707C00A0003B8C6D845484C0)
, .INIT_05 (256'h045A0000005024FD25050140004E24FD25050140005E0000003B0000001B0210) , .INIT_05 (256'h045A0000005024FD25050240004E24FD25050240005E0000003B0000001B0210)
, .INIT_06 (256'h903B01200204006D0402009000E4A89568F218EB18CD98A958D9388464560C27) , .INIT_06 (256'h903B02200204006D0402009000E4A89568F218EB18CD98A958D9388464560C27)
, .INIT_07 (256'h0000003BB07F0000005200840022003BB07F707C307930F202080073D10750FA) , .INIT_07 (256'h0000003BB07F0000005200840022003BB07F707C307930F202080073D10750FA)
, .INIT_08 (256'hC891002200440093288D290100140210008824FD25050440009ED0FF00A0003B) , .INIT_08 (256'hC891002200440093288D290100140210008824FD25050180009ED0FF0120003B)
, .INIT_09 (256'h29010024003B48810CAF29010210009924FD250502400052000C009300050093) , .INIT_09 (256'h29010024003B48810CAF29010210009924FD250504400052000C009300050093)
, .INIT_0A (256'h003000AF021000AD24FD2505014000520081005248A700220044003B48A728A3) , .INIT_0A (256'h003000AF021000AD24FD2505024000520081005248A700220044003B48A728A3)
, .INIT_0B (256'h003B889E00300009003B889E50BC0044008800B7D0FF50FA022000B3883B089E) , .INIT_0B (256'h003B889E00300009003B889E50BC0044008800B7D0FF50FA042000B3883B089E)
, .INIT_0C (256'h24FD250500C0003B889E50BC00440048021000C7C50524FD24FD042000C20030) , .INIT_0C (256'h24FD25050140003B889E50BC00440048021000C7C50524FD24FD00C000C20030)
, .INIT_0D (256'h29010014021000DD24FD25050180003B34D4000000D6001100D6C8D4021000D1) , .INIT_0D (256'h29010014021000DD24FD25050280003B34D4000000D6001100D6C8D4021000D1)
, .INIT_0E (256'h021000EF24FD25050140003B0401021000E824FD25050280005201010052C8E2) , .INIT_0E (256'h021000EF24FD25050240003B0401021000E824FD25050480005201010052C8E2)
, .INIT_0F (256'h002100FF041001030021008400F8000000F8021000F624FD2505014000F80082) , .INIT_0F (256'h002100FF041001030021008400F8000000F8021000F624FD2505024000F80082)
, .INIT_10 (256'h0000000000000000000000000000003B00410107041001030000010302010103) , .INIT_10 (256'h0000000000000000000000000000003B00410107041001030000010302010103)
, .INITP_00 (256'h8220098170902401E272722222800309418810820809C8020188800222222222) , .INITP_00 (256'h8220098170902401E272722222800309418810820809C8020188800222222222)
, .INITP_01 (256'h8882227209C82720A09C22089C680272181A01CB889C8605A2A89C882068270C) , .INITP_01 (256'h8882227209C82720A09C22089C680272181A01CB889C8605A2A89C882068270C)
......
py393sata/x393sata.py
View file @ 8ce6dc0e
...@@ -1083,6 +1083,10 @@ sata.reg_status(),sata.reset_ie(),sata.err_count() ...@@ -1083,6 +1083,10 @@ sata.reg_status(),sata.reset_ie(),sata.err_count()
_=mem.mem_dump (0x80000ff0, 4,4) _=mem.mem_dump (0x80000ff0, 4,4)
_=mem.mem_dump (0x80001000, 0x120,4) _=mem.mem_dump (0x80001000, 0x120,4)
hex(sata.get_reg_address('HBA_PORT__PxSCTL'))
mem.write_mem(0x8000012c,1)
mem.write_mem(0x8000012c,0)
hex(mem.read_mem(0x8000012c))
......
tb/tb_ahci.tf
View file @ 8ce6dc0e
...@@ -416,7 +416,8 @@ top dut( ...@@ -416,7 +416,8 @@ top dut(
assign device_rst = dut.axi_rst; assign device_rst = dut.axi_rst;
sata_device dev( sata_device dev(
.rst (1'b1), // FOREVER device_rst), // .rst (1'b1), // FOREVER device_rst),
.rst (device_rst),
.RXN (txn), .RXN (txn),
.RXP (txp), .RXP (txp),
.TXN (rxn), .TXN (rxn),
...@@ -1284,12 +1285,13 @@ initial begin //Host ...@@ -1284,12 +1285,13 @@ initial begin //Host
maxigp1_print ('h1014,"DATASCOPE 5"); // maxigp1_print ('h1014,"DATASCOPE 5"); //
maxigp1_print ('h1018,"DATASCOPE 6"); // maxigp1_print ('h1018,"DATASCOPE 6"); //
maxigp1_print ('h101c,"DATASCOPE 7"); // maxigp1_print ('h101c,"DATASCOPE 7"); //
/*
// Reset HBA // Reset HBA
maxigp1_writep (GHC__GHC__HR__ADDR << 2, 1); // Reset HBA maxigp1_writep (GHC__GHC__HR__ADDR << 2, 1); // Reset HBA
#12000; #12000;
@(posedge CLK); @(posedge CLK);
maxigp1_print (GHC__GHC__HR__ADDR << 2,"GHC__GHC__HR__ADDR after pause"); maxigp1_print (GHC__GHC__HR__ADDR << 2,"GHC__GHC__HR__ADDR after pause");
/* */
// Reset port // Reset port
maxigp1_print ('h3ff << 2,"DEBUG_REGISTER"); maxigp1_print ('h3ff << 2,"DEBUG_REGISTER");
maxigp1_writep (HBA_PORT__PxSCTL__DET__ADDR << 2, 1); // Reset SATA maxigp1_writep (HBA_PORT__PxSCTL__DET__ADDR << 2, 1); // Reset SATA
...@@ -1299,7 +1301,6 @@ initial begin //Host ...@@ -1299,7 +1301,6 @@ initial begin //Host
maxigp1_writep (HBA_PORT__PxSCTL__DET__ADDR << 2, 0); // Reset Off maxigp1_writep (HBA_PORT__PxSCTL__DET__ADDR << 2, 0); // Reset Off
repeat (1000) @(posedge CLK); repeat (1000) @(posedge CLK);
maxigp1_print ('h3ff << 2,"DEBUG_REGISTER"); maxigp1_print ('h3ff << 2,"DEBUG_REGISTER");
*/
//DET //DET
// $finish; // $finish;
//HBA_PORT__PxIE__DHRE__MASK = 'h1; //HBA_PORT__PxIE__DHRE__MASK = 'h1;
......
tb_ahci_01.sav
View file @ 8ce6dc0e
[*] [*]
[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI [*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
[*] Mon Feb 22 22:05:23 2016 [*] Tue Feb 23 00:04:34 2016
[*] [*]
[dumpfile] "/home/andrey/git/x393_sata/simulation/tb_ahci-20160222132932478.fst" [dumpfile] "/home/andrey/git/x393_sata/simulation/tb_ahci-20160222150448690.fst"
[dumpfile_mtime] "Mon Feb 22 20:31:27 2016" [dumpfile_mtime] "Mon Feb 22 22:05:55 2016"
[dumpfile_size] 14406416 [dumpfile_size] 7768068
[savefile] "/home/andrey/git/x393_sata/tb_ahci_01.sav" [savefile] "/home/andrey/git/x393_sata/tb_ahci_01.sav"
[timestart] 48630000 [timestart] 35797800
[size] 1823 1180 [size] 1823 1173
[pos] 2026 0 [pos] 2026 0
*-23.135801 73732102 62346574 72998842 74025406 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 *-15.135801 35895886 62346574 72998842 74025406 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] tb_ahci. [treeopen] tb_ahci.
[treeopen] tb_ahci.axi_read_addr. [treeopen] tb_ahci.axi_read_addr.
[treeopen] tb_ahci.dev.linkMonitorFIS. [treeopen] tb_ahci.dev.linkMonitorFIS.
...@@ -28,6 +28,7 @@ ...@@ -28,6 +28,7 @@
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.link. [treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.link.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.link.crc. [treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.link.crc.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.link.scrambler. [treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.link.scrambler.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap. [treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1. [treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper. [treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.
...@@ -1586,7 +1587,7 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_g ...@@ -1586,7 +1587,7 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_g
-drp -drp
@1401200 @1401200
-axi_ahci_regs -axi_ahci_regs
@c00200 @800200
-ahci_fsm -ahci_fsm
@28 @28
tb_ahci.dut.sata_top.ahci_top_i.hba_arst tb_ahci.dut.sata_top.ahci_top_i.hba_arst
...@@ -1609,7 +1610,7 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.async_pend_r[1:0] ...@@ -1609,7 +1610,7 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.async_pend_r[1:0]
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.async_ackn tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.async_ackn
@1401200 @1401200
-group_end -group_end
@c00022 @c00023
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pgm_addr[9:0] tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pgm_addr[9:0]
@28 @28
(0)tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pgm_addr[9:0] (0)tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pgm_addr[9:0]
...@@ -1622,7 +1623,7 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pgm_addr[9:0] ...@@ -1622,7 +1623,7 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pgm_addr[9:0]
(7)tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pgm_addr[9:0] (7)tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pgm_addr[9:0]
(8)tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pgm_addr[9:0] (8)tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pgm_addr[9:0]
(9)tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pgm_addr[9:0] (9)tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pgm_addr[9:0]
@1401200 @1401201
-group_end -group_end
@c00022 @c00022
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pgm_data[17:0] tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pgm_data[17:0]
...@@ -1860,7 +1861,7 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.async_pend_r[1:0] ...@@ -1860,7 +1861,7 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.async_pend_r[1:0]
@28 @28
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.async_ackn tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.async_ackn
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.async_from_st tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.async_from_st
@1401200 @1000200
-ahci_fsm -ahci_fsm
@c00200 @c00200
-ahci_fis_receive -ahci_fis_receive
...@@ -4141,7 +4142,7 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.link.frame_ack ...@@ -4141,7 +4142,7 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.link.frame_ack
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.frame_busy tb_ahci.dut.sata_top.ahci_sata_layers_i.link.frame_busy
@1401200 @1401200
-link -link
@c00201 @c00200
-phy -phy
@800200 @800200
-gtx_8x10enc -gtx_8x10enc
...@@ -4309,7 +4310,6 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_g ...@@ -4309,7 +4310,6 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_g
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.channel.rx.dataiface.wordcounter[31:0] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.channel.rx.dataiface.wordcounter[31:0]
@1401200 @1401200
-GTXE2_GPL -GTXE2_GPL
@1401201
-phy -phy
@c00200 @c00200
-comma -comma
...@@ -4521,6 +4521,10 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtx_comma_align.window[38:0 ...@@ -4521,6 +4521,10 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtx_comma_align.window[38:0
-comma_align -comma_align
@800200 @800200
-debug_cominit -debug_cominit
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.TXCOMINIT
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.TXCOMFINISH
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.txcominit
@200 @200
- -
@22 @22
......
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