modifying RX input settings (78da3183) · Commits · Elphel / x393_sata

.project

+17 −17

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		@@ -52,87 +52,87 @@
		<link>
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ahci/ahci_sata_layers.v

+28 −3

Original line number	Diff line number	Diff line
		@@ -21,6 +21,11 @@
		`timescale 1ns/1ps

		module ahci_sata_layers #(
		`ifdef USE_DATASCOPE
		parameter ADDRESS_BITS = 10, //for datascope
		parameter DATASCOPE_START_BIT = 14, // bit of DRP "other_control" to start recording after 0->1 (needs DRP)
		parameter DATASCOPE_POST_MEAS = 16, // number of measurements to perform after event
		`endif
		parameter BITS_TO_START_XMIT = 6, // wait H2D FIFO to have 1 << BITS_TO_START_XMIT to start FIS transmission (or all FIS fits)
		parameter DATA_BYTE_WIDTH = 4
		)(
		@@ -91,6 +96,14 @@ module ahci_sata_layers #(
		output wire txn_out,
		input wire rxp_in,
		input wire rxn_in,
		`ifdef USE_DATASCOPE
		// Datascope interface (write to memory that can be software-read)
		output datascope_clk,
		output [ADDRESS_BITS-1:0] datascope_waddr,
		output datascope_we,
		output [31:0] datascope_di,
		`endif

		`ifdef USE_DRP
		input drp_rst,
		input drp_clk,
		@@ -320,6 +333,11 @@ module ahci_sata_layers #(


		sata_phy #(
		`ifdef USE_DATASCOPE
		.ADDRESS_BITS (ADDRESS_BITS), // for datascope
		.DATASCOPE_START_BIT (DATASCOPE_START_BIT),
		.DATASCOPE_POST_MEAS (DATASCOPE_POST_MEAS),
		`endif
		.DATA_BYTE_WIDTH(4)
		) phy (
		.extrst (exrst), // input wire
		@@ -351,6 +369,13 @@ module ahci_sata_layers #(
		.usrpll_locked_debug(),
		.re_aligned (serr_DS), // output reg

		`ifdef USE_DATASCOPE
		.datascope_clk (datascope_clk), // output
		.datascope_waddr (datascope_waddr), // output[9:0]
		.datascope_we (datascope_we), // output
		.datascope_di (datascope_di), // output[31:0]
		.datascope_trig (ll_frame_ackn), // input datascope external trigger
		`endif

		`ifdef USE_DRP
		.drp_rst (drp_rst), // input

ahci/ahci_top.v

+19 −2

Original line number	Diff line number	Diff line
		@@ -182,6 +182,16 @@ module ahci_top#(


		output irq, // CPU interrupt request

		`ifdef USE_DATASCOPE
		// Datascope interface (write to memory that can be software-read)
		input datascope1_clk,
		input [ADDRESS_BITS-1:0] datascope1_waddr,
		input datascope1_we,
		input [31:0] datascope1_di,
		`endif


		`ifdef USE_DRP
		output drp_en, // @aclk strobes drp_ad
		output drp_we,
		@@ -715,7 +725,9 @@ module ahci_top#(
		.debug_in0 (debug_dma), // input[31:0]
		.debug_in1 (debug_dma1), // debug_in_link), // input[31:0]
		.debug_in2 (debug_in_phy), // input[31:0] // debug from phy/link
		.debug_in3 ({22'b0, last_jump_addr[9:0]}) // input[31:0]// Last jump address in the AHDCI sequencer
		// .debug_in3 ({22'b0, last_jump_addr[9:0]}) // input[31:0]// Last jump address in the AHDCI sequencer
		.debug_in3 ({3'b0, debug_in_link[4:0], 14'b0,last_jump_addr[9:0]}) // input[31:0]// Last jump address in the AHDCI sequencer

		`ifdef USE_DRP
		,.drp_en (drp_en), // output reg
		.drp_we (drp_we), // output reg
		@@ -730,7 +742,12 @@ module ahci_top#(
		,.datascope_clk (datascope_clk), // input
		.datascope_waddr (datascope_waddr), // input[9:0]
		.datascope_we (datascope_we), // input
		.datascope_di (datascope_di) // input[31:0]
		.datascope_di (datascope_di), // input[31:0]

		.datascope1_clk (datascope1_clk), // input
		.datascope1_waddr (datascope1_waddr),// input[9:0]
		.datascope1_we (datascope1_we), // input
		.datascope1_di (datascope1_di) // input[31:0]
		`endif
		/// .debug_in (debug_in[31:0])
		);

ahci/axi_ahci_regs.v

+33 −4

Original line number	Diff line number	Diff line
		@@ -132,7 +132,12 @@ module axi_ahci_regs#(
		,input datascope_clk,
		input [ADDRESS_BITS-1:0] datascope_waddr,
		input datascope_we,
		input [31:0] datascope_di
		input [31:0] datascope_di,

		input datascope1_clk,
		input [ADDRESS_BITS-1:0] datascope1_waddr,
		input datascope1_we,
		input [31:0] datascope1_di
		`endif
		);
		`ifdef USE_DRP
		@@ -142,11 +147,15 @@ module axi_ahci_regs#(
		reg drp_ready_r;
		`endif
		`ifdef USE_DATASCOPE
		localparam AXIBRAM_BITS = ADDRESS_BITS + 1; // number of axi address outputs (one more than ADDRESS_BITS when using datascope)
		// localparam AXIBRAM_BITS = ADDRESS_BITS + 1; // number of axi address outputs (one more than ADDRESS_BITS when using datascope)
		localparam AXIBRAM_BITS = ADDRESS_BITS + 2; // number of axi address outputs (one more than ADDRESS_BITS when using datascope)
		wire [31:0] datascope_rdata;
		reg [1:0] datascope_sel; // read datascope memory instead of the registers
		wire [31:0] datascope1_rdata;
		reg [1:0] datascope1_sel; // read datascope memory instead of the registers
		always @ (posedge aclk) begin
		datascope_sel <= {datascope_sel[0], bram_raddr[ADDRESS_BITS]};
		datascope_sel <= {datascope_sel[0], ~bram_raddr[ADDRESS_BITS+1] & bram_raddr[ADDRESS_BITS]};
		datascope1_sel <= {datascope1_sel[0], bram_raddr[ADDRESS_BITS+1] & ~bram_raddr[ADDRESS_BITS]};
		end
		`else
		localparam AXIBRAM_BITS = ADDRESS_BITS; // number of axi address outputs (one more than ADDRESS_BITS when using datascope)
		@@ -433,7 +442,9 @@ sata_phy_rst_out will be released after the sata clock is stable
		.bram_ren (bram_ren[0]), // output
		.bram_regen (bram_ren[1]), // output
		`ifdef USE_DATASCOPE
		.bram_rdata (datascope_sel[1] ? datascope_rdata : bram_rdata_r) // input[31:0]
		.bram_rdata ((datascope_sel[1] \| datascope1_sel[1]) ?
		(datascope1_sel[1]? datascope1_rdata : datascope_rdata) :
		bram_rdata_r) // input[31:0]
		`else
		.bram_rdata (bram_rdata_r) // input[31:0]
		`endif
		@@ -510,6 +521,24 @@ sata_phy_rst_out will be released after the sata clock is stable
		.web (8'hff), // input[7:0]
		.data_in (datascope_di) // input[31:0]
		);

		ram_var_w_var_r #(
		.REGISTERS (0),
		.LOG2WIDTH_WR (5),
		.LOG2WIDTH_RD (5),
		.DUMMY(0)
		) datascope1_mem_i (
		.rclk (aclk), // input
		.raddr (bram_raddr[9:0]), // input[9:0]
		.ren (bram_ren[0]), // input
		.regen (bram_ren[1]), // input
		.data_out (datascope1_rdata), // output[31:0]
		.wclk (datascope1_clk), // input
		.waddr (datascope1_waddr), // input[9:0]
		.we (datascope1_we), // input
		.web (8'hff), // input[7:0]
		.data_in (datascope1_di) // input[31:0]
		);
		`endif

		fifo_cross_clocks #(

ahci/sata_ahci_top.v

+32 −1

Original line number	Diff line number	Diff line
		@@ -40,6 +40,11 @@
		// parameter READ_REG_LATENCY = 2, // 0 if reg_rdata is available with reg_re/reg_addr, 2 with re/regen
		// parameter READ_CT_LATENCY = 1, // 0 if ct_rdata is available with reg_re/reg_addr, 2 with re/regen
		parameter ADDRESS_BITS = 10, // number of memory address bits - now fixed. Low half - RO/RW/RWC,RW1 (2-cycle write), 2-nd just RW (single-cycle)
		`ifdef USE_DATASCOPE
		parameter DATASCOPE_START_BIT = 14, // bit of DRP "other_control" to start recording after 0->1 (needs DRP)
		parameter DATASCOPE_POST_MEAS = 256, // 16, // number of measurements to perform after event
		`endif

		parameter HBA_RESET_BITS = 9, // duration of HBA reset in aclk periods (9: ~10usec)
		parameter RESET_TO_FIRST_ACCESS = 1 // keep port reset until first R/W any register by software
		)(
		@@ -223,6 +228,13 @@

		reg [2:0] nhrst_r;
		wire hrst = !nhrst_r[2];
		`ifdef USE_DATASCOPE
		// Datascope interface (write to memory that can be software-read)
		wire datascope_clk;
		wire [ADDRESS_BITS-1:0] datascope_waddr;
		wire datascope_we;
		wire [31:0] datascope_di;
		`endif

		`ifdef USE_DRP
		wire drp_en;
		@@ -376,6 +388,14 @@
		.sctl_ipm (sctl_ipm), // output[3:0]
		.sctl_spd (sctl_spd), // output[3:0]
		.irq (irq), // output

		`ifdef USE_DATASCOPE
		.datascope1_clk (datascope_clk), // input
		.datascope1_waddr (datascope_waddr), // input[9:0]
		.datascope1_we (datascope_we), // input
		.datascope1_di (datascope_di), // input[31:0]
		`endif

		`ifdef USE_DRP
		.drp_en (drp_en), // output reg
		.drp_we (drp_we), // output reg
		@@ -389,6 +409,11 @@
		);

		ahci_sata_layers #(
		`ifdef USE_DATASCOPE
		.ADDRESS_BITS (ADDRESS_BITS), // for datascope
		.DATASCOPE_START_BIT (DATASCOPE_START_BIT), // bit of DRP "other_control" to start recording after 0->1 (needs DRP)
		.DATASCOPE_POST_MEAS (DATASCOPE_POST_MEAS), // number of measurements to perform after event
		`endif
		.BITS_TO_START_XMIT (6),
		.DATA_BYTE_WIDTH(4)
		) ahci_sata_layers_i (
		@@ -444,6 +469,12 @@
		.txn_out (TXN), // output wire
		.rxp_in (RXP), // input wire
		.rxn_in (RXN), // input wire
		`ifdef USE_DATASCOPE
		.datascope_clk (datascope_clk), // output
		.datascope_waddr (datascope_waddr), // output[9:0]
		.datascope_we (datascope_we), // output
		.datascope_di (datascope_di), // output[31:0]
		`endif
		`ifdef USE_DRP
		.drp_rst (arst), // input
		.drp_clk (ACLK), // input

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