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Commit 5f22131e authored by Andrey Filippov's avatar Andrey Filippov
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updated to x393 project modifications

parent 44c2590f
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x393/simulation_modules/simul_axi_hp_rd.v
View file @ 5f22131e
......@@ -271,38 +271,40 @@ module simul_axi_hp_rd #(
fifo_same_clock_fill #( .DATA_WIDTH(50),.DATA_DEPTH(2)) // read - 4, write - 32?
raddr_i (
.rst (rst),
.clk (aclk),
.sync_rst (1'b0),
.we (arvalid && arready),
.re (start_read_burst_w),
.data_in ({arid[5:0], arburst[1:0], arsize[1:0], arlen[3:0], araddr[31:0], rd_qos_in[3:0]}),
.data_out ({arid_out[5:0], arburst_out[1:0],arsize_out[1:0],arlen_out[3:0],araddr_out[31:0], rd_qos_out[3:0]}),
.nempty (ar_nempty),
.half_full (), //aw_half_full),
.under (), //waddr_under), // output reg
.over (), //waddr_over), // output reg
.wcount (), //waddr_wcount), // output[3:0] reg
.rcount (), //waddr_rcount), // output[3:0] reg
.num_in_fifo(racount) // output[3:0]
.rst (rst),
.clk (aclk),
.sync_rst (1'b0),
.we (arvalid && arready),
.re (start_read_burst_w),
.data_in ({arid[5:0], arburst[1:0], arsize[1:0], arlen[3:0], araddr[31:0], rd_qos_in[3:0]}),
.data_out ({arid_out[5:0], arburst_out[1:0],arsize_out[1:0],arlen_out[3:0],araddr_out[31:0], rd_qos_out[3:0]}),
.nempty (ar_nempty),
.half_full (), //aw_half_full),
.under (), //waddr_under), // output reg
.over (), //waddr_over), // output reg
.wcount (), //waddr_wcount), // output[3:0] reg
.rcount (), //waddr_rcount), // output[3:0] reg
.wnum_in_fifo (racount), // output[3:0]
.rnum_in_fifo () // output[3:0]
);
fifo_same_clock_fill #( .DATA_WIDTH(73),.DATA_DEPTH(7)) // read - 4, write - 32?
rdata_i (
.rst (rst),
.clk (aclk),
.sync_rst (1'b0),
.we (sim_rd_valid && sim_rd_ready),
.re (rvalid && rready),
.data_in ({last_read, arid_out[5:0], sim_rd_resp[1:0], sim_rd_data[63:0]}),
.data_out ({rlast, rid[5:0], rresp[1:0], rdata[63:0]}),
.nempty (r_nempty), //r_nempty),
.half_full (), //aw_half_full),
.under (), //waddr_under),
.over (), //waddr_over),
.wcount (), //waddr_wcount),
.rcount (), //waddr_rcount),
.num_in_fifo(rcount)
.rst (rst),
.clk (aclk),
.sync_rst (1'b0),
.we (sim_rd_valid && sim_rd_ready),
.re (rvalid && rready),
.data_in ({last_read, arid_out[5:0], sim_rd_resp[1:0], sim_rd_data[63:0]}),
.data_out ({rlast, rid[5:0], rresp[1:0], rdata[63:0]}),
.nempty (r_nempty), //r_nempty),
.half_full (), //aw_half_full),
.under (), //waddr_under),
.over (), //waddr_over),
.wcount (), //waddr_wcount),
.rcount (), //waddr_rcount),
.wnum_in_fifo (),
.rnum_in_fifo (rcount)
);
......
x393/simulation_modules/simul_axi_hp_wr.v
View file @ 5f22131e
......@@ -104,6 +104,8 @@ Solved it!
To make it work, I set the (AR/AW)CACHE=0x11 and (AR/AW)PROT=0x00. In the CDMA datasheet, these were the recommended values, which I confirmed with ChipScope, when attached to CDMA's master port.
The default values set by VHLS were 0x00 and 0x10 respectively, which is also the case in the last post.
Alex
UPDATE: Xilinx docs say that (AR/AW)CACHE is ignored
*/
reg [3:0] WrDataThreshold = 'hf;
......@@ -302,37 +304,39 @@ Alex
fifo_same_clock_fill #( .DATA_WIDTH(50),.DATA_DEPTH(5)) // read - 4, write - 32?
waddr_i (
.rst (rst),
.clk (aclk),
.sync_rst (1'b0),
.we (awvalid && awready),
.re (start_write_burst_w),
.data_in ({awid[5:0], awburst[1:0], awsize[1:0], awlen[3:0], awaddr[31:0], wr_qos_in[3:0]}),
.data_out ({awid_out[5:0], awburst_out[1:0],awsize_out[1:0],awlen_out[3:0],awaddr_out[31:0], wr_qos_out[3:0]}),
.nempty (aw_nempty),
.half_full (), //aw_half_full),
.under (), //waddr_under), // output reg
.over (), //waddr_over), // output reg
.wcount (), //waddr_wcount), // output[3:0] reg
.rcount (), //waddr_rcount), // output[3:0] reg
.num_in_fifo(wacount) // output[3:0]
.rst (rst),
.clk (aclk),
.sync_rst (1'b0),
.we (awvalid && awready),
.re (start_write_burst_w),
.data_in ({awid[5:0], awburst[1:0], awsize[1:0], awlen[3:0], awaddr[31:0], wr_qos_in[3:0]}),
.data_out ({awid_out[5:0], awburst_out[1:0],awsize_out[1:0],awlen_out[3:0],awaddr_out[31:0], wr_qos_out[3:0]}),
.nempty (aw_nempty),
.half_full (), //aw_half_full),
.under (), //waddr_under), // output reg
.over (), //waddr_over), // output reg
.wcount (), //waddr_wcount), // output[3:0] reg
.rcount (), //waddr_rcount), // output[3:0] reg
.wnum_in_fifo (wacount), // output[3:0]
.rnum_in_fifo () // output[3:0]
);
fifo_same_clock_fill #( .DATA_WIDTH(79),.DATA_DEPTH(7))
wdata_i (
.rst(rst),
.clk(aclk),
.sync_rst (1'b0),
.we(wvalid && wready),
.re(fifo_wd_rd), //start_write_burst_w), // wrong
.data_in({wlast, wid[5:0], wstrb[7:0], wdata[63:0]}),
.data_out({wlast_out,wid_out[5:0], wstrb_out[7:0], wdata_out[63:0]}),
.nempty(w_nempty),
.half_full(), //w_half_full),
.under (), //wdata_under), // output reg
.over (), //wdata_over), // output reg
.wcount (), //wdata_wcount), // output[3:0] reg
.rcount (), //wdata_rcount), // output[3:0] reg
.num_in_fifo(wcount) // output[3:0]
.rst (rst),
.clk (aclk),
.sync_rst (1'b0),
.we (wvalid && wready),
.re (fifo_wd_rd), //start_write_burst_w), // wrong
.data_in ({wlast, wid[5:0], wstrb[7:0], wdata[63:0]}),
.data_out ({wlast_out,wid_out[5:0], wstrb_out[7:0], wdata_out[63:0]}),
.nempty (w_nempty),
.half_full (), //w_half_full),
.under (), //wdata_under), // output reg
.over (), //wdata_over), // output reg
.wcount (), //wdata_wcount), // output[3:0] reg
.rcount (), //wdata_rcount), // output[3:0] reg
.wnum_in_fifo (wcount), // output[3:0]
.rnum_in_fifo () // output[3:0]
);
// **** Write response channel ****
wire [ 1:0] bresp_value=2'b0;
......@@ -346,31 +350,32 @@ fifo_same_clock_fill #( .DATA_WIDTH(79),.DATA_DEPTH(7))
dly_16 #(
.WIDTH(1)
) bresp_dly_16_i (
.clk(aclk), // input
.rst(rst), // input
.dly(sim_bresp_latency[3:0]), // input[3:0]
.din(last_confirmed_write), //fifo_wd_rd), // input[0:0]
.dout(fifo_wd_rd_dly) // output[0:0]
.clk (aclk), // input
.rst (rst), // input
.dly (sim_bresp_latency[3:0]), // input[3:0]
.din (last_confirmed_write), //fifo_wd_rd), // input[0:0]
.dout (fifo_wd_rd_dly) // output[0:0]
);
// first FIFO for bresp - latency outside of the module
// wresp per burst, not per item !
fifo_same_clock_fill #( .DATA_WIDTH(8),.DATA_DEPTH(5))
wresp_ext_i (
.rst(rst),
.clk(aclk),
.sync_rst (1'b0),
.we(last_confirmed_write), // fifo_wd_rd),
.re(fifo_wd_rd_dly), // not allowing RE next cycle after bvalid
.data_in({wid_out[5:0],bresp_value[1:0]}),
.data_out({bid_in[5:0],bresp_in[1:0]}),
.nempty(),
.half_full(), //),
.under (), //wresp_under), // output reg
.over (), //wresp_over), // output reg
.wcount (), //wresp_wcount), // output[3:0] reg
.rcount (), //wresp_rcount), // output[3:0] reg
.num_in_fifo() // wresp_num_in_fifo) // output[3:0]
.rst (rst),
.clk (aclk),
.sync_rst (1'b0),
.we (last_confirmed_write), // fifo_wd_rd),
.re (fifo_wd_rd_dly), // not allowing RE next cycle after bvalid
.data_in ({wid_out[5:0],bresp_value[1:0]}),
.data_out ({bid_in[5:0],bresp_in[1:0]}),
.nempty (),
.half_full (), //),
.under (), //wresp_under), // output reg
.over (), //wresp_over), // output reg
.wcount (), //wresp_wcount), // output[3:0] reg
.rcount (), //wresp_rcount), // output[3:0] reg
.wnum_in_fifo (), // wresp_num_in_fifo) // output[3:0]
.rnum_in_fifo () // wresp_num_in_fifo) // output[3:0]
);
assign wresp_re=bready && bvalid; // && !was_wresp_re;
......@@ -382,20 +387,21 @@ fifo_same_clock_fill #( .DATA_WIDTH(8),.DATA_DEPTH(5))
// second wresp FIFO (does it exist in the actual module)?
fifo_same_clock_fill #( .DATA_WIDTH(8),.DATA_DEPTH(5))
wresp_i (
.rst(rst),
.clk(aclk),
.sync_rst (1'b0),
.we(fifo_wd_rd_dly),
.re(wresp_re), // not allowing RE next cycle after bvalid
.data_in({bid_in[5:0],bresp_in[1:0]}),
.data_out({bid[5:0],bresp[1:0]}),
.nempty(), //bvalid),
.half_full(), //),
.under (), //wresp_under), // output reg
.over (), //wresp_over), // output reg
.wcount (), //wresp_wcount), // output[3:0] reg
.rcount (), //wresp_rcount), // output[3:0] reg
.num_in_fifo(wresp_num_in_fifo) // wresp_num_in_fifo) // output[3:0]
.rst (rst),
.clk (aclk),
.sync_rst (1'b0),
.we (fifo_wd_rd_dly),
.re (wresp_re), // not allowing RE next cycle after bvalid
.data_in ({bid_in[5:0],bresp_in[1:0]}),
.data_out ({bid[5:0],bresp[1:0]}),
.nempty (), //bvalid),
.half_full (), //),
.under (), //wresp_under), // output reg
.over (), //wresp_over), // output reg
.wcount (), //wresp_wcount), // output[3:0] reg
.rcount (), //wresp_rcount), // output[3:0] reg
.wnum_in_fifo (), // wresp_num_in_fifo) // output[3:0]
.rnum_in_fifo (wresp_num_in_fifo) // wresp_num_in_fifo) // output[3:0]
);
endmodule
......
x393/util_modules/fifo_same_clock_fill.v
View file @ 5f22131e
......@@ -53,7 +53,8 @@ module fifo_same_clock_fill
output reg over, // overwritten
output reg [DATA_DEPTH-1:0] wcount,
output reg [DATA_DEPTH-1:0] rcount,
output [DATA_DEPTH: 0] num_in_fifo
output [DATA_DEPTH: 0] wnum_in_fifo, // number of items in FIFO on write side
output [DATA_DEPTH: 0] rnum_in_fifo // number of items in FIFO on read side
);
localparam integer DATA_2DEPTH=(1<<DATA_DEPTH)-1;
//ISExst: FF/Latch ddrc_test01.axibram_write_i.waddr_i.fill[4] has a constant value of 0 in block <ddrc_test01>. This FF/Latch will be trimmed during the optimization process.
......@@ -61,38 +62,45 @@ module fifo_same_clock_fill
//ISExst: FF/Latch ddrc_test01.axibram_write_i.wdata_i.fill[4] has a constant value of 0 in block <ddrc_test01>. This FF/Latch will be trimmed during the optimization process.
// Do not understand - why?
reg [DATA_DEPTH: 0] fill=0; // RAM fill
reg [DATA_DEPTH: 0] fifo_fill=0; // FIFO (RAM+reg) fill
reg [DATA_DEPTH: 0] wfifo_fill=0; // FIFO (RAM+reg) fill - total number in FIFO
reg [DATA_DEPTH: 0] rfifo_fill=0; // number in FIFO, ready to be read out
reg [DATA_WIDTH-1:0] inreg;
reg [DATA_WIDTH-1:0] outreg;
reg [DATA_DEPTH-1:0] ra;
reg [DATA_DEPTH-1:0] wa;
wire [DATA_DEPTH:0] next_fill;
reg wem;
wire [DATA_DEPTH:0] next_fill;
reg [1:0] wem;
wire rem;
reg out_full=0; //output register full
reg [DATA_WIDTH-1:0] ram [0:DATA_2DEPTH];
reg ram_nempty;
assign next_fill = fill[DATA_DEPTH:0]+((wem && ~rem)?1:((~wem && rem && ram_nempty)?-1:0));
assign next_fill = fill[DATA_DEPTH:0]+((wem[0] && ~rem)?1:((~wem[0] && rem && ram_nempty)?-1:0));
assign rem= ram_nempty && (re || !out_full);
assign data_out=outreg;
assign nempty=out_full;
// assign num_in_fifo=fill[DATA_DEPTH:0];
assign num_in_fifo=fifo_fill[DATA_DEPTH:0];
assign wnum_in_fifo=wfifo_fill[DATA_DEPTH:0];
assign rnum_in_fifo=rfifo_fill[DATA_DEPTH:0];
always @ (posedge clk or posedge rst) begin
if (rst) fill <= 0;
else if (sync_rst) fill <= 0;
else fill <= next_fill;
if (rst) fill <= 0;
else if (sync_rst) fill <= 0;
else fill <= next_fill;
if (rst) fifo_fill <= 0;
else if (sync_rst) fifo_fill <= 0;
else if ( we && !re) fifo_fill <= fifo_fill+1;
else if (!we && re) fifo_fill <= fifo_fill-1;
if (rst) wfifo_fill <= 0;
else if (sync_rst) wfifo_fill <= 0;
else if ( we && !re) wfifo_fill <= wfifo_fill+1;
else if (!we && re) wfifo_fill <= wfifo_fill-1;
if (rst) rfifo_fill <= 0; // pessimistic, all writes are delayed by 2
else if (sync_rst) rfifo_fill <= 0;
else if ( wem[1] && !re) rfifo_fill <= rfifo_fill+1;
else if (!wem[1] && re) rfifo_fill <= rfifo_fill-1;
if (rst) wem <= 0;
else if (sync_rst) wem <= 0;
else wem <= we;
else wem <= {wem[0], we};
if (rst) ram_nempty <= 0;
else if (sync_rst) ram_nempty <= 0;
......@@ -100,7 +108,7 @@ module fifo_same_clock_fill
if (rst) wa <= 0;
else if (sync_rst) wa <= 0;
else if (wem) wa <= wa+1;
else if (wem[0]) wa <= wa+1;
if (rst) ra <= 0;
else if (sync_rst) ra <= 0;
......@@ -123,12 +131,13 @@ module fifo_same_clock_fill
// no reset elements
always @ (posedge clk) begin
half_full <=(fill & (1<<(DATA_DEPTH-1)))!=0;
if (wem) ram[wa] <= inreg;
if (we) inreg <= data_in;
if (rem) outreg <= ram[ra];
// under <= ~we & re & ~nempty; // underrun error
// over <= we & ~re & (fill == (1<< (DATA_DEPTH-1))); // overrun error
if (wem[0]) ram[wa] <= inreg;
if (we) inreg <= data_in;
if (rem) outreg <= ram[ra];
under <= re & ~nempty; // underrun error
over <= wem & ~rem & fill[DATA_DEPTH] & ~fill[DATA_DEPTH-1]; // overrun error
over <= wem[0] & ~rem & fill[DATA_DEPTH] & ~fill[DATA_DEPTH-1]; // overrun error
end
endmodule
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