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Commit 4f36a863 authored by Andrey Filippov's avatar Andrey Filippov
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debugging h2d dma

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.project
View file @ 4f36a863
......@@ -52,87 +52,87 @@
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ahci/ahci_dma.v
View file @ 4f36a863
......@@ -146,6 +146,8 @@ module ahci_dma (
output [31:0] debug_out,
output [31:0] debug_out1
,output [31:0] debug_dma_h2d
);
......@@ -591,6 +593,8 @@ module ahci_dma (
.dout_vld (sys_dav), // output
.dout_re (sys_re), // input
.last_DW (last_h2d_data) // output
,.debug_dma_h2d(debug_dma_h2d) // output[31:0]
);
ahci_dma_wr_fifo #( // device to memory
......
ahci/ahci_dma_rd_fifo.v
View file @ 4f36a863
......@@ -61,53 +61,42 @@ module ahci_dma_rd_fifo#(
output dout_vld,
input dout_re,
output last_DW // dout contains last DW
,output [31:0] debug_dma_h2d
);
localparam ADDRESS_NUM = (1<<ADDRESS_BITS); // 8 for ADDRESS_BITS==3
reg [ADDRESS_BITS : 0] waddr; // 1 extra bit
reg [ADDRESS_BITS+1:0] raddr; // 1 extra bit
reg [63:16] din_prev; // only 48 bits are needed
reg [WCNT_BITS-3:0] qwcntr;
// reg some_offs;
/// reg extra_in;
reg busy;
// reg din_last_w = din_re && (qwcntr==0);
wire [2:0] end_offs = wcnt[1:0] + woffs;
reg [63:0] fifo_ram [0: ADDRESS_NUM - 1];
reg [3:0] vld_ram [0: ADDRESS_NUM - 1];
// reg [1:0] flush_ram [0: ADDRESS_NUM - 1];
reg [(1<<ADDRESS_BITS)-1:0] fifo_full; // set in write clock domain
reg [(1<<ADDRESS_BITS)-1:0] fifo_nempty;// set in read clock domain
wire fifo_wr;
wire fifo_rd;
reg [1:0] fifo_rd_r;
// reg hrst_mclk;
reg mrst_hclk;
/// wire [(1<<ADDRESS_BITS)-1:0] fifo_full2 = {fifo_full[0],fifo_full[ADDRESS_NUM-1:1]};
wire [(1<<ADDRESS_BITS)-1:0] fifo_full2 = {~fifo_full[0],fifo_full[ADDRESS_NUM-1:1]};
// wire [(1<<ADDRESS_BITS)-1:0] fifo_nempty_half = {fifo_nempty[(ADDRESS_NUM>>1)-1:0],fifo_full[ADDRESS_NUM-1: ADDRESS_NUM>>1]};
reg fifo_dav; // @mclk
wire fifo_dav2_w;
reg fifo_dav2; // @mclk
// wire fifo_dav_w;
reg fifo_half_hclk; // Half Fifo is empty, OK to write
reg [1:0] woffs_r;
wire [63:0] fifo_di= woffs_r[1]?(woffs_r[0] ? {din[47:0],din_prev[63:48]} : {din[31:0],din_prev[63:32]}):
(woffs_r[0] ? {din[15:0],din_prev[63:16]} : din[63:0]);
/// (woffs_r[0] ? {din[15:0],din_prev[63:16]} : din_prev[63:0]);
wire [3:0] fifo_di_vld;
// wire [1:0] fifo_di_flush; // Assign
wire [63:0] fifo_do = fifo_ram [raddr[ADDRESS_BITS:1]];
// wire [3:0] fifo_do_vld = fifo_dav_w? vld_ram [raddr[ADDRESS_BITS:1]] : 4'b0;
wire [3:0] fifo_do_vld = vld_ram [raddr[ADDRESS_BITS:1]];
// wire [1:0] fifo_do_flush = fifo_dav_w? flush_ram[raddr[ADDRESS_BITS:1]] : 2'b0;
reg din_av_safe_r;
reg en_fifo_wr;
reg [3:0] last_mask;
// reg flush_r;
wire done_flush_mclk;
reg flushing_hclk; // flushing data, ends when confirmed from mclk domain
reg flushing_mclk; // just registered flushing_hclk @mclk
......@@ -116,15 +105,8 @@ module ahci_dma_rd_fifo#(
assign din_re = busy && fifo_half_hclk && din_av_safe_r;
assign fifo_wr = en_fifo_wr && fifo_half_hclk && (din_av_safe_r || !busy);
/// assign fifo_di_vld = (busy && (!extra_in || (qwcntr != 0)))? 4'hf : last_mask ;
/// assign fifo_di_flush = ((busy && (!extra_in || (qwcntr != 0))) || !flush_r)? 2'h0 : {|last_mask[3:2], ~(|last_mask[3:2])} ;
/// assign fifo_di_vld = (busy && (qwcntr != 0))? 4'hf : last_mask ;
assign fifo_di_vld = last_fifo_wr? last_mask : 4'hf;
// assign fifo_di_flush = ((busy && (qwcntr != 0)) || !flush_r)? 2'h0 : {|last_mask[3:2], ~(|last_mask[3:2])} ;
// assign fifo_dav_w = fifo_dav && (fifo_dav2 || !(|fifo_rd_r));
wire [2:0] debug_waddr = waddr[2:0];
wire [2:0] debug_raddr = raddr[3:1];
......@@ -145,21 +127,15 @@ module ahci_dma_rd_fifo#(
if (mrst_hclk) en_fifo_wr <= 0;
else if (start) en_fifo_wr <= (woffs == 0);
/// else if (din_re || fifo_wr) en_fifo_wr <= busy && ((qwcntr != 0) || ((woffs != 0) && last_prd));
else if (din_re || fifo_wr) en_fifo_wr <= busy && ((qwcntr != 0) || ((woffs != 0) && !end_offs[2]));
//last_fifo_wr
/// if (start) qwcntr <= wcnt[WCNT_BITS-1:2];
if (start) qwcntr <= wcnt[WCNT_BITS-1:2] + end_offs[2];
else if (din_re) qwcntr <= qwcntr - 1;
/// if (start) extra_in <= end_offs[2];
if (start) woffs_r <= woffs;
if (mrst_hclk) fifo_full <= 0;
/// else if (fifo_wr) fifo_full <= {fifo_full[ADDRESS_NUM-2:0], waddr[ADDRESS_BITS]};
else if (fifo_wr) fifo_full <= {fifo_full[ADDRESS_NUM-2:0],~waddr[ADDRESS_BITS]};
if (mrst_hclk) waddr <= 0;
......@@ -178,27 +154,17 @@ module ahci_dma_rd_fifo#(
if (start) last_mask <= {&wcnt, wcnt[1], |wcnt, 1'b1};
// if (start) flush_r <= last_prd;
if (mrst_hclk || done_flush) flushing_hclk <= 0;
// else if (busy && din_re && (qwcntr == 0) && last_prd) flushing_hclk <= 1;
else if (fifo_wr && last_prd && (((qwcntr == 0) && ((woffs == 0) || !last_prd)) || !busy)) flushing_hclk <= 1;
// else if (din_re || fifo_wr) en_fifo_wr <= busy && ((qwcntr != 0) || (woffs != 0));
end
always @ (posedge mclk) begin
fifo_rd_r <= {fifo_rd_r[0],fifo_rd};
/// hrst_mclk <= hrst;
/// if (hrst_mclk) raddr <= 0;
if (mrst) raddr <= 0;
else if (fifo_rd) raddr <= raddr + 1;
/// if (hrst_mclk) fifo_nempty <= {{(ADDRESS_NUM>>1){1'b0}},{(ADDRESS_NUM>>1){1'b1}}};// 8'b00001111
if (mrst) fifo_nempty <= {{(ADDRESS_NUM>>1){1'b0}},{(ADDRESS_NUM>>1){1'b1}}};// 8'b00001111
/// else if (fifo_rd && raddr[0]) fifo_nempty <= {fifo_nempty[ADDRESS_NUM-2:0],raddr[ADDRESS_BITS+1] ^ raddr[ADDRESS_BITS]};
else if (fifo_rd && raddr[0]) fifo_nempty <= {fifo_nempty[ADDRESS_NUM-2:0], ~raddr[ADDRESS_BITS+1] ^ raddr[ADDRESS_BITS]};
fifo_dav <= fifo_full [raddr[ADDRESS_BITS:1]] ^ raddr[ADDRESS_BITS+1];
......@@ -214,7 +180,6 @@ module ahci_dma_rd_fifo#(
.din_av (fifo_dav), // input
.din_avm_w(fifo_dav2_w), // input
.din_avm (fifo_dav2), // input
// .flush (raddr[0]?fifo_do_flush[1]:fifo_do_flush[0]), // input
.flushing (flushing_mclk), // input
.din (raddr[0]?fifo_do[63:32]: fifo_do[31:0]), // input[31:0]
.dm (raddr[0]?fifo_do_vld[3:2]:fifo_do_vld[1:0]), // input[1:0]
......@@ -222,8 +187,8 @@ module ahci_dma_rd_fifo#(
.flushed (done_flush_mclk), // output reg: flush (end of last PRD is finished - data left module)
.dout (dout), // output[31:0] reg
.dout_vld (dout_vld), // output
.dout_re (dout_re), // input
.last_DW (last_DW)
.dout_re (dout_re), // input
.last_DW (last_DW) // output
);
pulse_cross_clock #(
......@@ -232,21 +197,25 @@ module ahci_dma_rd_fifo#(
.rst (mrst), // input
.src_clk (mclk), // input
.dst_clk (hclk), // input
// .in_pulse (flush_r && din_re && (qwcntr == 0)), // input
.in_pulse (done_flush_mclk), // input
.out_pulse (done_flush), // output
.busy() // output
);
/*
pulse_cross_clock #(
.EXTRA_DLY(0)
) last_data_i (
.rst (mrst_hclk), // input
.src_clk (hclk), // input
.dst_clk (mclk), // input
.in_pulse (busy && din_re && (qwcntr == 0) && last_prd),// input
.out_pulse (last_data), // output
.busy() // output
);
*/
assign debug_dma_h2d = {
14'b0,
fifo_rd,
raddr[4:0],
fifo_do_vld[3:0],
fifo_dav,
fifo_dav2_w,
fifo_dav2,
flushing_mclk,
done_flush_mclk,
dout_vld,
dout_re,
last_DW
};
endmodule
ahci/ahci_top.v
View file @ 4f36a863
......@@ -476,6 +476,7 @@ module ahci_top#(
wire [9:0] last_jump_addr;
wire [31:0] debug_dma;
wire [31:0] debug_dma1;
wire [31:0] debug_dma_h2d;
// Async FF
always @ (posedge mrst or posedge mclk) begin
if (mrst) en_port <= 0;
......@@ -941,6 +942,7 @@ wire[1:0] debug_get_fis_busy_r; // output[1:0]
.afi_rdissuecap1en (afi_rdissuecap1en), // output
.debug_out (debug_dma), // output[31:0]
.debug_out1 (debug_dma1) // output[31:0]
,.debug_dma_h2d (debug_dma_h2d)
);
ahci_fis_receive #(
......@@ -1085,8 +1087,66 @@ wire [9:0] xmit_dbg_01;
);
// Datascope code
`ifdef USE_DATASCOPE
`define DATASCOPE_V2
// Datascope interface (write to memory that can be software-read)
`ifdef USE_DATASCOPE
`ifdef DATASCOPE_V2
reg [ADDRESS_BITS-1:0] datascope_waddr_r;
reg [1:0] datascope_run;
// reg [1:0] datascope_run;
assign datascope_we = datascope_run[1];
assign datascope_clk = mclk;
assign datascope_waddr = datascope_waddr_r;
assign datascope_di = {
debug_dma_h2d[3], // done_flush_mclk,
debug_dma_h2d[2], // dout_vld,
debug_dma_h2d[1], // dout_re,
debug_dma_h2d[0], // last_DW,
dma_dout[27:16],
debug_dma_h2d[19:4]
};
// dma_dout[
always @ (posedge mclk) begin
if (mrst) datascope_run[0] <= 0;
else if (dma_cmd_start) datascope_run[0] <= 1;
else if (dma_cmd_done) datascope_run[0] <= 0;
if (mrst || !datascope_run[0]) datascope_run[1] <= 0;
else if (dma_dav) datascope_run[1] <= 1;
if (fsnd_cfis_xmit) datascope_waddr_r <= 0;
else if (datascope_we) datascope_waddr_r <= datascope_waddr_r + 1;
end
/*debug_dma_h2d
assign debug_dma_h2d = {
14'b0,
17 fifo_rd,
16:12 raddr[4:0],
11: 8 fifo_do_vld[3:0],
7 fifo_dav,
6 fifo_dav2_w,
5 fifo_dav2,
4 flushing_mclk,
3 done_flush_mclk,
2 dout_vld,
1 dout_re,
0 last_DW
};
*/
`endif // DATASCOPE_V2
`ifdef DATASCOPE_V1
localparam DATASCOPE_CFIS_START=0;
localparam DATASCOPE_INCOMING_POST=32;
......@@ -1270,9 +1330,10 @@ assign debug_out[7: 5] = {
.ct_re (dma_ct_re), // output[1:0]
.ct_data (dma_ct_data), // input[31:0]
*/
*/
`endif // DATASCOPE_V1
`endif
`endif // USE_DATASCOPE
......
device/sata_device.v
View file @ 4f36a863
......@@ -840,7 +840,8 @@ task send_identify_data; // @SuppressThisWarning VEditor - Used in testbench
reg [15:0] identify_data[0:255]; // SuppressThisWarning VEditor : assigned in $readmem() system task
integer i;
begin
$readmemh("input_data/identify.dat",identify_data);
// $readmemh("input_data/identify.dat",identify_data);
$readmemh("input_data/test512.dat",identify_data);
transmit_data[0] = FIS_DATA;
for (i=0;i<128;i=i+1) begin
transmit_data[i+1] = {identify_data[2 * i+1], identify_data[2 * i]};
......
py393sata/x393sata.py
View file @ 4f36a863
......@@ -1067,6 +1067,17 @@ for block in range (1,1024):
sata.reg_status(),sata.reset_ie(),sata.err_count()
#############
for i in range(128):
mem.write_mem(x393sata.DATAOUT_ADDRESS + 4*i,2*i + ((254-2*i)<<8) + ((2*i+1)<<16) + ((255-2*i) << 24))
_=mem.mem_dump(x393sata.DATAOUT_ADDRESS,128,4)
_=mem.mem_dump(x393sata.DATAOUT_ADDRESS,256,2)
sata.dd_write_dma(9,1)
_=mem.mem_dump (0x80000ff0, 4,4)
_=mem.mem_dump (0x80001000, 0x200,4)
......@@ -1427,6 +1438,17 @@ _=mem.mem_dump (0x80001000, 0x20,4)
mem.write_mem(0x80000118,0x10)
for i in range(128):
mem.write_mem(x393sata.DATAOUT_ADDRESS + 4*i,2*i + ((2*i+1)<<16))
mem.mem_dump(x393sata.DATAOUT_ADDRESS,128,4)
for i in range(128):
mem.write_mem(x393sata.DATAOUT_ADDRESS + 4*i,2*i + ((254-2*i)<<8) + ((2*i+1)<<16) + ((255-2*i) << 24))
sata.dd_write_dma(9,1)
idfy:
Command table data:
......
tb_ahci_01.sav
View file @ 4f36a863
[*]
[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
[*] Wed Feb 17 00:41:51 2016
[*] Wed Feb 17 17:02:15 2016
[*]
[dumpfile] "/home/andrey/git/x393_sata/simulation/tb_ahci-20160216095816459.fst"
[dumpfile_mtime] "Tue Feb 16 16:59:52 2016"
[dumpfile_size] 10761673
[dumpfile] "/home/andrey/git/x393_sata/simulation/tb_ahci-20160217091938387.fst"
[dumpfile_mtime] "Wed Feb 17 16:21:21 2016"
[dumpfile_size] 10752181
[savefile] "/home/andrey/git/x393_sata/tb_ahci_01.sav"
[timestart] 33334000
[timestart] 55279500
[size] 1823 1180
[pos] 2026 0
*-17.446142 33882754 29549854 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
*-15.446142 55307278 29549854 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] tb_ahci.
[treeopen] tb_ahci.axi_read_addr.
[treeopen] tb_ahci.dev.linkMonitorFIS.
......@@ -1969,7 +1969,7 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.fis_dcount[3:0]
-group_end
@1401200
-ahci_fis_receive
@c00200
@800200
-ahci_fis_transmit
@28
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.xmit_ok
......@@ -2129,7 +2129,7 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.prd_rd
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.data_addr[31:1]
@1001200
-group_end
@1401200
@1000200
-ahci_fis_transmit
@c00200
-ahci_sata_layers
......@@ -2327,7 +2327,7 @@ tb_ahci.simul_axi_hp_wr_i.wdata_i.fill[7:0]
-fifo_wdata
@1401200
-simul_axi_hp_wr
@c00200
@800200
-ahci_dma
@28
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.addr_data_rq_w
......@@ -2648,10 +2648,55 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_rd_fifo_i.waddr[3:0]
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_rd_fifo_i.din_prev[63:16]
@28
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_rd_fifo_i.mrst_hclk
@29
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_rd_fifo_i.fifo_rd
@800200
-debug
@28
tb_ahci.dut.sata_top.ahci_top_i.datascope_run[1:0]
@22
tb_ahci.dut.sata_top.ahci_top_i.datascope_waddr[9:0]
@c00022
tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
@28
(0)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(1)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(2)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(3)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(4)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(5)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(6)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(7)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(8)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(9)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(10)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(11)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(12)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(13)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(14)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(15)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(16)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(17)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(18)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(19)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(20)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(21)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(22)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(23)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(24)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(25)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(26)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(27)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(28)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(29)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(30)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(31)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
@1401200
-group_end
@28
tb_ahci.dut.sata_top.ahci_top_i.dma_cmd_start
tb_ahci.dut.sata_top.ahci_top_i.dma_cmd_done
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_rd_fifo_i.last_DW
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_rd_fifo_i.fifo_half_hclk
@22
[color] 1
......@@ -3431,19 +3476,12 @@ tb_ahci.simul_axi_hp_rd_i.rdata_i.out_full
-top
@200
-
@1401200
@1000200
-ahci_dma
@c00200
-datascope0
@22
tb_ahci.dut.sata_top.ahci_top_i.datascope_id[3:0]
tb_ahci.dut.sata_top.ahci_top_i.datascope_incoming_cntr[7:0]
@800028
tb_ahci.dut.sata_top.ahci_top_i.datascope_incoming_run[2:0]
@28
(0)tb_ahci.dut.sata_top.ahci_top_i.datascope_incoming_run[2:0]
(1)tb_ahci.dut.sata_top.ahci_top_i.datascope_incoming_run[2:0]
(2)tb_ahci.dut.sata_top.ahci_top_i.datascope_incoming_run[2:0]
@800200
-tb_ahci.dut.sata_top.ahci_top_i.datascope_incoming_run
@c00022
tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
@28
......@@ -3499,9 +3537,7 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.link.data_out_rr[31:0]
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.inc_is_data
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.set_rcvr_eof
@29
tb_ahci.dut.sata_top.ahci_sata_layers_i.ll_d2h_valid
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.fis_over_r
tb_ahci.dut.sata_top.ahci_sata_layers_i.d2h_fifo_wr
tb_ahci.dut.sata_top.ahci_sata_layers_i.d2h_type_in[1:0]
......
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