simple tests for a new testbench (4b361952) · Commits · Elphel / x393_sata

axi_regs.v

+8 −5

Original line number	Original line	Diff line number	Diff line
	@@ -126,13 +126,16 @@ endgenerate

	// read from memory. Interface's protocol assumes returning data to delay		// read from memory. Interface's protocol assumes returning data to delay
	reg [3:0] bram_raddr_r;		reg [3:0] bram_raddr_r;
	always @ (posedge ACLK)		reg [31:0] bram_rdata_r;
	bram_raddr_r <= bram_regen ? bram_raddr[3:0] : bram_raddr_r;		always @ (posedge ACLK) begin
	assign bram_rdata = mem[32*bram_raddr_r + 31-:32];		bram_raddr_r <= bram_ren ? bram_raddr[3:0] : bram_raddr_r;
			bram_rdata_r <= bram_regen ? mem[32*bram_raddr_r + 31-:32] : bram_rdata_r;
			end
			assign bram_rdata = bram_rdata_r;

	// Interface's instantiation		// Interface's instantiation
	axibram_write #(		axibram_write #(
	.ADDRESS_BITS(32)		.ADDRESS_BITS(16)
	)		)
	axibram_write(		axibram_write(
	.aclk (ACLK),		.aclk (ACLK),
	@@ -164,7 +167,7 @@ axibram_write(
	.bram_wdata (bram_wdata)		.bram_wdata (bram_wdata)
	);		);
	axibram_read #(		axibram_read #(
	.ADDRESS_BITS(32)		.ADDRESS_BITS(16)
	)		)
	axibram_read(		axibram_read(
	.aclk (ACLK),		.aclk (ACLK),

tb/tb_top.v

+30 −30

Original line number	Original line	Diff line number	Diff line
	@@ -163,28 +163,28 @@ always #(CLKIN_PERIOD/2) CLK = ~CLK;
	assign dut.ps7_i.FCLKCLK= {4{CLK}};		assign dut.ps7_i.FCLKCLK= {4{CLK}};
	assign dut.ps7_i.FCLKRESETN= {RST,~RST,RST,~RST};		assign dut.ps7_i.FCLKRESETN= {RST,~RST,RST,~RST};
	// Read address		// Read address
	assign dut.ps7_i.MAXIGP0ARADDR= araddr;		assign dut.ps7_i.MAXIGP1ARADDR= araddr;
	assign dut.ps7_i.MAXIGP0ARVALID= arvalid;		assign dut.ps7_i.MAXIGP1ARVALID= arvalid;
	assign arready= dut.ps7_i.MAXIGP0ARREADY;		assign arready= dut.ps7_i.MAXIGP1ARREADY;
	assign dut.ps7_i.MAXIGP0ARID= arid;		assign dut.ps7_i.MAXIGP1ARID= arid;
	assign dut.ps7_i.MAXIGP0ARLEN= arlen;		assign dut.ps7_i.MAXIGP1ARLEN= arlen;
	assign dut.ps7_i.MAXIGP0ARSIZE= arsize[1:0]; // arsize[2] is not used		assign dut.ps7_i.MAXIGP1ARSIZE= arsize[1:0]; // arsize[2] is not used
	assign dut.ps7_i.MAXIGP0ARBURST= arburst;		assign dut.ps7_i.MAXIGP1ARBURST= arburst;
	// Read data		// Read data
	assign rdata= dut.ps7_i.MAXIGP0RDATA;		assign rdata= dut.ps7_i.MAXIGP1RDATA;
	assign rvalid= dut.ps7_i.MAXIGP0RVALID;		assign rvalid= dut.ps7_i.MAXIGP1RVALID;
	assign dut.ps7_i.MAXIGP0RREADY= rready;		assign dut.ps7_i.MAXIGP1RREADY= rready;
	assign rid= dut.ps7_i.MAXIGP0RID;		assign rid= dut.ps7_i.MAXIGP1RID;
	assign rlast= dut.ps7_i.MAXIGP0RLAST;		assign rlast= dut.ps7_i.MAXIGP1RLAST;
	assign rresp= dut.ps7_i.MAXIGP0RRESP;		assign rresp= dut.ps7_i.MAXIGP1RRESP;
	// Write address		// Write address
	assign dut.ps7_i.MAXIGP0AWADDR= awaddr;		assign dut.ps7_i.MAXIGP1AWADDR= awaddr;
	assign dut.ps7_i.MAXIGP0AWVALID= awvalid;		assign dut.ps7_i.MAXIGP1AWVALID= awvalid;

	assign awready= dut.ps7_i.MAXIGP0AWREADY;		assign awready= dut.ps7_i.MAXIGP1AWREADY;

	//assign awready= AWREADY_AAAA;		//assign awready= AWREADY_AAAA;
	assign dut.ps7_i.MAXIGP0AWID=awid;		assign dut.ps7_i.MAXIGP1AWID=awid;

	// SuppressWarnings VEditor all		// SuppressWarnings VEditor all
	// wire [ 1:0] AWLOCK;		// wire [ 1:0] AWLOCK;
	@@ -192,23 +192,23 @@ assign dut.ps7_i.MAXIGP0AWID=awid;
	// wire [ 3:0] AWCACHE;		// wire [ 3:0] AWCACHE;
	// SuppressWarnings VEditor all		// SuppressWarnings VEditor all
	// wire [ 2:0] AWPROT;		// wire [ 2:0] AWPROT;
	assign dut.ps7_i.MAXIGP0AWLEN= awlen;		assign dut.ps7_i.MAXIGP1AWLEN= awlen;
	assign dut.ps7_i.MAXIGP0AWSIZE= awsize[1:0]; // awsize[2] is not used		assign dut.ps7_i.MAXIGP1AWSIZE= awsize[1:0]; // awsize[2] is not used
	assign dut.ps7_i.MAXIGP0AWBURST= awburst;		assign dut.ps7_i.MAXIGP1AWBURST= awburst;
	// SuppressWarnings VEditor all		// SuppressWarnings VEditor all
	// wire [ 3:0] AWQOS;		// wire [ 3:0] AWQOS;
	// Write data		// Write data
	assign dut.ps7_i.MAXIGP0WDATA= wdata;		assign dut.ps7_i.MAXIGP1WDATA= wdata;
	assign dut.ps7_i.MAXIGP0WVALID= wvalid;		assign dut.ps7_i.MAXIGP1WVALID= wvalid;
	assign wready= dut.ps7_i.MAXIGP0WREADY;		assign wready= dut.ps7_i.MAXIGP1WREADY;
	assign dut.ps7_i.MAXIGP0WID= wid;		assign dut.ps7_i.MAXIGP1WID= wid;
	assign dut.ps7_i.MAXIGP0WLAST= wlast;		assign dut.ps7_i.MAXIGP1WLAST= wlast;
	assign dut.ps7_i.MAXIGP0WSTRB= wstrb;		assign dut.ps7_i.MAXIGP1WSTRB= wstrb;
	// Write response		// Write response
	assign bvalid= dut.ps7_i.MAXIGP0BVALID;		assign bvalid= dut.ps7_i.MAXIGP1BVALID;
	assign dut.ps7_i.MAXIGP0BREADY= bready;		assign dut.ps7_i.MAXIGP1BREADY= bready;
	assign bid= dut.ps7_i.MAXIGP0BID;		assign bid= dut.ps7_i.MAXIGP1BID;
	assign bresp= dut.ps7_i.MAXIGP0BRESP;		assign bresp= dut.ps7_i.MAXIGP1BRESP;


	// Simulation modules		// Simulation modules

tb/test_top.v

+12 −1

Original line number	Original line	Diff line number	Diff line
	@@ -35,9 +35,20 @@ begin
	RST = 1'b1;		RST = 1'b1;
	NUM_WORDS_EXPECTED =0;		NUM_WORDS_EXPECTED =0;
	// #99000; // same as glbl		// #99000; // same as glbl
	#9000; // same as glbl		#900; // same as glbl
	repeat (20) @(posedge CLK) ;		repeat (20) @(posedge CLK) ;
	RST =1'b0;		RST =1'b0;

			repeat (20)
			@ (posedge CLK);
			axi_set_rd_lag(0);

			axi_write_single(32'h4, 32'hdeadbeef);
			axi_read_addr(12'h777, 32'h4, 4'h3, 2'b01);
			repeat (7)
			@ (posedge CLK);
			axi_write_single(32'h8, 32'hd34db33f);
			axi_read_addr(12'h555, 32'h0, 4'h3, 2'b01);
	end		end

	initial		initial

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