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Commit 4626e2cd authored by Andrey Filippov's avatar Andrey Filippov
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hardware debugging

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.project
View file @ 4626e2cd
...@@ -52,87 +52,87 @@ ...@@ -52,87 +52,87 @@
<link> <link>
<name>vivado_logs/VivadoBitstream.log</name> <name>vivado_logs/VivadoBitstream.log</name>
<type>1</type> <type>1</type>
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</link> </link>
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<name>vivado_logs/VivadoOpt.log</name> <name>vivado_logs/VivadoOpt.log</name>
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<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOpt-20160201011135425.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoOpt-20160202171857055.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOptPhys.log</name> <name>vivado_logs/VivadoOptPhys.log</name>
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</link> </link>
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</link> </link>
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<name>vivado_logs/VivadoPlace.log</name> <name>vivado_logs/VivadoPlace.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoPlace-20160201011135425.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoPlace-20160202171857055.log</location>
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<name>vivado_state/x393_sata-opt-phys.dcp</name> <name>vivado_state/x393_sata-opt-phys.dcp</name>
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<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-phys-20160201011135425.dcp</location> <location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-phys-20160202171857055.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/x393_sata-opt-power.dcp</name> <name>vivado_state/x393_sata-opt-power.dcp</name>
<type>1</type> <type>1</type>
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<name>vivado_state/x393_sata-opt.dcp</name> <name>vivado_state/x393_sata-opt.dcp</name>
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</link> </link>
<link> <link>
<name>vivado_state/x393_sata-place.dcp</name> <name>vivado_state/x393_sata-place.dcp</name>
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</link> </link>
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<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-route-20160201011135425.dcp</location> <location>/home/andrey/git/x393_sata/vivado_state/x393_sata-route-20160202171857055.dcp</location>
</link> </link>
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<name>vivado_state/x393_sata-synth.dcp</name> <name>vivado_state/x393_sata-synth.dcp</name>
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<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-synth-20160201011135425.dcp</location> <location>/home/andrey/git/x393_sata/vivado_state/x393_sata-synth-20160202171857055.dcp</location>
</link> </link>
</linkedResources> </linkedResources>
</projectDescription> </projectDescription>
ahci/ahci_sata_layers.v
View file @ 4626e2cd
...@@ -107,7 +107,8 @@ module ahci_sata_layers #( ...@@ -107,7 +107,8 @@ module ahci_sata_layers #(
localparam H2D_TYPE_FIS_HEAD = 1; localparam H2D_TYPE_FIS_HEAD = 1;
localparam H2D_TYPE_FIS_LAST = 2; localparam H2D_TYPE_FIS_LAST = 2;
wire phy_ready; wire phy_ready; // active when GTX gets aligned output
wire link_established; // Received 3 back-to-back non-ALIGNp
wire [31:0] ll_h2d_data_in; wire [31:0] ll_h2d_data_in;
wire [1:0] ll_h2d_mask_in; wire [1:0] ll_h2d_mask_in;
wire ll_strobe_out; wire ll_strobe_out;
...@@ -168,9 +169,18 @@ module ahci_sata_layers #( ...@@ -168,9 +169,18 @@ module ahci_sata_layers #(
wire d2h_fifo_wr = ll_d2h_valid || fis_over_r; // fis_over_r will push FIS end to FIFO wire d2h_fifo_wr = ll_d2h_valid || fis_over_r; // fis_over_r will push FIS end to FIFO
reg h2d_pending; // HBA started sending FIS to fifo reg h2d_pending; // HBA started sending FIS to fifo
assign ll_h2d_last = (h2d_type_out == H2D_TYPE_FIS_LAST); wire [31:0] debug_phy;
wire [31:0] debug_link;
wire debug_detected_alignp; // oob detects ALIGNp, but not the link layer
// assign debug_sata = {link_established, phy_ready, debug_phy[29:16],debug_link[15:0]}; //
assign debug_sata = debug_link[31:0]; //
/// assign debug_sata = debug_phy;
assign ll_h2d_last = (h2d_type_out == H2D_TYPE_FIS_LAST);
assign d2h_valid = d2h_nempty; assign d2h_valid = d2h_nempty;
assign d2h_many = |d2h_fill[FIFO_ADDR_WIDTH:3]; // assign d2h_many = |d2h_fill[FIFO_ADDR_WIDTH:3]; //
...@@ -180,15 +190,21 @@ module ahci_sata_layers #( ...@@ -180,15 +190,21 @@ module ahci_sata_layers #(
// assign ll_frame_req_w = !ll_frame_busy && h2d_pending && (((h2d_type == H2D_TYPE_FIS_LAST) && h2d_fifo_wr ) || (|h2d_fill[FIFO_ADDR_WIDTH : BITS_TO_START_XMIT])); // assign ll_frame_req_w = !ll_frame_busy && h2d_pending && (((h2d_type == H2D_TYPE_FIS_LAST) && h2d_fifo_wr ) || (|h2d_fill[FIFO_ADDR_WIDTH : BITS_TO_START_XMIT]));
// Separating different types of errors, sync_escape from other problems. TODO: route individual errors to set SERR bits // Separating different types of errors, sync_escape from other problems. TODO: route individual errors to set SERR bits
//assign incom_invalidate = state_rcvr_eof & crc_bad & ~alignes_pair | state_rcvr_data & dword_val & rcvd_dword[CODE_WTRMP]; //assign incom_invalidate = state_rcvr_eof & crc_bad & ~alignes_pair | state_rcvr_data & dword_val & rcvd_dword[CODE_WTRMP];
assign phy_speed = phy_ready ? PHY_SPEED:0; // assign phy_speed = phy_ready ? PHY_SPEED:0;
// assign serr_DB = phy_ready && (|ph2ll_err_out);
assign serr_DB = phy_ready && (|ph2ll_err_out); // assign serr_DH = phy_ready && (xmit_err);
assign serr_DH = phy_ready && (xmit_err); assign phy_speed = link_established ? PHY_SPEED:0;
assign serr_DB = link_established && (|ph2ll_err_out);
assign serr_DH = link_established && (xmit_err);
//
// not yet assigned errors // not yet assigned errors
assign serr_DT = phy_ready && (comreset_send); // RWC: Transport state transition error /// assign serr_DT = phy_ready && (comreset_send); // RWC: Transport state transition error
assign serr_DS = phy_ready && (cominit_got); // RWC: Link sequence error /// assign serr_DS = phy_ready && (cominit_got); // RWC: Link sequence error
assign serr_DC = phy_ready && (serr_DW); // RWC: CRC error in Link layer /// assign serr_DC = phy_ready && (serr_DW); // RWC: CRC error in Link layer
assign serr_DT = phy_ready && (0); // RWC: Transport state transition error
assign serr_DS = phy_ready && (0); // RWC: Link sequence error
assign serr_DC = phy_ready && (0); // RWC: CRC error in Link layer
// assign serr_DB = phy_ready && (0); // RWC: 10B to 8B decode error // assign serr_DB = phy_ready && (0); // RWC: 10B to 8B decode error
assign serr_DI = phy_ready && (0); // RWC: PHY Internal Error assign serr_DI = phy_ready && (0); // RWC: PHY Internal Error
assign serr_EP = phy_ready && (0); // RWC: Protocol Error - a violation of SATA protocol detected assign serr_EP = phy_ready && (0); // RWC: Protocol Error - a violation of SATA protocol detected
...@@ -239,6 +255,7 @@ module ahci_sata_layers #( ...@@ -239,6 +255,7 @@ module ahci_sata_layers #(
.sync_escape_req (syncesc_send), // input wire // TL demands to brutally cancel current transaction .sync_escape_req (syncesc_send), // input wire // TL demands to brutally cancel current transaction
.sync_escape_ack (syncesc_send_done), // output wire // acknowlegement of a successful reception? .sync_escape_ack (syncesc_send_done), // output wire // acknowlegement of a successful reception?
.incom_stop_req (pcmd_st_cleared), // input wire // TL demands to stop current recieving session .incom_stop_req (pcmd_st_cleared), // input wire // TL demands to stop current recieving session
.link_established (link_established),
// inputs from phy // inputs from phy
.phy_ready (phy_ready), // input wire // phy is ready - link is established .phy_ready (phy_ready), // input wire // phy is ready - link is established
// data-primitives stream from phy // data-primitives stream from phy
...@@ -247,7 +264,8 @@ module ahci_sata_layers #( ...@@ -247,7 +264,8 @@ module ahci_sata_layers #(
.phy_err_in (ph2ll_err_out), // input[3:0] wire // disperr | notintable .phy_err_in (ph2ll_err_out), // input[3:0] wire // disperr | notintable
// to phy // to phy
.phy_data_out (ll2ph_data_in), // output[31:0] wire .phy_data_out (ll2ph_data_in), // output[31:0] wire
.phy_isk_out (ll2ph_charisk_in) // output[3:0] wire // charisk .phy_isk_out (ll2ph_charisk_in), // output[3:0] wire // charisk
.debug_out (debug_link)
); );
always @ (posedge clk) begin always @ (posedge clk) begin
...@@ -304,9 +322,8 @@ module ahci_sata_layers #( ...@@ -304,9 +322,8 @@ module ahci_sata_layers #(
.comwake_got (serr_DW), // output wire .comwake_got (serr_DW), // output wire
.cplllock_debug (), .cplllock_debug (),
.usrpll_locked_debug(), .usrpll_locked_debug(),
.debug_sata (debug_sata) .debug_sata (debug_phy)
,.debug_detected_alignp(debug_detected_alignp)
); );
fifo_sameclock_control #( fifo_sameclock_control #(
......
ahci/ahci_top.v
View file @ 4626e2cd
...@@ -690,7 +690,8 @@ module ahci_top#( ...@@ -690,7 +690,8 @@ module ahci_top#(
.afi_cache_set (set_axi_cache_mode), // output .afi_cache_set (set_axi_cache_mode), // output
.was_hba_rst (was_hba_rst), // output .was_hba_rst (was_hba_rst), // output
.was_port_rst (was_port_rst), // output .was_port_rst (was_port_rst), // output
.debug_in ({2'b0, last_jump_addr[9:0], debug_in[19:0]}) // .debug_in ({2'b0, last_jump_addr[9:0], debug_in[19:0]})
.debug_in (debug_in[31:0])
); );
ahci_ctrl_stat #( ahci_ctrl_stat #(
.ADDRESS_BITS (ADDRESS_BITS) .ADDRESS_BITS (ADDRESS_BITS)
......
device/sata_device.v
View file @ 4626e2cd
...@@ -60,6 +60,24 @@ reg [31:0] dev2phy_data = 32'hB5B5957C; // SYNCP ...@@ -60,6 +60,24 @@ reg [31:0] dev2phy_data = 32'hB5B5957C; // SYNCP
reg [3:0] dev2phy_isk = 4'h1; reg [3:0] dev2phy_isk = 4'h1;
reg [2:0] phy_ready_syncp_r; // allow device to send 3 SYNCp before getting ready reg [2:0] phy_ready_syncp_r; // allow device to send 3 SYNCp before getting ready
reg [4:0] serial_delay = 7; // delay output to check host alignment
localparam DEV_ALIGN_PERIOD = 32; // make it more frequent than 250
//integer align_cntr = DEV_ALIGN_PERIOD;
reg [7:0] align_cntr = DEV_ALIGN_PERIOD;
initial forever @ (posedge clk) begin
if (align_cntr > 0) align_cntr = align_cntr - 1;
end
task send_align_pair_if_needed;
if (align_cntr ==0) begin
dev2phy_data <= PRIM_ALIGNP;
dev2phy_isk <= 4'h1;
align_cntr = DEV_ALIGN_PERIOD;
@ (posedge clk);
@ (posedge clk);
end
endtask
sata_phy_dev phy( sata_phy_dev phy(
// pll reset // pll reset
...@@ -84,7 +102,9 @@ sata_phy_dev phy( ...@@ -84,7 +102,9 @@ sata_phy_dev phy(
.ll_err_out (phy2dev_err), .ll_err_out (phy2dev_err),
.ll_data_in (dev2phy_data), .ll_data_in (dev2phy_data),
.ll_charisk_in (dev2phy_isk) .ll_charisk_in (dev2phy_isk),
.serial_delay (serial_delay) // delay output to check host alignment
); );
localparam [31:0] PRIM_SYNCP = {3'd5, 5'd21, 3'd5, 5'd21, 3'd4, 5'd21, 3'd3, 5'd28}; localparam [31:0] PRIM_SYNCP = {3'd5, 5'd21, 3'd5, 5'd21, 3'd4, 5'd21, 3'd3, 5'd28};
...@@ -1186,6 +1206,7 @@ endfunction ...@@ -1186,6 +1206,7 @@ endfunction
task linkSendData; task linkSendData;
input [31:0] data; input [31:0] data;
begin begin
send_align_pair_if_needed;
dev2phy_data <= data; dev2phy_data <= data;
dev2phy_isk <= 4'h0; dev2phy_isk <= 4'h0;
end end
...@@ -1198,9 +1219,11 @@ endtask ...@@ -1198,9 +1219,11 @@ endtask
task linkSendPrim; task linkSendPrim;
input [111:0] type; input [111:0] type;
begin begin
// send_align_pair_if_needed;
case (type) case (type)
"SYNC": "SYNC":
begin begin
send_align_pair_if_needed;
dev2phy_data <= PRIM_SYNCP; dev2phy_data <= PRIM_SYNCP;
dev2phy_isk <= 4'h1; dev2phy_isk <= 4'h1;
end end
......
device/sata_phy_dev.v
View file @ 4626e2cd
...@@ -62,7 +62,10 @@ module sata_phy_dev #( ...@@ -62,7 +62,10 @@ module sata_phy_dev #(
// from link layer // from link layer
input wire [31:0] ll_data_in, input wire [31:0] ll_data_in,
input wire [3:0] ll_charisk_in input wire [3:0] ll_charisk_in,
input [4:0] serial_delay // delay output to check host alignment
); );
wire [31:0] txdata; wire [31:0] txdata;
...@@ -739,6 +742,15 @@ gtx_wrapper( ...@@ -739,6 +742,15 @@ gtx_wrapper(
.TXSYNCALLIN (1'b0), .TXSYNCALLIN (1'b0),
.TXSYNCIN (1'b0)*/ .TXSYNCIN (1'b0)*/
); );
// Serial data bit shift to check host alignment
wire tx_serial_clk=gtx_wrapper.gtx_gpl.channel.tx_serial_clk;
//reg [4:0] serial_delay = 0;
reg [31:0] txp_r;
reg [31:0] txn_r;
always @(posedge tx_serial_clk) begin
txp_r = {txp_r[30:0],txp};
txn_r = {txn_r[30:0],txn};
end
// align to 4-byte boundary // align to 4-byte boundary
reg twobytes_shift; reg twobytes_shift;
...@@ -761,8 +773,12 @@ assign drpclk = gtrefclk; ...@@ -761,8 +773,12 @@ assign drpclk = gtrefclk;
assign clk = usrclk2; assign clk = usrclk2;
assign rxn = rxn_in; assign rxn = rxn_in;
assign rxp = rxp_in; assign rxp = rxp_in;
assign txn_out = txn;
assign txp_out = txp; ///assign txn_out = txn;
///assign txp_out = txp;
assign txn_out = txn_r[serial_delay];
assign txp_out = txp_r[serial_delay];
//assign ll_data_out = rxdata_out; //assign ll_data_out = rxdata_out;
//assign ll_charisk_out = rxcharisk_out; //assign ll_charisk_out = rxcharisk_out;
//assign txdata_in = ll_data_in; //assign txdata_in = ll_data_in;
......
host/gtx_wrap.v
View file @ 4626e2cd
...@@ -624,7 +624,9 @@ gtxe2_channel_wrapper #( ...@@ -624,7 +624,9 @@ gtxe2_channel_wrapper #(
.RX_XCLK_SEL ("RXREC"), .RX_XCLK_SEL ("RXREC"),
.RX_DDI_SEL (6'b000000), .RX_DDI_SEL (6'b000000),
.RX_DEFER_RESET_BUF_EN ("TRUE"), .RX_DEFER_RESET_BUF_EN ("TRUE"),
.RXCDR_CFG (72'h03000023ff10200020), /// .RXCDR_CFG (72'h03000023ff10200020),// 1.6G - 6.25G, No SS, RXOUT_DIV=2
/// .RXCDR_CFG (72'h03800023ff10200008),// Guess for SS
.RXCDR_CFG (72'h03_8800_8BFF_4020_0008),// http://www.xilinx.com/support/answers/53364.html - SATA-2, div=2
.RXCDR_FR_RESET_ON_EIDLE (1'b0), .RXCDR_FR_RESET_ON_EIDLE (1'b0),
.RXCDR_HOLD_DURING_EIDLE (1'b0), .RXCDR_HOLD_DURING_EIDLE (1'b0),
.RXCDR_PH_RESET_ON_EIDLE (1'b0), .RXCDR_PH_RESET_ON_EIDLE (1'b0),
...@@ -703,7 +705,8 @@ gtxe2_channel_wrapper #( ...@@ -703,7 +705,8 @@ gtxe2_channel_wrapper #(
.RX_DFE_H4_CFG (11'b00011110000), .RX_DFE_H4_CFG (11'b00011110000),
.RX_DFE_H5_CFG (11'b00011100000), .RX_DFE_H5_CFG (11'b00011100000),
.RX_DFE_KL_CFG (13'b0000011111110), .RX_DFE_KL_CFG (13'b0000011111110),
.RX_DFE_LPM_CFG (16'h0954), /// .RX_DFE_LPM_CFG (16'h0954),
.RX_DFE_LPM_CFG (16'h0904),
.RX_DFE_LPM_HOLD_DURING_EIDLE (1'b0), .RX_DFE_LPM_HOLD_DURING_EIDLE (1'b0),
.RX_DFE_UT_CFG (17'b10001111000000000), .RX_DFE_UT_CFG (17'b10001111000000000),
.RX_DFE_VP_CFG (17'b00011111100000011), .RX_DFE_VP_CFG (17'b00011111100000011),
......
host/link.v
View file @ 4626e2cd
This diff is collapsed.
host/oob.v
View file @ 4626e2cd
...@@ -100,6 +100,8 @@ module oob #( ...@@ -100,6 +100,8 @@ module oob #(
// noone responds to our cominits // noone responds to our cominits
output wire oob_silence output wire oob_silence
,output debug_detected_alignp
`ifdef OOB_MULTISPEED `ifdef OOB_MULTISPEED
//TODO //TODO
// !!Implement it later on, ref to gen.adjustment fsm in the notebook!! // !!Implement it later on, ref to gen.adjustment fsm in the notebook!!
...@@ -119,6 +121,8 @@ module oob #( ...@@ -119,6 +121,8 @@ module oob #(
`endif //OOB_MULTISPEED `endif //OOB_MULTISPEED
); );
assign debug_detected_alignp = detected_alignp;
`ifdef SIMULATION `ifdef SIMULATION
reg [639:0] HOST_OOB_TITLE ='bz; // to show human-readable state in the GTKWave reg [639:0] HOST_OOB_TITLE ='bz; // to show human-readable state in the GTKWave
`endif `endif
...@@ -150,6 +154,9 @@ reg [DATA_BYTE_WIDTH - 1:0] rxcharisk; ...@@ -150,6 +154,9 @@ reg [DATA_BYTE_WIDTH - 1:0] rxcharisk;
// primitives detection // primitives detection
wire detected_alignp; wire detected_alignp;
localparam NUM_CON_ALIGNS = 1024;
reg detected_alignp_r; // debugging - N-th ALIGNp primitive
reg [12:0] detected_alignp_cntr; // count detected ALIGNp - do not respond yet
wire detected_syncp; wire detected_syncp;
// wait until device's cominit is done // wait until device's cominit is done
...@@ -222,7 +229,8 @@ assign set_recal_tx = state_wait_comwake & rxcomwakedet_l & rxcomwake_done; ...@@ -222,7 +229,8 @@ assign set_recal_tx = state_wait_comwake & rxcomwakedet_l & rxcomwake_done;
assign set_wait_eidle = state_recal_tx & recal_tx_done; assign set_wait_eidle = state_recal_tx & recal_tx_done;
assign set_wait_rxrst = state_wait_eidle & eidle_timer_done; assign set_wait_rxrst = state_wait_eidle & eidle_timer_done;
assign set_wait_align = state_wait_rxrst & rxreset_ack; assign set_wait_align = state_wait_rxrst & rxreset_ack;
assign set_wait_synp = state_wait_align & detected_alignp; //assign set_wait_synp = state_wait_align & detected_alignp;
assign set_wait_synp = state_wait_align & (detected_alignp_r); // N previous were both ALIGNp
assign set_wait_linkup = state_wait_synp & detected_syncp; assign set_wait_linkup = state_wait_synp & detected_syncp;
assign set_error = timer_fin & (state_wait_cominit | state_wait_comwake | state_recal_tx | state_wait_eidle | state_wait_rxrst | state_wait_align | state_wait_synp/* | state_wait_linkup*/); assign set_error = timer_fin & (state_wait_cominit | state_wait_comwake | state_recal_tx | state_wait_eidle | state_wait_rxrst | state_wait_align | state_wait_synp/* | state_wait_linkup*/);
assign clr_wait_cominit = set_wait_comwake | set_error; assign clr_wait_cominit = set_wait_comwake | set_error;
...@@ -306,19 +314,19 @@ generate ...@@ -306,19 +314,19 @@ generate
always @ (posedge clk) always @ (posedge clk)
detected_alignp_f <= rst | ~state_wait_align ? 1'b0 : detected_alignp_f <= rst | ~state_wait_align ? 1'b0 :
~|(rxdata[15:0] ^ alignp[15:0]) & ~|(rxcharisk[1:0] ^ 2'b01); // {D10.2, K28.5} ~|(rxdata[15:0] ^ alignp[15:0]) & ~|(rxcharisk[1:0] ^ 2'b01); // {D10.2, K28.5}
assign detected_alignp = detected_alignp_f & ~|(rxdata[15:0] ^ alignp[31:16]) & ~|(rxcharisk[1:0] ^ 2'b00); // {D27.3, D10.2} // SuppressThisWarning VEditor -warning would be fixed in future releases assign detected_alignp = detected_alignp_f & ~|(rxdata[15:0] ^ alignp[31:16]) & ~|(rxcharisk[1:0] ^ 2'b00); // {D27.3, D10.2} // S uppressThisWarning VEditor -warning would be fixed in future releases
reg detected_syncp_f; reg detected_syncp_f;
always @ (posedge clk) always @ (posedge clk)
detected_syncp_f <= rst | ~state_wait_synp ? 1'b0 : detected_syncp_f <= rst | ~state_wait_synp ? 1'b0 :
~|(rxdata[15:0] ^ syncp[15:0]) & ~|(rxcharisk[1:0] ^ 2'b01); // {D21.4, K28.3} ~|(rxdata[15:0] ^ syncp[15:0]) & ~|(rxcharisk[1:0] ^ 2'b01); // {D21.4, K28.3}
assign detected_syncp = detected_syncp_f & ~|(rxdata[15:0] ^ syncp[31:16]) & ~|(rxcharisk[1:0] ^ 2'b00); // {D21.5, D21.5} // SuppressThisWarning VEditor -warning would be fixed in future releases assign detected_syncp = detected_syncp_f & ~|(rxdata[15:0] ^ syncp[31:16]) & ~|(rxcharisk[1:0] ^ 2'b00); // {D21.5, D21.5} // S uppressThisWarning VEditor -warning would be fixed in future releases
end end
else else
if (DATA_BYTE_WIDTH == 4) if (DATA_BYTE_WIDTH == 4)
begin begin
assign detected_alignp = ~|(rxdata[31:0] ^ alignp[31:0]) & ~|(rxcharisk[3:0] ^ 4'h1); // {D27.3, D10.2, D10.2, K28.5} // SuppressThisWarning VEditor -warning would be fixed in future releases assign detected_alignp = ~|(rxdata[31:0] ^ alignp[31:0]) & ~|(rxcharisk[3:0] ^ 4'h1); // {D27.3, D10.2, D10.2, K28.5} // S uppressThisWarning VEditor -warning would be fixed in future releases
assign detected_syncp = ~|(rxdata[31:0] ^ syncp[31:0]) & ~|(rxcharisk[3:0] ^ 4'h1); // {D21.5, D21.5, D21.4, K28.3} // SuppressThisWarning VEditor -warning would be fixed in future releases assign detected_syncp = ~|(rxdata[31:0] ^ syncp[31:0]) & ~|(rxcharisk[3:0] ^ 4'h1); // {D21.5, D21.5, D21.4, K28.3} // S uppressThisWarning VEditor -warning would be fixed in future releases
end end
else else
if (DATA_BYTE_WIDTH == 8) if (DATA_BYTE_WIDTH == 8)
...@@ -450,6 +458,12 @@ assign eidle_timer_done = eidle_timer == 64; ...@@ -450,6 +458,12 @@ assign eidle_timer_done = eidle_timer == 64;
always @ (posedge clk) always @ (posedge clk)
eidle_timer <= rst | rxelecidle | ~state_wait_eidle ? 8'b0 : eidle_timer + CLK_TO_TIMER_CONTRIB[7:0]; eidle_timer <= rst | rxelecidle | ~state_wait_eidle ? 8'b0 : eidle_timer + CLK_TO_TIMER_CONTRIB[7:0];
always @ (posedge clk) begin
if (rst || !detected_alignp) detected_alignp_cntr <= NUM_CON_ALIGNS;
else if (|detected_alignp_cntr) detected_alignp_cntr <= detected_alignp_cntr -1;
detected_alignp_r <= detected_alignp_cntr == 0;
end
always @ (posedge clk) always @ (posedge clk)
debug <= rst ? 12'h000 : { debug <= rst ? 12'h000 : {
state_idle, state_idle,
......
host/oob_ctrl.v
View file @ 4626e2cd
...@@ -63,6 +63,7 @@ module oob_ctrl #( ...@@ -63,6 +63,7 @@ module oob_ctrl #(
output wire phy_ready, // output wire // shows if channel is ready output wire phy_ready, // output wire // shows if channel is ready
input set_offline, // input wire // electrically idle // From input set_offline, // input wire // electrically idle // From
input comreset_send // input wire // Not possible yet? // From input comreset_send // input wire // Not possible yet? // From
,output debug_detected_alignp
); );
// oob sequence needs to be issued // oob sequence needs to be issued
...@@ -160,6 +161,7 @@ oob ...@@ -160,6 +161,7 @@ oob
.oob_incompatible (oob_incompatible),// output wire // incompatible host-device speed grades (host cannot lock to alignp) .oob_incompatible (oob_incompatible),// output wire // incompatible host-device speed grades (host cannot lock to alignp)
.oob_error (oob_error), // output wire // timeout in an unexpected place .oob_error (oob_error), // output wire // timeout in an unexpected place
.oob_silence (oob_silence) // output wire // noone responds to our cominits .oob_silence (oob_silence) // output wire // noone responds to our cominits
,.debug_detected_alignp(debug_detected_alignp)
); );
......
host/sata_phy.v
View file @ 4626e2cd
...@@ -78,6 +78,8 @@ module sata_phy #( ...@@ -78,6 +78,8 @@ module sata_phy #(
output cplllock_debug, output cplllock_debug,
output usrpll_locked_debug, output usrpll_locked_debug,
output [31:0] debug_sata output [31:0] debug_sata
,output debug_detected_alignp
); );
wire [DATA_BYTE_WIDTH * 8 - 1:0] txdata; wire [DATA_BYTE_WIDTH * 8 - 1:0] txdata;
...@@ -168,7 +170,7 @@ oob_ctrl oob_ctrl( ...@@ -168,7 +170,7 @@ oob_ctrl oob_ctrl(
// To/from AHCI // To/from AHCI
.set_offline (set_offline), // input .set_offline (set_offline), // input
.comreset_send (comreset_send) // input .comreset_send (comreset_send) // input
,.debug_detected_alignp(debug_detected_alignp)
); );
wire cplllockdetclk; // TODO wire cplllockdetclk; // TODO
...@@ -491,6 +493,10 @@ reg [3:0] debug_cntr1; ...@@ -491,6 +493,10 @@ reg [3:0] debug_cntr1;
reg [3:0] debug_cntr2; reg [3:0] debug_cntr2;
reg [3:0] debug_cntr3; reg [3:0] debug_cntr3;
reg [3:0] debug_cntr4; reg [3:0] debug_cntr4;
reg [15:0] debug_cntr5;
reg [15:0] debug_cntr6;
reg [1:0] debug_rxbyteisaligned_r;
reg debug_error_r;
//txoutclk //txoutclk
always @ (posedge gtrefclk) begin always @ (posedge gtrefclk) begin
if (extrst) debug_cntr1 <= 0; if (extrst) debug_cntr1 <= 0;
...@@ -512,6 +518,17 @@ always @ (posedge txoutclk) begin ...@@ -512,6 +518,17 @@ always @ (posedge txoutclk) begin
else debug_cntr4 <= debug_cntr4 + 1; else debug_cntr4 <= debug_cntr4 + 1;
end end
always @ (posedge clk) begin
debug_rxbyteisaligned_r <= {debug_rxbyteisaligned_r[0],rxbyteisaligned};
debug_error_r <= |ll_err_out;
if (rst) debug_cntr5 <= 0;
else if (debug_rxbyteisaligned_r==1) debug_cntr5 <= debug_cntr5 + 1;
if (rst) debug_cntr6 <= 0;
else if (debug_error_r) debug_cntr6 <= debug_cntr6 + 1;
end
/*
assign debug_sata[ 3: 0] = debug_cntr1; assign debug_sata[ 3: 0] = debug_cntr1;
assign debug_sata[ 7: 4] = debug_cntr2; assign debug_sata[ 7: 4] = debug_cntr2;
assign debug_sata[11: 8] = debug_cntr3; assign debug_sata[11: 8] = debug_cntr3;
...@@ -524,5 +541,8 @@ assign debug_sata[17] = txreset; ...@@ -524,5 +541,8 @@ assign debug_sata[17] = txreset;
assign debug_sata[18] = txpcsreset; assign debug_sata[18] = txpcsreset;
assign debug_sata[19] = txelecidle; assign debug_sata[19] = txelecidle;
assign debug_sata[23:20] = debug_cntr4; assign debug_sata[23:20] = debug_cntr4;
*/
//assign phy_ready = link_state & gtx_ready & rxbyteisaligned;
assign debug_sata = {debug_cntr6,debug_cntr5};
endmodule endmodule
py393sata/x393sata.py
View file @ 4626e2cd
This diff is collapsed.
tb/tb_ahci.tf
View file @ 4626e2cd
...@@ -985,6 +985,7 @@ initial begin //Host ...@@ -985,6 +985,7 @@ initial begin //Host
TESTBENCH_TITLE = "DMA transfer to device completed"; TESTBENCH_TITLE = "DMA transfer to device completed";
$display("[Testbench]: %s @%t", TESTBENCH_TITLE, $time); $display("[Testbench]: %s @%t", TESTBENCH_TITLE, $time);
repeat (50) @(posedge CLK); repeat (50) @(posedge CLK);
/*
// Reset port // Reset port
maxigp1_print ('h3ff << 2,"DEBUG_REGISTER"); maxigp1_print ('h3ff << 2,"DEBUG_REGISTER");
maxigp1_writep (HBA_PORT__PxSCTL__DET__ADDR << 2, 1); // Reset SATA maxigp1_writep (HBA_PORT__PxSCTL__DET__ADDR << 2, 1); // Reset SATA
...@@ -994,6 +995,7 @@ initial begin //Host ...@@ -994,6 +995,7 @@ initial begin //Host
maxigp1_writep (HBA_PORT__PxSCTL__DET__ADDR << 2, 0); // Reset Off maxigp1_writep (HBA_PORT__PxSCTL__DET__ADDR << 2, 0); // Reset Off
repeat (1000) @(posedge CLK); repeat (1000) @(posedge CLK);
maxigp1_print ('h3ff << 2,"DEBUG_REGISTER"); maxigp1_print ('h3ff << 2,"DEBUG_REGISTER");
*/
//DET //DET
// $finish; // $finish;
//HBA_PORT__PxIE__DHRE__MASK = 'h1; //HBA_PORT__PxIE__DHRE__MASK = 'h1;
......
tb_ahci_01.sav
View file @ 4626e2cd
This diff is collapsed.
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