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Commit 4626e2cd authored by Andrey Filippov's avatar Andrey Filippov
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hardware debugging

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.project
View file @ 4626e2cd
...@@ -52,87 +52,87 @@ ...@@ -52,87 +52,87 @@
<link> <link>
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<type>1</type> <type>1</type>
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</link> </link>
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</link> </link>
<link> <link>
<name>vivado_logs/VivadoOptPhys.log</name> <name>vivado_logs/VivadoOptPhys.log</name>
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</link> </link>
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<name>vivado_state/x393_sata-opt-phys.dcp</name> <name>vivado_state/x393_sata-opt-phys.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-phys-20160201011135425.dcp</location> <location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-phys-20160202171857055.dcp</location>
</link> </link>
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</link> </link>
<link> <link>
<name>vivado_state/x393_sata-place.dcp</name> <name>vivado_state/x393_sata-place.dcp</name>
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</link> </link>
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<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-route-20160201011135425.dcp</location> <location>/home/andrey/git/x393_sata/vivado_state/x393_sata-route-20160202171857055.dcp</location>
</link> </link>
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<name>vivado_state/x393_sata-synth.dcp</name> <name>vivado_state/x393_sata-synth.dcp</name>
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<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-synth-20160201011135425.dcp</location> <location>/home/andrey/git/x393_sata/vivado_state/x393_sata-synth-20160202171857055.dcp</location>
</link> </link>
</linkedResources> </linkedResources>
</projectDescription> </projectDescription>
ahci/ahci_sata_layers.v
View file @ 4626e2cd
...@@ -107,7 +107,8 @@ module ahci_sata_layers #( ...@@ -107,7 +107,8 @@ module ahci_sata_layers #(
localparam H2D_TYPE_FIS_HEAD = 1; localparam H2D_TYPE_FIS_HEAD = 1;
localparam H2D_TYPE_FIS_LAST = 2; localparam H2D_TYPE_FIS_LAST = 2;
wire phy_ready; wire phy_ready; // active when GTX gets aligned output
wire link_established; // Received 3 back-to-back non-ALIGNp
wire [31:0] ll_h2d_data_in; wire [31:0] ll_h2d_data_in;
wire [1:0] ll_h2d_mask_in; wire [1:0] ll_h2d_mask_in;
wire ll_strobe_out; wire ll_strobe_out;
...@@ -168,9 +169,18 @@ module ahci_sata_layers #( ...@@ -168,9 +169,18 @@ module ahci_sata_layers #(
wire d2h_fifo_wr = ll_d2h_valid || fis_over_r; // fis_over_r will push FIS end to FIFO wire d2h_fifo_wr = ll_d2h_valid || fis_over_r; // fis_over_r will push FIS end to FIFO
reg h2d_pending; // HBA started sending FIS to fifo reg h2d_pending; // HBA started sending FIS to fifo
assign ll_h2d_last = (h2d_type_out == H2D_TYPE_FIS_LAST); wire [31:0] debug_phy;
wire [31:0] debug_link;
wire debug_detected_alignp; // oob detects ALIGNp, but not the link layer
// assign debug_sata = {link_established, phy_ready, debug_phy[29:16],debug_link[15:0]}; //
assign debug_sata = debug_link[31:0]; //
/// assign debug_sata = debug_phy;
assign ll_h2d_last = (h2d_type_out == H2D_TYPE_FIS_LAST);
assign d2h_valid = d2h_nempty; assign d2h_valid = d2h_nempty;
assign d2h_many = |d2h_fill[FIFO_ADDR_WIDTH:3]; // assign d2h_many = |d2h_fill[FIFO_ADDR_WIDTH:3]; //
...@@ -180,15 +190,21 @@ module ahci_sata_layers #( ...@@ -180,15 +190,21 @@ module ahci_sata_layers #(
// assign ll_frame_req_w = !ll_frame_busy && h2d_pending && (((h2d_type == H2D_TYPE_FIS_LAST) && h2d_fifo_wr ) || (|h2d_fill[FIFO_ADDR_WIDTH : BITS_TO_START_XMIT])); // assign ll_frame_req_w = !ll_frame_busy && h2d_pending && (((h2d_type == H2D_TYPE_FIS_LAST) && h2d_fifo_wr ) || (|h2d_fill[FIFO_ADDR_WIDTH : BITS_TO_START_XMIT]));
// Separating different types of errors, sync_escape from other problems. TODO: route individual errors to set SERR bits // Separating different types of errors, sync_escape from other problems. TODO: route individual errors to set SERR bits
//assign incom_invalidate = state_rcvr_eof & crc_bad & ~alignes_pair | state_rcvr_data & dword_val & rcvd_dword[CODE_WTRMP]; //assign incom_invalidate = state_rcvr_eof & crc_bad & ~alignes_pair | state_rcvr_data & dword_val & rcvd_dword[CODE_WTRMP];
assign phy_speed = phy_ready ? PHY_SPEED:0; // assign phy_speed = phy_ready ? PHY_SPEED:0;
// assign serr_DB = phy_ready && (|ph2ll_err_out);
assign serr_DB = phy_ready && (|ph2ll_err_out); // assign serr_DH = phy_ready && (xmit_err);
assign serr_DH = phy_ready && (xmit_err); assign phy_speed = link_established ? PHY_SPEED:0;
assign serr_DB = link_established && (|ph2ll_err_out);
assign serr_DH = link_established && (xmit_err);
//
// not yet assigned errors // not yet assigned errors
assign serr_DT = phy_ready && (comreset_send); // RWC: Transport state transition error /// assign serr_DT = phy_ready && (comreset_send); // RWC: Transport state transition error
assign serr_DS = phy_ready && (cominit_got); // RWC: Link sequence error /// assign serr_DS = phy_ready && (cominit_got); // RWC: Link sequence error
assign serr_DC = phy_ready && (serr_DW); // RWC: CRC error in Link layer /// assign serr_DC = phy_ready && (serr_DW); // RWC: CRC error in Link layer
assign serr_DT = phy_ready && (0); // RWC: Transport state transition error
assign serr_DS = phy_ready && (0); // RWC: Link sequence error
assign serr_DC = phy_ready && (0); // RWC: CRC error in Link layer
// assign serr_DB = phy_ready && (0); // RWC: 10B to 8B decode error // assign serr_DB = phy_ready && (0); // RWC: 10B to 8B decode error
assign serr_DI = phy_ready && (0); // RWC: PHY Internal Error assign serr_DI = phy_ready && (0); // RWC: PHY Internal Error
assign serr_EP = phy_ready && (0); // RWC: Protocol Error - a violation of SATA protocol detected assign serr_EP = phy_ready && (0); // RWC: Protocol Error - a violation of SATA protocol detected
...@@ -239,6 +255,7 @@ module ahci_sata_layers #( ...@@ -239,6 +255,7 @@ module ahci_sata_layers #(
.sync_escape_req (syncesc_send), // input wire // TL demands to brutally cancel current transaction .sync_escape_req (syncesc_send), // input wire // TL demands to brutally cancel current transaction
.sync_escape_ack (syncesc_send_done), // output wire // acknowlegement of a successful reception? .sync_escape_ack (syncesc_send_done), // output wire // acknowlegement of a successful reception?
.incom_stop_req (pcmd_st_cleared), // input wire // TL demands to stop current recieving session .incom_stop_req (pcmd_st_cleared), // input wire // TL demands to stop current recieving session
.link_established (link_established),
// inputs from phy // inputs from phy
.phy_ready (phy_ready), // input wire // phy is ready - link is established .phy_ready (phy_ready), // input wire // phy is ready - link is established
// data-primitives stream from phy // data-primitives stream from phy
...@@ -247,7 +264,8 @@ module ahci_sata_layers #( ...@@ -247,7 +264,8 @@ module ahci_sata_layers #(
.phy_err_in (ph2ll_err_out), // input[3:0] wire // disperr | notintable .phy_err_in (ph2ll_err_out), // input[3:0] wire // disperr | notintable
// to phy // to phy
.phy_data_out (ll2ph_data_in), // output[31:0] wire .phy_data_out (ll2ph_data_in), // output[31:0] wire
.phy_isk_out (ll2ph_charisk_in) // output[3:0] wire // charisk .phy_isk_out (ll2ph_charisk_in), // output[3:0] wire // charisk
.debug_out (debug_link)
); );
always @ (posedge clk) begin always @ (posedge clk) begin
...@@ -304,9 +322,8 @@ module ahci_sata_layers #( ...@@ -304,9 +322,8 @@ module ahci_sata_layers #(
.comwake_got (serr_DW), // output wire .comwake_got (serr_DW), // output wire
.cplllock_debug (), .cplllock_debug (),
.usrpll_locked_debug(), .usrpll_locked_debug(),
.debug_sata (debug_sata) .debug_sata (debug_phy)
,.debug_detected_alignp(debug_detected_alignp)
); );
fifo_sameclock_control #( fifo_sameclock_control #(
......
ahci/ahci_top.v
View file @ 4626e2cd
...@@ -690,7 +690,8 @@ module ahci_top#( ...@@ -690,7 +690,8 @@ module ahci_top#(
.afi_cache_set (set_axi_cache_mode), // output .afi_cache_set (set_axi_cache_mode), // output
.was_hba_rst (was_hba_rst), // output .was_hba_rst (was_hba_rst), // output
.was_port_rst (was_port_rst), // output .was_port_rst (was_port_rst), // output
.debug_in ({2'b0, last_jump_addr[9:0], debug_in[19:0]}) // .debug_in ({2'b0, last_jump_addr[9:0], debug_in[19:0]})
.debug_in (debug_in[31:0])
); );
ahci_ctrl_stat #( ahci_ctrl_stat #(
.ADDRESS_BITS (ADDRESS_BITS) .ADDRESS_BITS (ADDRESS_BITS)
......
device/sata_device.v
View file @ 4626e2cd
...@@ -60,6 +60,24 @@ reg [31:0] dev2phy_data = 32'hB5B5957C; // SYNCP ...@@ -60,6 +60,24 @@ reg [31:0] dev2phy_data = 32'hB5B5957C; // SYNCP
reg [3:0] dev2phy_isk = 4'h1; reg [3:0] dev2phy_isk = 4'h1;
reg [2:0] phy_ready_syncp_r; // allow device to send 3 SYNCp before getting ready reg [2:0] phy_ready_syncp_r; // allow device to send 3 SYNCp before getting ready
reg [4:0] serial_delay = 7; // delay output to check host alignment
localparam DEV_ALIGN_PERIOD = 32; // make it more frequent than 250
//integer align_cntr = DEV_ALIGN_PERIOD;
reg [7:0] align_cntr = DEV_ALIGN_PERIOD;
initial forever @ (posedge clk) begin
if (align_cntr > 0) align_cntr = align_cntr - 1;
end
task send_align_pair_if_needed;
if (align_cntr ==0) begin
dev2phy_data <= PRIM_ALIGNP;
dev2phy_isk <= 4'h1;
align_cntr = DEV_ALIGN_PERIOD;
@ (posedge clk);
@ (posedge clk);
end
endtask
sata_phy_dev phy( sata_phy_dev phy(
// pll reset // pll reset
...@@ -84,7 +102,9 @@ sata_phy_dev phy( ...@@ -84,7 +102,9 @@ sata_phy_dev phy(
.ll_err_out (phy2dev_err), .ll_err_out (phy2dev_err),
.ll_data_in (dev2phy_data), .ll_data_in (dev2phy_data),
.ll_charisk_in (dev2phy_isk) .ll_charisk_in (dev2phy_isk),
.serial_delay (serial_delay) // delay output to check host alignment
); );
localparam [31:0] PRIM_SYNCP = {3'd5, 5'd21, 3'd5, 5'd21, 3'd4, 5'd21, 3'd3, 5'd28}; localparam [31:0] PRIM_SYNCP = {3'd5, 5'd21, 3'd5, 5'd21, 3'd4, 5'd21, 3'd3, 5'd28};
...@@ -1186,6 +1206,7 @@ endfunction ...@@ -1186,6 +1206,7 @@ endfunction
task linkSendData; task linkSendData;
input [31:0] data; input [31:0] data;
begin begin
send_align_pair_if_needed;
dev2phy_data <= data; dev2phy_data <= data;
dev2phy_isk <= 4'h0; dev2phy_isk <= 4'h0;
end end
...@@ -1198,9 +1219,11 @@ endtask ...@@ -1198,9 +1219,11 @@ endtask
task linkSendPrim; task linkSendPrim;
input [111:0] type; input [111:0] type;
begin begin
// send_align_pair_if_needed;
case (type) case (type)
"SYNC": "SYNC":
begin begin
send_align_pair_if_needed;
dev2phy_data <= PRIM_SYNCP; dev2phy_data <= PRIM_SYNCP;
dev2phy_isk <= 4'h1; dev2phy_isk <= 4'h1;
end end
......
device/sata_phy_dev.v
View file @ 4626e2cd
...@@ -62,7 +62,10 @@ module sata_phy_dev #( ...@@ -62,7 +62,10 @@ module sata_phy_dev #(
// from link layer // from link layer
input wire [31:0] ll_data_in, input wire [31:0] ll_data_in,
input wire [3:0] ll_charisk_in input wire [3:0] ll_charisk_in,
input [4:0] serial_delay // delay output to check host alignment
); );
wire [31:0] txdata; wire [31:0] txdata;
...@@ -739,6 +742,15 @@ gtx_wrapper( ...@@ -739,6 +742,15 @@ gtx_wrapper(
.TXSYNCALLIN (1'b0), .TXSYNCALLIN (1'b0),
.TXSYNCIN (1'b0)*/ .TXSYNCIN (1'b0)*/
); );
// Serial data bit shift to check host alignment
wire tx_serial_clk=gtx_wrapper.gtx_gpl.channel.tx_serial_clk;
//reg [4:0] serial_delay = 0;
reg [31:0] txp_r;
reg [31:0] txn_r;
always @(posedge tx_serial_clk) begin
txp_r = {txp_r[30:0],txp};
txn_r = {txn_r[30:0],txn};
end
// align to 4-byte boundary // align to 4-byte boundary
reg twobytes_shift; reg twobytes_shift;
...@@ -761,8 +773,12 @@ assign drpclk = gtrefclk; ...@@ -761,8 +773,12 @@ assign drpclk = gtrefclk;
assign clk = usrclk2; assign clk = usrclk2;
assign rxn = rxn_in; assign rxn = rxn_in;
assign rxp = rxp_in; assign rxp = rxp_in;
assign txn_out = txn;
assign txp_out = txp; ///assign txn_out = txn;
///assign txp_out = txp;
assign txn_out = txn_r[serial_delay];
assign txp_out = txp_r[serial_delay];
//assign ll_data_out = rxdata_out; //assign ll_data_out = rxdata_out;
//assign ll_charisk_out = rxcharisk_out; //assign ll_charisk_out = rxcharisk_out;
//assign txdata_in = ll_data_in; //assign txdata_in = ll_data_in;
......
host/gtx_wrap.v
View file @ 4626e2cd
...@@ -624,7 +624,9 @@ gtxe2_channel_wrapper #( ...@@ -624,7 +624,9 @@ gtxe2_channel_wrapper #(
.RX_XCLK_SEL ("RXREC"), .RX_XCLK_SEL ("RXREC"),
.RX_DDI_SEL (6'b000000), .RX_DDI_SEL (6'b000000),
.RX_DEFER_RESET_BUF_EN ("TRUE"), .RX_DEFER_RESET_BUF_EN ("TRUE"),
.RXCDR_CFG (72'h03000023ff10200020), /// .RXCDR_CFG (72'h03000023ff10200020),// 1.6G - 6.25G, No SS, RXOUT_DIV=2
/// .RXCDR_CFG (72'h03800023ff10200008),// Guess for SS
.RXCDR_CFG (72'h03_8800_8BFF_4020_0008),// http://www.xilinx.com/support/answers/53364.html - SATA-2, div=2
.RXCDR_FR_RESET_ON_EIDLE (1'b0), .RXCDR_FR_RESET_ON_EIDLE (1'b0),
.RXCDR_HOLD_DURING_EIDLE (1'b0), .RXCDR_HOLD_DURING_EIDLE (1'b0),
.RXCDR_PH_RESET_ON_EIDLE (1'b0), .RXCDR_PH_RESET_ON_EIDLE (1'b0),
...@@ -703,7 +705,8 @@ gtxe2_channel_wrapper #( ...@@ -703,7 +705,8 @@ gtxe2_channel_wrapper #(
.RX_DFE_H4_CFG (11'b00011110000), .RX_DFE_H4_CFG (11'b00011110000),
.RX_DFE_H5_CFG (11'b00011100000), .RX_DFE_H5_CFG (11'b00011100000),
.RX_DFE_KL_CFG (13'b0000011111110), .RX_DFE_KL_CFG (13'b0000011111110),
.RX_DFE_LPM_CFG (16'h0954), /// .RX_DFE_LPM_CFG (16'h0954),
.RX_DFE_LPM_CFG (16'h0904),
.RX_DFE_LPM_HOLD_DURING_EIDLE (1'b0), .RX_DFE_LPM_HOLD_DURING_EIDLE (1'b0),
.RX_DFE_UT_CFG (17'b10001111000000000), .RX_DFE_UT_CFG (17'b10001111000000000),
.RX_DFE_VP_CFG (17'b00011111100000011), .RX_DFE_VP_CFG (17'b00011111100000011),
......
host/link.v
View file @ 4626e2cd
...@@ -49,72 +49,46 @@ module link #( ...@@ -49,72 +49,46 @@ module link #(
// in case of strange data aligments and size (1st mentioned @ doc, p.310, odd number of words case) // in case of strange data aligments and size (1st mentioned @ doc, p.310, odd number of words case)
// Actually, only last data bundle shall be masked, others are always valid. // Actually, only last data bundle shall be masked, others are always valid.
// Mask could be encoded into 3 bits instead of 4 for qword, but encoding+decoding aren't worth the bit // Mask could be encoded into 3 bits instead of 4 for qword, but encoding+decoding aren't worth the bit
// TODO, for now not supported, all mask bits are assumed to be set
input wire [DATA_BYTE_WIDTH/2 - 1:0] data_mask_in,
// buffer read strobe
output wire data_strobe_out,
// transaction's last data budle pulse
input wire data_last_in,
// read data is valid (if 0 while last pulse wasn't received => need to hold the line)
input wire data_val_in,
input wire [DATA_BYTE_WIDTH/2 - 1:0] data_mask_in, // TODO, for now not supported, all mask bits are assumed to be set
output wire data_strobe_out, // buffer read strobe
input wire data_last_in, // transaction's last data budle pulse
input wire data_val_in, // read data is valid (if 0 while last pulse wasn't received => need to hold the line)
// data outputs to transport layer // data outputs to transport layer
// read data, same as related inputs output wire [DATA_BYTE_WIDTH*8 - 1:0] data_out, // read data, same as related inputs
output wire [DATA_BYTE_WIDTH*8 - 1:0] data_out, output wire [DATA_BYTE_WIDTH/2 - 1:0] data_mask_out, // same thing - all 1s for now. TODO
// same thing - all 1s for now. TODO output wire data_val_out, // count every data bundle read by transport layer, even if busy flag is set
output wire [DATA_BYTE_WIDTH/2 - 1:0] data_mask_out, // let the transport layer handle oveflows by itself
// count every data bundle read by transport layer, even if busy flag is set input wire data_busy_in, // transport layer tells if its inner buffer is almost full
// let the transport layer handle oveflows by himself
output wire data_val_out,
// transport layer tells if its inner buffer is almost full
input wire data_busy_in,
output wire data_last_out, output wire data_last_out,
input wire frame_req, // request for a new frame transition
// request for a new frame transition // a little bit of overkill with the cound of response signals, think of throwing out 1 of them
input wire frame_req, output wire frame_busy, // LL tells back if it cant handle the request for now
// a little bit of overkill with the cound of response signals, think of throwing out 1 of them output wire frame_ack, // LL tells if the request is transmitting
// LL tells back if it cant handle the request for now output wire frame_rej, // or if it was cancelled because of simultanious incoming transmission
output wire frame_busy, output wire frame_done_good, // Tell TL if the outcoming transaction is done and how it was done
// LL tells if the request is transmitting
output wire frame_ack,
// or if it was cancelled because of simultanious incoming transmission
output wire frame_rej,
// TL tell if the outcoming transaction is done and how it was done
output wire frame_done_good,
output wire frame_done_bad, output wire frame_done_bad,
output wire incom_start, // if started an incoming transaction
// if started an incoming transaction output wire incom_done, // if incoming transition was completed
output wire incom_start, output wire incom_invalidate, // if incoming transition had errors
// if incoming transition was completed output wire incom_sync_escape, // particular type - got sync escape
output wire incom_done, input wire incom_ack_good, // transport layer responds on a completion of a FIS
// if incoming transition had errors
output wire incom_invalidate,
// particular type - got sync escape
output wire incom_sync_escape,
// transport layer responds on a completion of a FIS
input wire incom_ack_good,
input wire incom_ack_bad, input wire incom_ack_bad,
input wire link_reset, // oob sequence is reinitiated and link now is not established or rxelecidle
// oob sequence is reinitiated and link now is not established or rxelecidle input wire sync_escape_req, // TL demands to brutally cancel current transaction
input wire link_reset, output wire sync_escape_ack, // acknowlegement of a successful reception
// TL demands to brutally cancel current transaction input wire incom_stop_req, // TL demands to stop current recieving session
input wire sync_escape_req, output link_established, // received 3 back-to-back non-align primitives.
// acknowlegement of a successful reception
output wire sync_escape_ack,
// TL demands to stop current recieving session
input wire incom_stop_req,
// inputs from phy // inputs from phy
// phy is ready - link is established input wire phy_ready, // phy is ready - link is established: Not yet - need 3 non-align primitives
input wire phy_ready, input wire [DATA_BYTE_WIDTH*8 - 1:0] phy_data_in, // data-primitives stream from phy
// data-primitives stream from phy
input wire [DATA_BYTE_WIDTH*8 - 1:0] phy_data_in,
input wire [DATA_BYTE_WIDTH - 1:0] phy_isk_in, // charisk input wire [DATA_BYTE_WIDTH - 1:0] phy_isk_in, // charisk
input wire [DATA_BYTE_WIDTH - 1:0] phy_err_in, // disperr | notintable input wire [DATA_BYTE_WIDTH - 1:0] phy_err_in, // disperr | notintable
// to phy // to phy
output wire [DATA_BYTE_WIDTH*8 - 1:0] phy_data_out, output wire [DATA_BYTE_WIDTH*8 - 1:0] phy_data_out,
output wire [DATA_BYTE_WIDTH - 1:0] phy_isk_out // charisk output wire [DATA_BYTE_WIDTH - 1:0] phy_isk_out, // charisk
// debug
output [31:0] debug_out //
); );
`ifdef SIMULATION `ifdef SIMULATION
reg [639:0] HOST_LINK_TITLE; // to show human-readable state in the GTKWave reg [639:0] HOST_LINK_TITLE; // to show human-readable state in the GTKWave
...@@ -132,8 +106,12 @@ reg [DATA_BYTE_WIDTH - 1:0] phy_err_in_r0; // disperr | notintable ...@@ -132,8 +106,12 @@ reg [DATA_BYTE_WIDTH - 1:0] phy_err_in_r0; // disperr | notintable
reg [DATA_BYTE_WIDTH*8 - 1:0] last_not_cont_di; // last primitive dword, but not CONTp reg [DATA_BYTE_WIDTH*8 - 1:0] last_not_cont_di; // last primitive dword, but not CONTp
reg rcv_junk; // receiving CONTp junk data reg rcv_junk; // receiving CONTp junk data
wire is_non_cont_p_w; // got primitive other than CONTp wire is_non_cont_non_align_p_w; // got primitive other than CONTp and ALIGNp (early by 1)
wire is_cont_p_w; // got CONTp primitive wire is_cont_p_w; // got CONTp primitive (early by 1)
wire is_align_p_w; // got ALIGNp primitive (early by 1)
//CONTp should pass ALIGNp
wire frame_done; wire frame_done;
// scrambled data // scrambled data
...@@ -144,7 +122,11 @@ wire crc_good; ...@@ -144,7 +122,11 @@ wire crc_good;
wire crc_bad; wire crc_bad;
// current crc // current crc
wire [31:0] crc_dword; wire [31:0] crc_dword;
// Removing - state_align is handled by OOB
///reg link_established_r; // received 3 back-to-back non-align primitives.
///reg [1:0] non_align_cntr;
///assign link_established = link_established_r;
assign link_established = phy_ready;
// send primitives variety count, including CRC and DATA as primitives // send primitives variety count, including CRC and DATA as primitives
localparam PRIM_NUM = 16; // 15; localparam PRIM_NUM = 16; // 15;
wire [PRIM_NUM - 1:0] rcvd_dword; // shows current processing primitive (or just data dword) wire [PRIM_NUM - 1:0] rcvd_dword; // shows current processing primitive (or just data dword)
...@@ -173,15 +155,17 @@ always @ (posedge clk) begin ...@@ -173,15 +155,17 @@ always @ (posedge clk) begin
phy_isk_in_r0 <= phy_isk_in; phy_isk_in_r0 <= phy_isk_in;
phy_err_in_r0 <= phy_err_in; phy_err_in_r0 <= phy_err_in;
if (is_non_cont_p_w) last_not_cont_di <= phy_data_in_r0; if (is_non_cont_non_align_p_w) last_not_cont_di <= phy_data_in_r0; // last_not_cont_di - primitive to repeat instead of junk
if (rst || is_non_cont_p_w) rcv_junk <= 0;
if (rst || is_non_cont_non_align_p_w) rcv_junk <= 0;
else if (is_cont_p_w) rcv_junk <= 1; else if (is_cont_p_w) rcv_junk <= 1;
if (is_cont_p_w || (rcv_junk && !is_non_cont_p_w)) begin
phy_data_in_r <= last_not_cont_di; if (is_cont_p_w || (rcv_junk && !(is_non_cont_non_align_p_w || is_align_p_w))) begin
phy_isk_in_r <= 1; phy_data_in_r <= last_not_cont_di; // last non-cont/non-align primitive will be sent instead of junk
phy_isk_in_r <= 1; // it was always primitive (4'b0001)
end else begin end else begin
phy_data_in_r <= phy_data_in_r0; phy_data_in_r <= phy_data_in_r0; // data and ALIGNp will go through
phy_isk_in_r <= phy_isk_in_r0; phy_isk_in_r <= phy_isk_in_r0; // data and ALIGNp will go through
end end
phy_err_in_r <= phy_err_in_r0; phy_err_in_r <= phy_err_in_r0;
...@@ -208,7 +192,7 @@ wire state_idle; ...@@ -208,7 +192,7 @@ wire state_idle;
reg state_sync_esc; // SyncEscape reg state_sync_esc; // SyncEscape
reg state_nocommerr; // NoComErr reg state_nocommerr; // NoComErr
reg state_nocomm; // NoComm reg state_nocomm; // NoComm
reg state_align; // SendAlign reg state_align; // SendAlign - not used, handled by OOB
reg state_reset; // RESET reg state_reset; // RESET
// tranmitter branch // tranmitter branch
reg state_send_rdy; // SendChkRdy reg state_send_rdy; // SendChkRdy
...@@ -327,19 +311,23 @@ reg alignes_pair_0; // time for 1st align primitive ...@@ -327,19 +311,23 @@ reg alignes_pair_0; // time for 1st align primitive
reg alignes_pair_1; // time for 2nd align primitive reg alignes_pair_1; // time for 2nd align primitive
always @ (posedge clk) begin always @ (posedge clk) begin
if (rst || select_prim[CODE_ALIGNP]) alignes_timer <= ALIGNES_PERIOD; /// if (!link_established_r || select_prim[CODE_ALIGNP]) alignes_timer <= ALIGNES_PERIOD;
if (!phy_ready || select_prim[CODE_ALIGNP]) alignes_timer <= ALIGNES_PERIOD;
else alignes_timer <= alignes_timer -1; else alignes_timer <= alignes_timer -1;
alignes_pair_0 <= alignes_timer == 0; alignes_pair_0 <= alignes_timer == 0;
alignes_pair_1 <= alignes_pair_0; alignes_pair_1 <= alignes_pair_0;
end end
assign alignes_pair = alignes_pair_0 | alignes_pair_1; ///assign alignes_pair = link_established_r && (alignes_pair_0 | alignes_pair_1);
assign alignes_pair = phy_ready && (alignes_pair_0 | alignes_pair_1);
// Whole transitions table, literally from doc pages 311-328 // Whole transitions table, literally from doc pages 311-328
assign set_sync_esc = sync_escape_req; assign set_sync_esc = sync_escape_req;
assign set_nocommerr = ~phy_ready & ~state_nocomm & ~state_reset; assign set_nocommerr = ~phy_ready & ~state_nocomm & ~state_reset;
assign set_nocomm = state_nocommerr; assign set_nocomm = state_nocommerr;
assign set_align = state_reset & ~link_reset; ///assign set_align = state_reset & ~link_reset;
///assign set_align = state_reset & ~link_reset & rcvd_dword[CODE_ALIGNP];
assign set_align = 0; // never, as this state is handled by OOB
assign set_reset = link_reset; assign set_reset = link_reset;
assign set_send_rdy = state_idle & frame_req; assign set_send_rdy = state_idle & frame_req;
assign set_send_sof = state_send_rdy & phy_ready & dword_val & rcvd_dword[CODE_RRDYP]; assign set_send_sof = state_send_rdy & phy_ready & dword_val & rcvd_dword[CODE_RRDYP];
...@@ -375,8 +363,11 @@ assign set_rcvr_badend = state_rcvr_data & dword_val & rcvd_dword[CODE_W ...@@ -375,8 +363,11 @@ assign set_rcvr_badend = state_rcvr_data & dword_val & rcvd_dword[CODE_W
assign clr_sync_esc = set_nocommerr | set_reset | dword_val & (rcvd_dword[CODE_RRDYP] | rcvd_dword[CODE_SYNCP]); assign clr_sync_esc = set_nocommerr | set_reset | dword_val & (rcvd_dword[CODE_RRDYP] | rcvd_dword[CODE_SYNCP]);
assign clr_nocommerr = set_reset | set_nocomm; assign clr_nocommerr = set_reset | set_nocomm;
assign clr_nocomm = set_reset | set_align; assign clr_nocomm = set_reset | set_align;
assign clr_align = set_nocommerr | set_reset | phy_ready; ///assign clr_align = set_nocommerr | set_reset | phy_ready;
///assign clr_align = set_nocommerr | set_reset | link_established_r; // Not phy_ready !!!
assign clr_align = 0; // never - this state is handled in OOB
assign clr_reset = ~link_reset; assign clr_reset = ~link_reset;
///assign clr_reset = set_align;
assign clr_send_rdy = set_nocommerr | set_reset | set_sync_esc | set_send_sof | set_rcvr_wait; assign clr_send_rdy = set_nocommerr | set_reset | set_sync_esc | set_send_sof | set_rcvr_wait;
assign clr_send_sof = set_nocommerr | set_reset | set_sync_esc | set_send_data | got_escape; assign clr_send_sof = set_nocommerr | set_reset | set_sync_esc | set_send_data | got_escape;
assign clr_send_data = set_nocommerr | set_reset | set_sync_esc | set_send_rhold | set_send_shold | set_send_crc | got_escape; assign clr_send_data = set_nocommerr | set_reset | set_sync_esc | set_send_rhold | set_send_shold | set_send_crc | got_escape;
...@@ -403,6 +394,7 @@ begin ...@@ -403,6 +394,7 @@ begin
state_sync_esc <= (state_sync_esc | set_sync_esc & ~alignes_pair) & ~clr_sync_esc & ~rst; state_sync_esc <= (state_sync_esc | set_sync_esc & ~alignes_pair) & ~clr_sync_esc & ~rst;
state_nocommerr <= (state_nocommerr | set_nocommerr & ~alignes_pair) & ~clr_nocommerr & ~rst; state_nocommerr <= (state_nocommerr | set_nocommerr & ~alignes_pair) & ~clr_nocommerr & ~rst;
state_nocomm <= (state_nocomm | set_nocomm & ~alignes_pair) & ~clr_nocomm & ~rst; state_nocomm <= (state_nocomm | set_nocomm & ~alignes_pair) & ~clr_nocomm & ~rst;
// state_align is not used, it is handled by OOB
state_align <= (state_align | set_align & ~alignes_pair) & ~clr_align & ~rst; state_align <= (state_align | set_align & ~alignes_pair) & ~clr_align & ~rst;
state_reset <= (state_reset | set_reset ) & ~clr_reset & ~rst; state_reset <= (state_reset | set_reset ) & ~clr_reset & ~rst;
state_send_rdy <= (state_send_rdy | set_send_rdy & ~alignes_pair) & ~clr_send_rdy & ~rst; state_send_rdy <= (state_send_rdy | set_send_rdy & ~alignes_pair) & ~clr_send_rdy & ~rst;
...@@ -461,7 +453,7 @@ localparam [15:0] PRIM_ERRP_HI = {3'd2, 5'd22, 3'd2, 5'd22}; ...@@ -461,7 +453,7 @@ localparam [15:0] PRIM_ERRP_HI = {3'd2, 5'd22, 3'd2, 5'd22};
localparam [15:0] PRIM_ERRP_LO = {3'd5, 5'd21, 3'd3, 5'd28}; localparam [15:0] PRIM_ERRP_LO = {3'd5, 5'd21, 3'd3, 5'd28};
//The transmission of CONTp is optional, but the ability to receive and properly process CONTp is required. //The transmission of CONTp is optional, but the ability to receive and properly process CONTp is required.
localparam [15:0] PRIM_CONTP_HI = {3'd4, 5'd25, 3'd4, 5'd25}; localparam [15:0] PRIM_CONTP_HI = {3'd4, 5'd25, 3'd4, 5'd25};
localparam [15:0] PRIM_CONTP_LO = {3'd2, 5'd10, 3'd3, 5'd28}; localparam [15:0] PRIM_CONTP_LO = {3'd5, 5'd10, 3'd3, 5'd28};
wire [DATA_BYTE_WIDTH*8 - 1:0] prim_data [PRIM_NUM - 1:0]; wire [DATA_BYTE_WIDTH*8 - 1:0] prim_data [PRIM_NUM - 1:0];
...@@ -644,6 +636,8 @@ assign incom_sync_escape = (state_rcvr_wait | state_rcvr_rdy | state_rcvr_data ...@@ -644,6 +636,8 @@ assign incom_sync_escape = (state_rcvr_wait | state_rcvr_rdy | state_rcvr_data
// shows that incoming primitive or data is ready to be processed // TODO somehow move alignes_pair into dword_val // shows that incoming primitive or data is ready to be processed // TODO somehow move alignes_pair into dword_val
assign dword_val = |rcvd_dword & phy_ready & ~rcvd_dword[CODE_ALIGNP]; assign dword_val = |rcvd_dword & phy_ready & ~rcvd_dword[CODE_ALIGNP];
// determine imcoming primitive type // determine imcoming primitive type
/*
// determine imcoming primitive type
assign rcvd_dword[CODE_DATA] = ~|phy_isk_in_r; assign rcvd_dword[CODE_DATA] = ~|phy_isk_in_r;
assign rcvd_dword[CODE_CRC] = 1'b0; assign rcvd_dword[CODE_CRC] = 1'b0;
assign rcvd_dword[CODE_SYNCP] = phy_isk_in_r[0] == 1'b1 & ~|phy_isk_in_r[DATA_BYTE_WIDTH-1:1] & prim_data[CODE_SYNCP ] == phy_data_in_r; assign rcvd_dword[CODE_SYNCP] = phy_isk_in_r[0] == 1'b1 & ~|phy_isk_in_r[DATA_BYTE_WIDTH-1:1] & prim_data[CODE_SYNCP ] == phy_data_in_r;
...@@ -659,10 +653,35 @@ assign rcvd_dword[CODE_IPP] = phy_isk_in_r[0] == 1'b1 & ~|phy_isk_in_r[DATA_BYT ...@@ -659,10 +653,35 @@ assign rcvd_dword[CODE_IPP] = phy_isk_in_r[0] == 1'b1 & ~|phy_isk_in_r[DATA_BYT
assign rcvd_dword[CODE_DMATP] = phy_isk_in_r[0] == 1'b1 & ~|phy_isk_in_r[DATA_BYTE_WIDTH-1:1] & prim_data[CODE_DMATP ] == phy_data_in_r; assign rcvd_dword[CODE_DMATP] = phy_isk_in_r[0] == 1'b1 & ~|phy_isk_in_r[DATA_BYTE_WIDTH-1:1] & prim_data[CODE_DMATP ] == phy_data_in_r;
assign rcvd_dword[CODE_OKP] = phy_isk_in_r[0] == 1'b1 & ~|phy_isk_in_r[DATA_BYTE_WIDTH-1:1] & prim_data[CODE_OKP ] == phy_data_in_r; assign rcvd_dword[CODE_OKP] = phy_isk_in_r[0] == 1'b1 & ~|phy_isk_in_r[DATA_BYTE_WIDTH-1:1] & prim_data[CODE_OKP ] == phy_data_in_r;
assign rcvd_dword[CODE_ERRP] = phy_isk_in_r[0] == 1'b1 & ~|phy_isk_in_r[DATA_BYTE_WIDTH-1:1] & prim_data[CODE_ERRP ] == phy_data_in_r; assign rcvd_dword[CODE_ERRP] = phy_isk_in_r[0] == 1'b1 & ~|phy_isk_in_r[DATA_BYTE_WIDTH-1:1] & prim_data[CODE_ERRP ] == phy_data_in_r;
// was missing
assign rcvd_dword[CODE_CONTP] = phy_isk_in_r[0] == 1'b1 & ~|phy_isk_in_r[DATA_BYTE_WIDTH-1:1] & prim_data[CODE_CONTP ] == phy_data_in_r;
*/
assign rcvd_dword[CODE_DATA] = ~|phy_isk_in_r;
assign rcvd_dword[CODE_CRC] = 1'b0;
assign rcvd_dword[CODE_SYNCP] = phy_isk_in_r[0] && !(|phy_isk_in_r[DATA_BYTE_WIDTH-1:1]) && (prim_data[CODE_SYNCP ] == phy_data_in_r);
assign rcvd_dword[CODE_ALIGNP] = phy_isk_in_r[0] && !(|phy_isk_in_r[DATA_BYTE_WIDTH-1:1]) && (prim_data[CODE_ALIGNP] == phy_data_in_r);
assign rcvd_dword[CODE_XRDYP] = phy_isk_in_r[0] && !(|phy_isk_in_r[DATA_BYTE_WIDTH-1:1]) && (prim_data[CODE_XRDYP ] == phy_data_in_r);
assign rcvd_dword[CODE_SOFP] = phy_isk_in_r[0] && !(|phy_isk_in_r[DATA_BYTE_WIDTH-1:1]) && (prim_data[CODE_SOFP ] == phy_data_in_r);
assign rcvd_dword[CODE_HOLDAP] = phy_isk_in_r[0] && !(|phy_isk_in_r[DATA_BYTE_WIDTH-1:1]) && (prim_data[CODE_HOLDAP] == phy_data_in_r);
assign rcvd_dword[CODE_HOLDP] = phy_isk_in_r[0] && !(|phy_isk_in_r[DATA_BYTE_WIDTH-1:1]) && (prim_data[CODE_HOLDP ] == phy_data_in_r);
assign rcvd_dword[CODE_EOFP] = phy_isk_in_r[0] && !(|phy_isk_in_r[DATA_BYTE_WIDTH-1:1]) && (prim_data[CODE_EOFP ] == phy_data_in_r);
assign rcvd_dword[CODE_WTRMP] = phy_isk_in_r[0] && !(|phy_isk_in_r[DATA_BYTE_WIDTH-1:1]) && (prim_data[CODE_WTRMP ] == phy_data_in_r);
assign rcvd_dword[CODE_RRDYP] = phy_isk_in_r[0] && !(|phy_isk_in_r[DATA_BYTE_WIDTH-1:1]) && (prim_data[CODE_RRDYP ] == phy_data_in_r);
assign rcvd_dword[CODE_IPP] = phy_isk_in_r[0] && !(|phy_isk_in_r[DATA_BYTE_WIDTH-1:1]) && (prim_data[CODE_IPP ] == phy_data_in_r);
assign rcvd_dword[CODE_DMATP] = phy_isk_in_r[0] && !(|phy_isk_in_r[DATA_BYTE_WIDTH-1:1]) && (prim_data[CODE_DMATP ] == phy_data_in_r);
assign rcvd_dword[CODE_OKP] = phy_isk_in_r[0] && !(|phy_isk_in_r[DATA_BYTE_WIDTH-1:1]) && (prim_data[CODE_OKP ] == phy_data_in_r);
assign rcvd_dword[CODE_ERRP] = phy_isk_in_r[0] && !(|phy_isk_in_r[DATA_BYTE_WIDTH-1:1]) && (prim_data[CODE_ERRP ] == phy_data_in_r);
// was missing
assign rcvd_dword[CODE_CONTP] = phy_isk_in_r[0] && ~(|phy_isk_in_r[DATA_BYTE_WIDTH-1:1]) && (prim_data[CODE_CONTP ] == phy_data_in_r);
// CONTp (*_r0 is one cycle ahead of *_r) // CONTp (*_r0 is one cycle ahead of *_r)
assign is_cont_p_w = phy_isk_in_r0[0] == 1'b1 & ~|phy_isk_in_r[DATA_BYTE_WIDTH-1:1] & prim_data[CODE_CONTP ] == phy_data_in_r0; //assign is_cont_p_w = phy_isk_in_r0[0] == 1'b1 & ~|phy_isk_in_r[DATA_BYTE_WIDTH-1:1] & prim_data[CODE_CONTP ] == phy_data_in_r0;
assign is_non_cont_p_w = phy_isk_in_r0[0] == 1'b1 & ~|phy_isk_in_r[DATA_BYTE_WIDTH-1:1] & prim_data[CODE_CONTP ] != phy_data_in_r0; //assign is_non_cont_non_align_p_w = phy_isk_in_r0[0] == 1'b1 & ~|phy_isk_in_r[DATA_BYTE_WIDTH-1:1] & prim_data[CODE_CONTP ] != phy_data_in_r0;
assign is_cont_p_w = phy_isk_in_r0[0] && !(|phy_isk_in_r[DATA_BYTE_WIDTH-1:1]) && (prim_data[CODE_CONTP ] == phy_data_in_r0);
assign is_align_p_w = phy_isk_in_r0[0] && !(|phy_isk_in_r[DATA_BYTE_WIDTH-1:1]) && (prim_data[CODE_ALIGNP ] == phy_data_in_r0);
assign is_non_cont_non_align_p_w = phy_isk_in_r0[0] && !(|phy_isk_in_r[DATA_BYTE_WIDTH-1:1]) && (prim_data[CODE_CONTP ] != phy_data_in_r0)
&& (prim_data[CODE_ALIGNP ] != phy_data_in_r0);
// phy level errors handling TODO // phy level errors handling TODO
...@@ -673,12 +692,188 @@ assign frame_done = frame_done_good | frame_done_bad; ...@@ -673,12 +692,188 @@ assign frame_done = frame_done_good | frame_done_bad;
assign frame_done_good = state_wait & dword_val & rcvd_dword[CODE_OKP]; assign frame_done_good = state_wait & dword_val & rcvd_dword[CODE_OKP];
assign frame_done_bad = state_wait & dword_val & rcvd_dword[CODE_ERRP]; assign frame_done_bad = state_wait & dword_val & rcvd_dword[CODE_ERRP];
// Handling 3 non-align primitives - removed, this is (should be) done by OOB
/*
always @ (posedge clk) begin
if (!phy_ready || link_reset) link_established_r <= 0;
else if (state_align && !(|non_align_cntr)) link_established_r <= 1;
if (!state_align || rcvd_dword[CODE_ALIGNP]) non_align_cntr <= 3;
else non_align_cntr <= non_align_cntr - 1;
end
*/
// =========== Debug code ===================
wire [PRIM_NUM - 1:0] rcvd_dword0; // at least oce received after reset
assign rcvd_dword0[CODE_DATA] = ~|phy_isk_in_r0;
assign rcvd_dword0[CODE_CRC] = 1'b0;
assign rcvd_dword0[CODE_SYNCP] = phy_isk_in_r0[0] && !(|phy_isk_in_r0[DATA_BYTE_WIDTH-1:1]) && (prim_data[CODE_SYNCP ] == phy_data_in_r0);
assign rcvd_dword0[CODE_ALIGNP] = phy_isk_in_r0[0] && !(|phy_isk_in_r0[DATA_BYTE_WIDTH-1:1]) && (prim_data[CODE_ALIGNP] == phy_data_in_r0);
assign rcvd_dword0[CODE_XRDYP] = phy_isk_in_r0[0] && !(|phy_isk_in_r0[DATA_BYTE_WIDTH-1:1]) && (prim_data[CODE_XRDYP ] == phy_data_in_r0);
assign rcvd_dword0[CODE_SOFP] = phy_isk_in_r0[0] && !(|phy_isk_in_r0[DATA_BYTE_WIDTH-1:1]) && (prim_data[CODE_SOFP ] == phy_data_in_r0);
assign rcvd_dword0[CODE_HOLDAP] = phy_isk_in_r0[0] && !(|phy_isk_in_r0[DATA_BYTE_WIDTH-1:1]) && (prim_data[CODE_HOLDAP] == phy_data_in_r0);
assign rcvd_dword0[CODE_HOLDP] = phy_isk_in_r0[0] && !(|phy_isk_in_r0[DATA_BYTE_WIDTH-1:1]) && (prim_data[CODE_HOLDP ] == phy_data_in_r0);
assign rcvd_dword0[CODE_EOFP] = phy_isk_in_r0[0] && !(|phy_isk_in_r0[DATA_BYTE_WIDTH-1:1]) && (prim_data[CODE_EOFP ] == phy_data_in_r0);
assign rcvd_dword0[CODE_WTRMP] = phy_isk_in_r0[0] && !(|phy_isk_in_r0[DATA_BYTE_WIDTH-1:1]) && (prim_data[CODE_WTRMP ] == phy_data_in_r0);
assign rcvd_dword0[CODE_RRDYP] = phy_isk_in_r0[0] && !(|phy_isk_in_r0[DATA_BYTE_WIDTH-1:1]) && (prim_data[CODE_RRDYP ] == phy_data_in_r0);
assign rcvd_dword0[CODE_IPP] = phy_isk_in_r0[0] && !(|phy_isk_in_r0[DATA_BYTE_WIDTH-1:1]) && (prim_data[CODE_IPP ] == phy_data_in_r0);
assign rcvd_dword0[CODE_DMATP] = phy_isk_in_r0[0] && !(|phy_isk_in_r0[DATA_BYTE_WIDTH-1:1]) && (prim_data[CODE_DMATP ] == phy_data_in_r0);
assign rcvd_dword0[CODE_OKP] = phy_isk_in_r0[0] && !(|phy_isk_in_r0[DATA_BYTE_WIDTH-1:1]) && (prim_data[CODE_OKP ] == phy_data_in_r0);
assign rcvd_dword0[CODE_ERRP] = phy_isk_in_r0[0] && !(|phy_isk_in_r0[DATA_BYTE_WIDTH-1:1]) && (prim_data[CODE_ERRP ] == phy_data_in_r0);
assign rcvd_dword0[CODE_CONTP] = phy_isk_in_r0[0] && !(|phy_isk_in_r0[DATA_BYTE_WIDTH-1:1]) && (prim_data[CODE_CONTP ] == phy_data_in_r0);
reg [PRIM_NUM - 1:0] debug_rcvd_dword; // at least oce received after reset
//reg [7:0] debug_alignp_cntr;
///reg [7:0] debug_unknown_primitives;
///reg [7:0] debug_notaligned_primitives;
///reg [7:0] debug_data_primitives;
///reg [7:0] debug_alignes;
///reg [1:0] debug_state_reset_r;
///reg debug_alignp_r;
///reg debug_syncp_r;
reg debug_first_error;
reg debug_first_alignp;
reg debug_first_syncp;
reg debug_first_nonsyncp;
reg debug_first_unknown;
reg [19:0] debug_to_first_err;
reg [15:0] debug_num_aligns;
reg [15:0] debug_num_syncs;
reg [15:0] debug_num_later_aligns;
reg other_prim_r;
reg [15:0] debug_num_other; // other primitives - not aligh, sync or cont
reg [31:0] debug_unknown_dword;
wire debug_is_sync_p_w = phy_isk_in_r0[0] && !(|phy_isk_in_r[DATA_BYTE_WIDTH-1:1]) && (prim_data[CODE_SYNCP ] == phy_data_in_r0);
wire [STATES_COUNT - 1:0] debug_states_concat = {
state_idle
, state_sync_esc
, state_nocommerr
, state_nocomm
, state_align
, state_reset
, state_send_rdy
, state_send_sof
, state_send_data
, state_send_rhold
, state_send_shold
, state_send_crc
, state_send_eof
, state_wait
, state_rcvr_wait
, state_rcvr_rdy
, state_rcvr_data
, state_rcvr_rhold
, state_rcvr_shold
, state_rcvr_eof
, state_rcvr_goodcrc
, state_rcvr_goodend
, state_rcvr_badend
};
reg [STATES_COUNT - 1:0] debug_states_visited;
always @ (posedge clk) begin
other_prim_r <= is_non_cont_non_align_p_w && !debug_is_sync_p_w;
if (rst) debug_first_alignp <= 0;
else if (is_align_p_w) debug_first_alignp <= 1;
if (rst) debug_first_syncp <= 0;
else if (debug_is_sync_p_w && debug_first_alignp) debug_first_syncp <= 1;
if (rst) debug_first_error <= 0;
else if (dec_err && debug_first_syncp) debug_first_error <= 1;
if (rst) debug_first_nonsyncp <= 0;
else if (!debug_is_sync_p_w && debug_first_syncp) debug_first_nonsyncp <= 1;
if (rst) debug_first_unknown <= 0;
else if ((rcvd_dword0 ==0) && debug_first_alignp) debug_first_unknown <= 1;
if (rst) debug_to_first_err <= 0;
else if (debug_first_alignp && !debug_first_error) debug_to_first_err <= debug_to_first_err + 1;
if (rst) debug_num_aligns <= 0;
else if (debug_first_alignp && !debug_first_syncp) debug_num_aligns <= debug_num_aligns + 1;
if (rst) debug_num_syncs <= 0;
else if (debug_first_syncp && !debug_first_nonsyncp) debug_num_syncs <= debug_num_syncs + 1;
if (rst) debug_num_later_aligns <= 0;
else if (debug_first_nonsyncp && !debug_first_error && is_align_p_w) debug_num_later_aligns <= debug_num_later_aligns + 1;
if (rst) debug_num_other <= 0;
// else if (debug_first_nonsyncp && !debug_first_error && other_prim_r) debug_num_later_aligns <= debug_num_later_aligns + 1;
else if (debug_first_nonsyncp && !debug_first_error && other_prim_r) debug_num_other <= debug_num_other + 1;
if (rst) debug_unknown_dword <= 0;
else if ((rcvd_dword0 ==0) && debug_first_alignp && !debug_first_unknown) debug_unknown_dword <= phy_data_in_r0;
if (rst) debug_rcvd_dword <= 0;
else if (debug_first_syncp && !debug_first_error) debug_rcvd_dword <= debug_rcvd_dword | rcvd_dword0;
if (rst) debug_states_visited <= 0;
else debug_states_visited <= debug_states_visited | debug_states_concat;
/*
if (rst) debug_rcvd_dword <= 0;
debug_alignp_r <= rcvd_dword[CODE_ALIGNP];
debug_syncp_r <= rcvd_dword[CODE_SYNCP];
debug_state_reset_r <= {debug_state_reset_r[0], state_reset};
if (rst) debug_rcvd_dword <= 0;
// if (rst) debug_rcvd_dword <= 0;
else if (debug_state_reset_r[0]) debug_rcvd_dword <= debug_rcvd_dword | rcvd_dword;
if (state_reset) debug_unknown_primitives <= 0;
else if ((phy_isk_in_r == 1) && !(|rcvd_dword)) debug_unknown_primitives <= debug_unknown_primitives + 1;
if (rst) debug_data_primitives <= 0;
else if ((debug_state_reset_r[0] && debug_syncp_r)) debug_data_primitives <= debug_data_primitives + 1;
if (rst) debug_alignes <= 0;
else if (debug_state_reset_r[0] && debug_alignp_r) debug_alignes <= debug_alignes + 1;
if (rst) debug_notaligned_primitives <= 0;
// else if (phy_isk_in_r[3:1] != 0) debug_notaligned_primitives <= debug_notaligned_primitives + 1;
else if (debug_state_reset_r == 1) debug_notaligned_primitives <= debug_notaligned_primitives + 1;
*/
end
///assign debug_out[19: 0] = debug_to_first_err;
//assign debug_out[23:16] = debug_num_aligns;
//assign debug_out[31:20] = debug_num_syncs[11:0];
//assign debug_out[31:20] = debug_num_later_aligns[11:0];
///assign debug_out[31:20] = debug_num_other[11:0];
///assign debug_out = debug_unknown_dword; // first unknown dword
//assign debug_out[15: 0] = debug_to_first_err[19:4];
//assign debug_out[31:16] = debug_rcvd_dword;
assign debug_out[STATES_COUNT - 1:0] = debug_states_visited;
/*
//assign debug_out[PRIM_NUM - 1:0] = debug_rcvd_dword;
assign debug_out[ 7: 0] = debug_rcvd_dword[7:0];
assign debug_out[15: 8] = debug_alignes;
assign debug_out[23:16] = debug_data_primitives;
assign debug_out[30:24] = debug_notaligned_primitives[6:0]; // now count state_reset _/~
assign debug_out[31] = debug_state_reset_r[0];
*/
`ifdef CHECKERS_ENABLED `ifdef CHECKERS_ENABLED
// incoming primitives // incoming primitives
always @ (posedge clk) always @ (posedge clk)
if (~|rcvd_dword & phy_ready) if (~|rcvd_dword & phy_ready)
begin begin
$display("%m: invalid primitive recieved : %h, conrol : %h, err : %h", phy_data_in_r, phy_isk_in_r, phy_err_in_r); $display("%m: invalid primitive received : %h, conrol : %h, err : %h", phy_data_in_r, phy_isk_in_r, phy_err_in_r);
$finish; $finish;
end end
// States checker // States checker
......
host/oob.v
View file @ 4626e2cd
...@@ -100,6 +100,8 @@ module oob #( ...@@ -100,6 +100,8 @@ module oob #(
// noone responds to our cominits // noone responds to our cominits
output wire oob_silence output wire oob_silence
,output debug_detected_alignp
`ifdef OOB_MULTISPEED `ifdef OOB_MULTISPEED
//TODO //TODO
// !!Implement it later on, ref to gen.adjustment fsm in the notebook!! // !!Implement it later on, ref to gen.adjustment fsm in the notebook!!
...@@ -119,6 +121,8 @@ module oob #( ...@@ -119,6 +121,8 @@ module oob #(
`endif //OOB_MULTISPEED `endif //OOB_MULTISPEED
); );
assign debug_detected_alignp = detected_alignp;
`ifdef SIMULATION `ifdef SIMULATION
reg [639:0] HOST_OOB_TITLE ='bz; // to show human-readable state in the GTKWave reg [639:0] HOST_OOB_TITLE ='bz; // to show human-readable state in the GTKWave
`endif `endif
...@@ -150,6 +154,9 @@ reg [DATA_BYTE_WIDTH - 1:0] rxcharisk; ...@@ -150,6 +154,9 @@ reg [DATA_BYTE_WIDTH - 1:0] rxcharisk;
// primitives detection // primitives detection
wire detected_alignp; wire detected_alignp;
localparam NUM_CON_ALIGNS = 1024;
reg detected_alignp_r; // debugging - N-th ALIGNp primitive
reg [12:0] detected_alignp_cntr; // count detected ALIGNp - do not respond yet
wire detected_syncp; wire detected_syncp;
// wait until device's cominit is done // wait until device's cominit is done
...@@ -222,7 +229,8 @@ assign set_recal_tx = state_wait_comwake & rxcomwakedet_l & rxcomwake_done; ...@@ -222,7 +229,8 @@ assign set_recal_tx = state_wait_comwake & rxcomwakedet_l & rxcomwake_done;
assign set_wait_eidle = state_recal_tx & recal_tx_done; assign set_wait_eidle = state_recal_tx & recal_tx_done;
assign set_wait_rxrst = state_wait_eidle & eidle_timer_done; assign set_wait_rxrst = state_wait_eidle & eidle_timer_done;
assign set_wait_align = state_wait_rxrst & rxreset_ack; assign set_wait_align = state_wait_rxrst & rxreset_ack;
assign set_wait_synp = state_wait_align & detected_alignp; //assign set_wait_synp = state_wait_align & detected_alignp;
assign set_wait_synp = state_wait_align & (detected_alignp_r); // N previous were both ALIGNp
assign set_wait_linkup = state_wait_synp & detected_syncp; assign set_wait_linkup = state_wait_synp & detected_syncp;
assign set_error = timer_fin & (state_wait_cominit | state_wait_comwake | state_recal_tx | state_wait_eidle | state_wait_rxrst | state_wait_align | state_wait_synp/* | state_wait_linkup*/); assign set_error = timer_fin & (state_wait_cominit | state_wait_comwake | state_recal_tx | state_wait_eidle | state_wait_rxrst | state_wait_align | state_wait_synp/* | state_wait_linkup*/);
assign clr_wait_cominit = set_wait_comwake | set_error; assign clr_wait_cominit = set_wait_comwake | set_error;
...@@ -306,19 +314,19 @@ generate ...@@ -306,19 +314,19 @@ generate
always @ (posedge clk) always @ (posedge clk)
detected_alignp_f <= rst | ~state_wait_align ? 1'b0 : detected_alignp_f <= rst | ~state_wait_align ? 1'b0 :
~|(rxdata[15:0] ^ alignp[15:0]) & ~|(rxcharisk[1:0] ^ 2'b01); // {D10.2, K28.5} ~|(rxdata[15:0] ^ alignp[15:0]) & ~|(rxcharisk[1:0] ^ 2'b01); // {D10.2, K28.5}
assign detected_alignp = detected_alignp_f & ~|(rxdata[15:0] ^ alignp[31:16]) & ~|(rxcharisk[1:0] ^ 2'b00); // {D27.3, D10.2} // SuppressThisWarning VEditor -warning would be fixed in future releases assign detected_alignp = detected_alignp_f & ~|(rxdata[15:0] ^ alignp[31:16]) & ~|(rxcharisk[1:0] ^ 2'b00); // {D27.3, D10.2} // S uppressThisWarning VEditor -warning would be fixed in future releases
reg detected_syncp_f; reg detected_syncp_f;
always @ (posedge clk) always @ (posedge clk)
detected_syncp_f <= rst | ~state_wait_synp ? 1'b0 : detected_syncp_f <= rst | ~state_wait_synp ? 1'b0 :
~|(rxdata[15:0] ^ syncp[15:0]) & ~|(rxcharisk[1:0] ^ 2'b01); // {D21.4, K28.3} ~|(rxdata[15:0] ^ syncp[15:0]) & ~|(rxcharisk[1:0] ^ 2'b01); // {D21.4, K28.3}
assign detected_syncp = detected_syncp_f & ~|(rxdata[15:0] ^ syncp[31:16]) & ~|(rxcharisk[1:0] ^ 2'b00); // {D21.5, D21.5} // SuppressThisWarning VEditor -warning would be fixed in future releases assign detected_syncp = detected_syncp_f & ~|(rxdata[15:0] ^ syncp[31:16]) & ~|(rxcharisk[1:0] ^ 2'b00); // {D21.5, D21.5} // S uppressThisWarning VEditor -warning would be fixed in future releases
end end
else else
if (DATA_BYTE_WIDTH == 4) if (DATA_BYTE_WIDTH == 4)
begin begin
assign detected_alignp = ~|(rxdata[31:0] ^ alignp[31:0]) & ~|(rxcharisk[3:0] ^ 4'h1); // {D27.3, D10.2, D10.2, K28.5} // SuppressThisWarning VEditor -warning would be fixed in future releases assign detected_alignp = ~|(rxdata[31:0] ^ alignp[31:0]) & ~|(rxcharisk[3:0] ^ 4'h1); // {D27.3, D10.2, D10.2, K28.5} // S uppressThisWarning VEditor -warning would be fixed in future releases
assign detected_syncp = ~|(rxdata[31:0] ^ syncp[31:0]) & ~|(rxcharisk[3:0] ^ 4'h1); // {D21.5, D21.5, D21.4, K28.3} // SuppressThisWarning VEditor -warning would be fixed in future releases assign detected_syncp = ~|(rxdata[31:0] ^ syncp[31:0]) & ~|(rxcharisk[3:0] ^ 4'h1); // {D21.5, D21.5, D21.4, K28.3} // S uppressThisWarning VEditor -warning would be fixed in future releases
end end
else else
if (DATA_BYTE_WIDTH == 8) if (DATA_BYTE_WIDTH == 8)
...@@ -450,6 +458,12 @@ assign eidle_timer_done = eidle_timer == 64; ...@@ -450,6 +458,12 @@ assign eidle_timer_done = eidle_timer == 64;
always @ (posedge clk) always @ (posedge clk)
eidle_timer <= rst | rxelecidle | ~state_wait_eidle ? 8'b0 : eidle_timer + CLK_TO_TIMER_CONTRIB[7:0]; eidle_timer <= rst | rxelecidle | ~state_wait_eidle ? 8'b0 : eidle_timer + CLK_TO_TIMER_CONTRIB[7:0];
always @ (posedge clk) begin
if (rst || !detected_alignp) detected_alignp_cntr <= NUM_CON_ALIGNS;
else if (|detected_alignp_cntr) detected_alignp_cntr <= detected_alignp_cntr -1;
detected_alignp_r <= detected_alignp_cntr == 0;
end
always @ (posedge clk) always @ (posedge clk)
debug <= rst ? 12'h000 : { debug <= rst ? 12'h000 : {
state_idle, state_idle,
......
host/oob_ctrl.v
View file @ 4626e2cd
...@@ -63,6 +63,7 @@ module oob_ctrl #( ...@@ -63,6 +63,7 @@ module oob_ctrl #(
output wire phy_ready, // output wire // shows if channel is ready output wire phy_ready, // output wire // shows if channel is ready
input set_offline, // input wire // electrically idle // From input set_offline, // input wire // electrically idle // From
input comreset_send // input wire // Not possible yet? // From input comreset_send // input wire // Not possible yet? // From
,output debug_detected_alignp
); );
// oob sequence needs to be issued // oob sequence needs to be issued
...@@ -160,6 +161,7 @@ oob ...@@ -160,6 +161,7 @@ oob
.oob_incompatible (oob_incompatible),// output wire // incompatible host-device speed grades (host cannot lock to alignp) .oob_incompatible (oob_incompatible),// output wire // incompatible host-device speed grades (host cannot lock to alignp)
.oob_error (oob_error), // output wire // timeout in an unexpected place .oob_error (oob_error), // output wire // timeout in an unexpected place
.oob_silence (oob_silence) // output wire // noone responds to our cominits .oob_silence (oob_silence) // output wire // noone responds to our cominits
,.debug_detected_alignp(debug_detected_alignp)
); );
......
host/sata_phy.v
View file @ 4626e2cd
...@@ -78,6 +78,8 @@ module sata_phy #( ...@@ -78,6 +78,8 @@ module sata_phy #(
output cplllock_debug, output cplllock_debug,
output usrpll_locked_debug, output usrpll_locked_debug,
output [31:0] debug_sata output [31:0] debug_sata
,output debug_detected_alignp
); );
wire [DATA_BYTE_WIDTH * 8 - 1:0] txdata; wire [DATA_BYTE_WIDTH * 8 - 1:0] txdata;
...@@ -168,7 +170,7 @@ oob_ctrl oob_ctrl( ...@@ -168,7 +170,7 @@ oob_ctrl oob_ctrl(
// To/from AHCI // To/from AHCI
.set_offline (set_offline), // input .set_offline (set_offline), // input
.comreset_send (comreset_send) // input .comreset_send (comreset_send) // input
,.debug_detected_alignp(debug_detected_alignp)
); );
wire cplllockdetclk; // TODO wire cplllockdetclk; // TODO
...@@ -491,6 +493,10 @@ reg [3:0] debug_cntr1; ...@@ -491,6 +493,10 @@ reg [3:0] debug_cntr1;
reg [3:0] debug_cntr2; reg [3:0] debug_cntr2;
reg [3:0] debug_cntr3; reg [3:0] debug_cntr3;
reg [3:0] debug_cntr4; reg [3:0] debug_cntr4;
reg [15:0] debug_cntr5;
reg [15:0] debug_cntr6;
reg [1:0] debug_rxbyteisaligned_r;
reg debug_error_r;
//txoutclk //txoutclk
always @ (posedge gtrefclk) begin always @ (posedge gtrefclk) begin
if (extrst) debug_cntr1 <= 0; if (extrst) debug_cntr1 <= 0;
...@@ -512,6 +518,17 @@ always @ (posedge txoutclk) begin ...@@ -512,6 +518,17 @@ always @ (posedge txoutclk) begin
else debug_cntr4 <= debug_cntr4 + 1; else debug_cntr4 <= debug_cntr4 + 1;
end end
always @ (posedge clk) begin
debug_rxbyteisaligned_r <= {debug_rxbyteisaligned_r[0],rxbyteisaligned};
debug_error_r <= |ll_err_out;
if (rst) debug_cntr5 <= 0;
else if (debug_rxbyteisaligned_r==1) debug_cntr5 <= debug_cntr5 + 1;
if (rst) debug_cntr6 <= 0;
else if (debug_error_r) debug_cntr6 <= debug_cntr6 + 1;
end
/*
assign debug_sata[ 3: 0] = debug_cntr1; assign debug_sata[ 3: 0] = debug_cntr1;
assign debug_sata[ 7: 4] = debug_cntr2; assign debug_sata[ 7: 4] = debug_cntr2;
assign debug_sata[11: 8] = debug_cntr3; assign debug_sata[11: 8] = debug_cntr3;
...@@ -524,5 +541,8 @@ assign debug_sata[17] = txreset; ...@@ -524,5 +541,8 @@ assign debug_sata[17] = txreset;
assign debug_sata[18] = txpcsreset; assign debug_sata[18] = txpcsreset;
assign debug_sata[19] = txelecidle; assign debug_sata[19] = txelecidle;
assign debug_sata[23:20] = debug_cntr4; assign debug_sata[23:20] = debug_cntr4;
*/
//assign phy_ready = link_state & gtx_ready & rxbyteisaligned;
assign debug_sata = {debug_cntr6,debug_cntr5};
endmodule endmodule
py393sata/x393sata.py
View file @ 4626e2cd
...@@ -136,8 +136,8 @@ class x393sata(object): ...@@ -136,8 +136,8 @@ class x393sata(object):
print ("Reset OFF") print ("Reset OFF")
self.reset(0xa) self.reset(0xa)
# self.x393_axi_tasks.init_state() # self.x393_axi_tasks.init_state()
# self.set_zynq() self.set_zynq()
self.set_debug() # self.set_debug()
print("Use 'set_zynq()', 'set_esata()' or 'set_debug() to switch SSD connection") print("Use 'set_zynq()', 'set_esata()' or 'set_debug() to switch SSD connection")
def set_zynq(self): def set_zynq(self):
...@@ -152,6 +152,29 @@ class x393sata(object): ...@@ -152,6 +152,29 @@ class x393sata(object):
self.vsc3304.connect_debug() self.vsc3304.connect_debug()
self.vsc3304.connection_status() self.vsc3304.connection_status()
def erate(self, dly = 1.0):
c0 = self.x393_mem.read_mem(0x80000ff0)
sleep(dly)
c1 = self.x393_mem.read_mem(0x80000ff0)
c00 = c0 & 0xffff
c01 = (c0 >> 16) & 0xffff
c10 = c1 & 0xffff
c11 = (c1 >> 16) & 0xffff
if c10 < c00:
c10 += 1 << 16;
if c11 < c01:
c11 += 1 << 16;
return ((c10 - c00)/dly, (c11 - c01)/dly)
def dword_to_code(self,dword):
def byte_to_code(b):
return (b & 0x1f, (b >> 5) & 7)
c = []
for i in range(4):
c.append (byte_to_code((dword >> (8*i)) & 0xff))
return "D%d.%d D%d.%d D%d.%d K%d.%d "%(c[3][0],c[3][1],c[2][0],c[2][1],c[1][0],c[1][1],c[0][0],c[0][1])
#hex(mem.read_mem(0x80000ff0))
def exp_gpio (self, def exp_gpio (self,
mode="in", mode="in",
gpio_low=54, gpio_low=54,
...@@ -224,6 +247,8 @@ class x393sata(object): ...@@ -224,6 +247,8 @@ class x393sata(object):
shutil.copy2(src, dst) shutil.copy2(src, dst)
""" """
cd /mnt/mmc/local/bin
python
from __future__ import print_function from __future__ import print_function
from __future__ import division from __future__ import division
import x393sata import x393sata
...@@ -231,10 +256,20 @@ import x393_mem ...@@ -231,10 +256,20 @@ import x393_mem
mem = x393_mem.X393Mem(1,0,1) mem = x393_mem.X393Mem(1,0,1)
sata = x393sata.x393sata() sata = x393sata.x393sata()
sata.bitstream() sata.bitstream()
sata.vsc3304.connection_status()
mem.write_mem(0x8000012c,1)
hex(mem.read_mem(0x8000012c))
mem.write_mem(0x8000012c,0)
hex(mem.read_mem(0x8000012c))
hex(mem.read_mem(0x80000130))
hex(mem.read_mem(0x80000ff0))
mem.maxi_base() mem.maxi_base()
hex(mem.read_mem(0x80000180)) hex(mem.read_mem(0x80000180))
mem.mem_dump (0x80000000, 0x200,1) mem.mem_dump (0x80000000, 0x200,1)
mem.mem_dump (0x80000000, 0x100,4) _=mem.mem_dump (0x80000000, 0x100,4)
0x80000000:00240020 80000000 00000000 00000001 00010301 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 0x80000000:00240020 80000000 00000000 00000001 00010301 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0x80000040:00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 0x80000040:00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0x80000080:00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 0x80000080:00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
...@@ -270,6 +305,57 @@ mem.mem_dump (0x80000000, 0x100,4) ...@@ -270,6 +305,57 @@ mem.mem_dump (0x80000000, 0x100,4)
0x800003c0:00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 0x800003c0:00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0x80000000:00240020 80000000 00000000 00000001 00010301 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0x80000040:00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0x80000080:00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0x800000c0:00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0x80000100:80000800 00000000 80000c00 00000000 00400055 00000000 0004c006 00000000 00000080 ffffffff 00000123 00000000 060d0000 00000000 00000000 00000000
0x80000140:00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000033 00000003 00000000 00000000
0x80000180:0001fffe 00100000 01010002 00000000 00000000 00000000 00000000 00000000 00000000 80000000 00000000 0001fffe 00000000 00000040 00000000 00000100
0x800001c0:40000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0x80000200:00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0x80000240:00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0x80000280:00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0x800002c0:00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0x80000300:00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0x80000340:00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0x80000380:00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0x800003c0:00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0x80000000:00240020 80000000 00000000 00000001 00010301 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0x80000040:00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0x80000080:00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0x800000c0:00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0x80000100:80000800 00000000 80000c00 00000000 00400040 00000000 0004c006 00000000 00000080 00000000 00000123 00000000 040d0000 00000000 00000000 00000000
0x80000140:00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000033 00000003 00000000 00000000
0x80000180:0001fffe 00100000 01010002 00000000 00000000 00000000 00000000 00000000 00000000 80000000 00000000 0001fffe 00000000 00000040 00000000 00000100
0x800001c0:40000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0x80000200:00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0x80000240:00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0x80000280:00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0x800002c0:00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0x80000300:00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0x80000340:00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0x80000380:00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0x800003c0:00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0x80000000:00240020 80000000 00000000 00000001 00010301 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0x80000040:00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0x80000080:00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0x800000c0:00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0x80000100:80000800 00000000 80000c00 00000000 08400075 00000000 0004c006 00000000 00000080 ffffffff 00000123 00000000 060d0800 00000000 00000000 00000000
0x80000140:00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000033 00000003 00000000 00000000
0x80000180:0001fffe 00100000 01010002 00000000 00000000 00000000 00000000 00000000 00000000 80000000 00000000 0001fffe 00000000 00000040 00000000 00000100
0x800001c0:40000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0x80000200:00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0x80000240:00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0x80000280:00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0x800002c0:00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0x80000300:00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0x80000340:00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0x80000380:00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0x800003c0:00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
mem.write_mem(0x8000012c,1) mem.write_mem(0x8000012c,1)
hex(mem.read_mem(0x8000012c)) hex(mem.read_mem(0x8000012c))
mem.write_mem(0x8000012c,0) mem.write_mem(0x8000012c,0)
......
tb/tb_ahci.tf
View file @ 4626e2cd
...@@ -985,6 +985,7 @@ initial begin //Host ...@@ -985,6 +985,7 @@ initial begin //Host
TESTBENCH_TITLE = "DMA transfer to device completed"; TESTBENCH_TITLE = "DMA transfer to device completed";
$display("[Testbench]: %s @%t", TESTBENCH_TITLE, $time); $display("[Testbench]: %s @%t", TESTBENCH_TITLE, $time);
repeat (50) @(posedge CLK); repeat (50) @(posedge CLK);
/*
// Reset port // Reset port
maxigp1_print ('h3ff << 2,"DEBUG_REGISTER"); maxigp1_print ('h3ff << 2,"DEBUG_REGISTER");
maxigp1_writep (HBA_PORT__PxSCTL__DET__ADDR << 2, 1); // Reset SATA maxigp1_writep (HBA_PORT__PxSCTL__DET__ADDR << 2, 1); // Reset SATA
...@@ -994,6 +995,7 @@ initial begin //Host ...@@ -994,6 +995,7 @@ initial begin //Host
maxigp1_writep (HBA_PORT__PxSCTL__DET__ADDR << 2, 0); // Reset Off maxigp1_writep (HBA_PORT__PxSCTL__DET__ADDR << 2, 0); // Reset Off
repeat (1000) @(posedge CLK); repeat (1000) @(posedge CLK);
maxigp1_print ('h3ff << 2,"DEBUG_REGISTER"); maxigp1_print ('h3ff << 2,"DEBUG_REGISTER");
*/
//DET //DET
// $finish; // $finish;
//HBA_PORT__PxIE__DHRE__MASK = 'h1; //HBA_PORT__PxIE__DHRE__MASK = 'h1;
......
tb_ahci_01.sav
View file @ 4626e2cd
[*] [*]
[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI [*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
[*] Mon Feb 1 07:23:01 2016 [*] Tue Feb 2 18:17:45 2016
[*] [*]
[dumpfile] "/home/andrey/git/x393_sata/simulation/tb_ahci-20160131230324333.fst" [dumpfile] "/home/andrey/git/x393_sata/simulation/tb_ahci-20160202111528174.fst"
[dumpfile_mtime] "Mon Feb 1 06:04:35 2016" [dumpfile_mtime] "Tue Feb 2 18:16:38 2016"
[dumpfile_size] 8481144 [dumpfile_size] 8331332
[savefile] "/home/andrey/git/x393_sata/tb_ahci_01.sav" [savefile] "/home/andrey/git/x393_sata/tb_ahci_01.sav"
[timestart] 0 [timestart] 0
[size] 1823 1180 [size] 1823 1180
[pos] 1997 0 [pos] 1997 0
*-18.601202 846582 35135962 430000 1192690 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 *-23.459948 25150000 35135962 430000 1192690 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] tb_ahci. [treeopen] tb_ahci.
[treeopen] tb_ahci.dev. [treeopen] tb_ahci.dev.
[treeopen] tb_ahci.dev.linkMonitorFIS. [treeopen] tb_ahci.dev.linkMonitorFIS.
[treeopen] tb_ahci.dev.phy. [treeopen] tb_ahci.dev.phy.
[treeopen] tb_ahci.dev.phy.gtx_wrapper.
[treeopen] tb_ahci.dev.phy.gtx_wrapper.gtx_gpl.
[treeopen] tb_ahci.dev.phy.gtx_wrapper.gtx_gpl.channel.
[treeopen] tb_ahci.dev.phy.gtx_wrapper.gtx_gpl.channel.tx.
[treeopen] tb_ahci.dev.phy.gtx_wrapper.gtx_gpl.channel.tx.ser.
[treeopen] tb_ahci.dev.phy.oob_dev.
[treeopen] tb_ahci.dut. [treeopen] tb_ahci.dut.
[treeopen] tb_ahci.dut.axi_hp_clk_i. [treeopen] tb_ahci.dut.axi_hp_clk_i.
[treeopen] tb_ahci.dut.sata_top. [treeopen] tb_ahci.dut.sata_top.
...@@ -24,7 +30,6 @@ ...@@ -24,7 +30,6 @@
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.link.scrambler. [treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.link.scrambler.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy. [treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap. [treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl. [treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.channel. [treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.channel.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.channel.rx. [treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.channel.rx.
...@@ -48,10 +53,10 @@ ...@@ -48,10 +53,10 @@
[treeopen] tb_ahci.simul_axi_hp_wr_i. [treeopen] tb_ahci.simul_axi_hp_wr_i.
[treeopen] tb_ahci.simul_axi_hp_wr_i.waddr_i. [treeopen] tb_ahci.simul_axi_hp_wr_i.waddr_i.
[treeopen] tb_ahci.simul_axi_hp_wr_i.wdata_i. [treeopen] tb_ahci.simul_axi_hp_wr_i.wdata_i.
[sst_width] 461 [sst_width] 438
[signals_width] 371 [signals_width] 411
[sst_expanded] 1 [sst_expanded] 1
[sst_vpaned_height] 644 [sst_vpaned_height] 565
@820 @820
tb_ahci.TESTBENCH_TITLE[639:0] tb_ahci.TESTBENCH_TITLE[639:0]
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.HOST_OOB_TITLE[639:0] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.HOST_OOB_TITLE[639:0]
...@@ -2415,13 +2420,182 @@ tb_ahci.simul_axi_hp_rd_i.rdata_i.out_full ...@@ -2415,13 +2420,182 @@ tb_ahci.simul_axi_hp_rd_i.rdata_i.out_full
- -
@1401200 @1401200
-ahci_dma -ahci_dma
@c00200 @800200
-link -link
@c00023
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
@28
(0)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(1)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(2)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(3)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(4)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(5)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(6)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(7)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(8)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(9)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(10)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(11)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(12)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(13)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(14)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(15)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(16)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(17)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(18)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(19)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(20)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(21)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(22)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(23)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(24)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(25)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(26)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(27)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(28)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(29)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(30)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(31)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
@1401201
-group_end
@28 @28
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.rst tb_ahci.dut.sata_top.ahci_sata_layers_i.link.rst
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_reset
@800022
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.rcvd_dword[15:0]
@28
(0)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.rcvd_dword[15:0]
(1)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.rcvd_dword[15:0]
(2)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.rcvd_dword[15:0]
(3)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.rcvd_dword[15:0]
(4)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.rcvd_dword[15:0]
(5)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.rcvd_dword[15:0]
(6)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.rcvd_dword[15:0]
(7)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.rcvd_dword[15:0]
(8)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.rcvd_dword[15:0]
(9)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.rcvd_dword[15:0]
(10)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.rcvd_dword[15:0]
(11)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.rcvd_dword[15:0]
[color] 3
(12)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.rcvd_dword[15:0]
(13)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.rcvd_dword[15:0]
(14)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.rcvd_dword[15:0]
(15)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.rcvd_dword[15:0]
@c00022
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.select_prim[15:0]
@28
(0)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.select_prim[15:0]
(1)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.select_prim[15:0]
(2)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.select_prim[15:0]
(3)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.select_prim[15:0]
(4)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.select_prim[15:0]
(5)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.select_prim[15:0]
(6)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.select_prim[15:0]
(7)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.select_prim[15:0]
(8)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.select_prim[15:0]
(9)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.select_prim[15:0]
(10)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.select_prim[15:0]
(11)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.select_prim[15:0]
[color] 2
(12)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.select_prim[15:0]
(13)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.select_prim[15:0]
(14)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.select_prim[15:0]
(15)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.select_prim[15:0]
@1401200
-group_end
@1001200
-group_end
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.link_reset
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.set_align
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.set_nocommerr
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.set_reset
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.phy_ready
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.link_established
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_align
@c00022
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.alignes_timer[8:0]
@28
(0)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.alignes_timer[8:0]
(1)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.alignes_timer[8:0]
(2)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.alignes_timer[8:0]
(3)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.alignes_timer[8:0]
(4)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.alignes_timer[8:0]
(5)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.alignes_timer[8:0]
(6)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.alignes_timer[8:0]
(7)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.alignes_timer[8:0]
(8)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.alignes_timer[8:0]
@1401200
-group_end
@800200
-oob
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.link_state
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.rxbyteisaligned
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.gtx_ready
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.set_wait_synp
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.detected_alignp
@22
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.alignp[63:0]
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.rxdata[31:0]
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.rxcharisk[3:0]
@200
---- same in link
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.clk
@22
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.phy_isk_in[3:0]
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.phy_isk_in_r[3:0]
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.phy_data_in_r[31:0]
@200 @200
- -
@800200 @800200
-states
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.rst
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.state_error
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.state_idle
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.state_recal_tx
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.state_wait_align
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.state_wait_cominit
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.state_wait_comwake
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.state_wait_eidle
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.state_wait_linkup
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.state_wait_rxrst
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.state_wait_synp
@1000200
-states
-oob
@800200
-states
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_align
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_idle
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_nocomm
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_nocommerr
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_rcvr_badend
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_rcvr_data
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_rcvr_eof
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_rcvr_goodcrc
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_rcvr_goodend
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_rcvr_rdy
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_rcvr_rhold
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_rcvr_shold
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_rcvr_wait
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_reset
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_send_crc
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_send_data
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_send_eof
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_send_rdy
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_send_rhold
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_send_shold
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_send_sof
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_sync_esc
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_wait
@1000200
-states
@800200
-crc -crc
@28 @28
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.crc.clk tb_ahci.dut.sata_top.ahci_sata_layers_i.link.crc.clk
...@@ -2493,7 +2667,7 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.link.data_strobe_out ...@@ -2493,7 +2667,7 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.link.data_strobe_out
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.data_txing tb_ahci.dut.sata_top.ahci_sata_layers_i.link.data_txing
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.data_last_in tb_ahci.dut.sata_top.ahci_sata_layers_i.link.data_last_in
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.data_last_out tb_ahci.dut.sata_top.ahci_sata_layers_i.link.data_last_out
@c00022 @800022
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.select_prim[15:0] tb_ahci.dut.sata_top.ahci_sata_layers_i.link.select_prim[15:0]
@28 @28
(0)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.select_prim[15:0] (0)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.select_prim[15:0]
...@@ -2512,7 +2686,7 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.link.select_prim[15:0] ...@@ -2512,7 +2686,7 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.link.select_prim[15:0]
(13)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.select_prim[15:0] (13)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.select_prim[15:0]
(14)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.select_prim[15:0] (14)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.select_prim[15:0]
(15)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.select_prim[15:0] (15)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.select_prim[15:0]
@1401200 @1001200
-group_end -group_end
@28 @28
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.alignes_pair_0 tb_ahci.dut.sata_top.ahci_sata_layers_i.link.alignes_pair_0
...@@ -2586,41 +2760,12 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.link.alignes_pair ...@@ -2586,41 +2760,12 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.link.alignes_pair
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.frame_req tb_ahci.dut.sata_top.ahci_sata_layers_i.link.frame_req
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.frame_ack tb_ahci.dut.sata_top.ahci_sata_layers_i.link.frame_ack
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.frame_busy tb_ahci.dut.sata_top.ahci_sata_layers_i.link.frame_busy
@800200
-states
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_align
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_idle
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_nocomm
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_nocommerr
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_rcvr_badend
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_rcvr_data
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_rcvr_eof
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_rcvr_goodcrc
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_rcvr_goodend
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_rcvr_rdy
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_rcvr_rhold
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_rcvr_shold
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_rcvr_wait
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_reset
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_send_crc
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_send_data
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_send_eof
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_send_rdy
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_send_rhold
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_send_shold
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_send_sof
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_sync_esc
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_wait
@1000200 @1000200
-states
@1401200
-link -link
@800200 @c00200
-phy -phy
@28 @28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.txoutclk tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.txoutclk
@29
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.txreset tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.txreset
@22 @22
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.txpcsreset_cnt[3:0] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.txpcsreset_cnt[3:0]
...@@ -2769,7 +2914,6 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_g ...@@ -2769,7 +2914,6 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_g
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.channel.rx.dataiface.wordcounter[31:0] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.channel.rx.dataiface.wordcounter[31:0]
@1401200 @1401200
-GTXE2_GPL -GTXE2_GPL
@1000200
-phy -phy
@c00200 @c00200
-oob_ctrl -oob_ctrl
...@@ -2785,9 +2929,18 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.gtx_ready ...@@ -2785,9 +2929,18 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.gtx_ready
-oob -oob
@1401200 @1401200
-oob_ctrl -oob_ctrl
@c00200 @800200
-gtx -gtx
@28 @28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.xclk
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.state_aligned
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.state_triggered
@22
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.rxdata_comma_in[19:0]
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.rxdata_comma_out[19:0]
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.comma
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.realign
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.cpllreset tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.cpllreset
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.cplllock tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.cplllock
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.cplllockdetclk tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.cplllockdetclk
...@@ -2808,6 +2961,7 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.txdata_enc_out[19:0] ...@@ -2808,6 +2961,7 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.txdata_enc_out[19:0]
- -
@1401200 @1401200
-gtx8x10enc -gtx8x10enc
@1000200
-gtx -gtx
@800200 @800200
-device -device
...@@ -2839,10 +2993,28 @@ tb_ahci.dev.phy.ll_data_out[31:0] ...@@ -2839,10 +2993,28 @@ tb_ahci.dev.phy.ll_data_out[31:0]
tb_ahci.dev.phy.ll_charisk_out[3:0] tb_ahci.dev.phy.ll_charisk_out[3:0]
tb_ahci.dev.phy.ll_data_in[31:0] tb_ahci.dev.phy.ll_data_in[31:0]
tb_ahci.dev.phy.ll_charisk_in[3:0] tb_ahci.dev.phy.ll_charisk_in[3:0]
tb_ahci.dev.phy.oob_dev.rxdata[31:0]
@800200
-dev_oob
@28
tb_ahci.dev.phy.oob_dev.aligndet
tb_ahci.dev.phy.oob_dev.syncdet
@200 @200
- -
@1000200 @1000200
-dev_oob
@28
tb_ahci.dev.phy.gtx_wrapper.gtx_gpl.channel.tx.TXUSRCLK2
tb_ahci.dev.phy.gtx_wrapper.gtx_gpl.channel.tx.TXUSRCLK
tb_ahci.dev.phy.gtx_wrapper.gtx_gpl.channel.tx.serial_clk
tb_ahci.dev.phy.gtx_wrapper.gtx_gpl.channel.tx.serial_data
tb_ahci.dev.phy.gtx_wrapper.gtx_gpl.channel.tx.TXP
tb_ahci.dev.phy.gtx_wrapper.gtx_gpl.channel.tx.TXN
@1000200
-dev_phy -dev_phy
@820
tb_ahci.dev.linkSendPrim.type[111:0]
@1000200
-device -device
[pattern_trace] 1 [pattern_trace] 1
[pattern_trace] 0 [pattern_trace] 0
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