fixing ifdef for debug features (44c2590f) · Commits · Elphel / x393_sata

.project

+17 −17

Original line number	Original line	Diff line number	Diff line
	@@ -52,87 +52,87 @@
	<link>		<link>
	<name>vivado_logs/VivadoBitstream.log</name>		<name>vivado_logs/VivadoBitstream.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393_sata/vivado_logs/VivadoBitstream-20160312231527798.log</location>		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoBitstream-20160313145236495.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoOpt.log</name>		<name>vivado_logs/VivadoOpt.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOpt-20160312231527798.log</location>		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOpt-20160313145236495.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoOptPhys.log</name>		<name>vivado_logs/VivadoOptPhys.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPhys-20160312231527798.log</location>		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPhys-20160313145236495.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoOptPower.log</name>		<name>vivado_logs/VivadoOptPower.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPower-20160312231527798.log</location>		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPower-20160313145236495.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoPlace.log</name>		<name>vivado_logs/VivadoPlace.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393_sata/vivado_logs/VivadoPlace-20160312231527798.log</location>		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoPlace-20160313145236495.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoRoute.log</name>		<name>vivado_logs/VivadoRoute.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393_sata/vivado_logs/VivadoRoute-20160312231527798.log</location>		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoRoute-20160313145236495.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoSynthesis.log</name>		<name>vivado_logs/VivadoSynthesis.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393_sata/vivado_logs/VivadoSynthesis-20160312231356578.log</location>		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoSynthesis-20160313145052718.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>		<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportImplemented-20160312231527798.log</location>		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportImplemented-20160313145236495.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>		<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160312231356578.log</location>		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160313145052718.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoTimingReportImplemented.log</name>		<name>vivado_logs/VivadoTimingReportImplemented.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportImplemented-20160312231527798.log</location>		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportImplemented-20160313145236495.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoTimingReportSynthesis.log</name>		<name>vivado_logs/VivadoTimingReportSynthesis.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportSynthesis-20160312231356578.log</location>		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportSynthesis-20160313145052718.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_state/x393_sata-opt-phys.dcp</name>		<name>vivado_state/x393_sata-opt-phys.dcp</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-phys-20160312231527798.dcp</location>		<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-phys-20160313145236495.dcp</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_state/x393_sata-opt-power.dcp</name>		<name>vivado_state/x393_sata-opt-power.dcp</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-power-20160312231527798.dcp</location>		<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-power-20160313145236495.dcp</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_state/x393_sata-opt.dcp</name>		<name>vivado_state/x393_sata-opt.dcp</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-20160312231527798.dcp</location>		<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-20160313145236495.dcp</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_state/x393_sata-place.dcp</name>		<name>vivado_state/x393_sata-place.dcp</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-place-20160312231527798.dcp</location>		<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-place-20160313145236495.dcp</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_state/x393_sata-route.dcp</name>		<name>vivado_state/x393_sata-route.dcp</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-route-20160312231527798.dcp</location>		<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-route-20160313145236495.dcp</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_state/x393_sata-synth.dcp</name>		<name>vivado_state/x393_sata-synth.dcp</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-synth-20160312231356578.dcp</location>		<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-synth-20160313145052718.dcp</location>
	</link>		</link>
	</linkedResources>		</linkedResources>
	</projectDescription>		</projectDescription>

ahci/ahci_sata_layers.v

+32 −100

Original line number	Original line	Diff line number	Diff line
	@@ -149,19 +149,11 @@ module ahci_sata_layers #(
	wire [ 1:0] ll_d2h_mask_out;		wire [ 1:0] ll_d2h_mask_out;
	wire ll_d2h_valid;		wire ll_d2h_valid;
	wire ll_d2h_almost_full;		wire ll_d2h_almost_full;
	// wire ll_d2h_last; // may loose ll timing and send 'last' after data. Now assuming no data comes next xyxle after last
	// wire [1:0] d2h_type_in;
	reg [1:0] d2h_type_in;		reg [1:0] d2h_type_in;
	reg fis_over_r; // push 1 more DWORD (ignore) + type (ERR/OK) when received FIS is done/error		reg fis_over_r; // push 1 more DWORD (ignore) + type (ERR/OK) when received FIS is done/error

	// wire ll_frame_req_w; // pre ll_frame_req
	reg ll_frame_req; // -> link // request for a new frame transition		reg ll_frame_req; // -> link // request for a new frame transition
	wire ll_frame_ackn; // acknowledge for ll_frame_req		wire ll_frame_ackn; // acknowledge for ll_frame_req
	// wire ll_frame_busy; // link -> // a little bit of overkill with the cound of response signals, think of throwing out 1 of them // LL tells back if it cant handle the request for now
	// wire ll_frame_ack; // link -> // LL tells if the request is transmitting not used
	// wire ll_frame_rej; // link -> // or if it was cancelled because of simultanious incoming transmission
	// wire ll_frame_done_good; // link -> // TL tell if the outcoming transaction is done and how it was done
	// wire ll_frame_done_bad; // link ->

	wire ll_incom_start; // link -> // if started an incoming transaction assuming this and next 2 are single-cycle		wire ll_incom_start; // link -> // if started an incoming transaction assuming this and next 2 are single-cycle
	wire ll_incom_done; // link -> // if incoming transition was completed		wire ll_incom_done; // link -> // if incoming transition was completed
	@@ -169,13 +161,8 @@ module ahci_sata_layers #(
	reg ll_incom_invalidate_r; // error delayed by 1 clock - if eof was incorrect (because of earlier data error)		reg ll_incom_invalidate_r; // error delayed by 1 clock - if eof was incorrect (because of earlier data error)
	// let last data dword to pass through		// let last data dword to pass through

	// wire incom_ack_good = send_R_OK; // -> link // transport layer responds on a completion of a FIS
	// wire incom_ack_bad = send_R_ERR; // -> link // oob sequence is reinitiated and link now is not established or rxelecidle

	wire ll_link_reset = ~phy_ready; // -> link // oob sequence is reinitiated and link now is not established or rxelecidle //TODO Alexey:mb it shall be independent		wire ll_link_reset = ~phy_ready; // -> link // oob sequence is reinitiated and link now is not established or rxelecidle //TODO Alexey:mb it shall be independent

	// wire ll_incom_stop_req; // -> link // TL demands to stop current recieving session (use !PxCMD.ST)?

	wire [DATA_BYTE_WIDTH*8 - 1:0] ph2ll_data_out;		wire [DATA_BYTE_WIDTH*8 - 1:0] ph2ll_data_out;
	wire [DATA_BYTE_WIDTH - 1:0] ph2ll_charisk_out; // charisk		wire [DATA_BYTE_WIDTH - 1:0] ph2ll_charisk_out; // charisk
	wire [DATA_BYTE_WIDTH - 1:0] ph2ll_err_out; // disperr \| notintable		wire [DATA_BYTE_WIDTH - 1:0] ph2ll_err_out; // disperr \| notintable
	@@ -187,14 +174,12 @@ module ahci_sata_layers #(
	wire [FIFO_ADDR_WIDTH-1:0] h2d_waddr;		wire [FIFO_ADDR_WIDTH-1:0] h2d_waddr;
	wire [FIFO_ADDR_WIDTH:0] h2d_fill;		wire [FIFO_ADDR_WIDTH:0] h2d_fill;
	wire h2d_nempty;		wire h2d_nempty;
	// wire h2d_under;

	wire [FIFO_ADDR_WIDTH-1:0] d2h_raddr;		wire [FIFO_ADDR_WIDTH-1:0] d2h_raddr;
	wire [1:0] d2h_fifo_re_regen;		wire [1:0] d2h_fifo_re_regen;
	wire [FIFO_ADDR_WIDTH-1:0] d2h_waddr;		wire [FIFO_ADDR_WIDTH-1:0] d2h_waddr;
	wire [FIFO_ADDR_WIDTH:0] d2h_fill;		wire [FIFO_ADDR_WIDTH:0] d2h_fill;
	wire d2h_nempty;		wire d2h_nempty;
	// wire d2h_over;
	wire h2d_fifo_rd = h2d_nempty && ll_strobe_out; // TODO: check latency in link.v		wire h2d_fifo_rd = h2d_nempty && ll_strobe_out; // TODO: check latency in link.v
	wire h2d_fifo_wr = h2d_valid;		wire h2d_fifo_wr = h2d_valid;

	@@ -202,27 +187,15 @@ module ahci_sata_layers #(
	wire d2h_fifo_wr = ll_d2h_valid \|\| fis_over_r; // fis_over_r will push FIS end to FIFO		wire d2h_fifo_wr = ll_d2h_valid \|\| fis_over_r; // fis_over_r will push FIS end to FIFO
	reg h2d_pending; // HBA started sending FIS to fifo		reg h2d_pending; // HBA started sending FIS to fifo

	// wire [31:0] debug_phy;
	// wire [31:0] debug_link;

	wire rxelsfull;		wire rxelsfull;
	wire rxelsempty;		wire rxelsempty;
	wire xclk; // output receive clock, just to measure frequency		wire xclk; // output receive clock, just to measure frequency
	// wire [FREQ_METER_WIDTH - 1:0] xclk_period; // relative (to 2*clk) xclk period

	wire debug_detected_alignp; // oob detects ALIGNp, but not the link layer		wire debug_detected_alignp; // oob detects ALIGNp, but not the link layer
	wire [31:0] debug_phy0;		wire [31:0] debug_phy0;
			`ifdef USE_DATASCOPE
	wire [31:0] datascope0_di;		wire [31:0] datascope0_di;
			`endif
	// assign debug_sata = {link_established, phy_ready, debug_phy[29:16],debug_link[15:0]}; //
	// assign debug_sata = debug_link[31:0]; //
	/// assign debug_sata = debug_phy;

	// assign debug_sata = {debug_link[31:4],debug_phy[3:0]} ; //
	// assign debug_sata = {debug_link[31:8],debug_phy[7:0]} ; //
	// assign debug_sata = {debug_link[27:20],debug_phy[23:0]} ; //

	assign ll_h2d_last = (h2d_type_out == H2D_TYPE_FIS_LAST);		assign ll_h2d_last = (h2d_type_out == H2D_TYPE_FIS_LAST);
	assign d2h_valid = d2h_nempty;		assign d2h_valid = d2h_nempty;
	assign d2h_many = \|d2h_fill[FIFO_ADDR_WIDTH:3]; //		assign d2h_many = \|d2h_fill[FIFO_ADDR_WIDTH:3]; //
	@@ -264,50 +237,9 @@ module ahci_sata_layers #(
	if (d2h_fifo_wr) debug_last_d2h_type_in<= d2h_type_in;		if (d2h_fifo_wr) debug_last_d2h_type_in<= d2h_type_in;
	if (d2h_fifo_rd) debug_last_d2h_type<= d2h_type;		if (d2h_fifo_rd) debug_last_d2h_type<= d2h_type;
	end		end
	/*
	assign debug_phy = {h2d_type_out[1:0],h2d_type[1:0],
	ll_h2d_last,d2h_valid, d2h_type[1:0],
	debug_last_d2h_type_in, d2h_type_in[1:0],
	debug_last_d2h_type[1:0],
	d2h_fill[1:0],
	1'b0,
	d2h_fifo_wr,
	d2h_fifo_re_regen[1:0],
	d2h_waddr[1:0],
	d2h_raddr[1:0],
	debug_phy0[ 7:0]};
	*/
	/*
	assign debug_phy = {h2d_type_out[1:0],h2d_type[1:0],
	ll_h2d_last,d2h_valid, d2h_type[1:0],
	// debug_last_d2h_type_in, d2h_type_in[1:0],
	// debug_last_d2h_type[1:0],
	// d2h_fill[1:0],
	// 1'b0,
	// d2h_fifo_wr,
	// d2h_fifo_re_regen[1:0],
	// d2h_waddr[1:0],
	// d2h_raddr[1:0],
	debug_phy0[23:0]};
	*/
	assign debug_phy = debug_phy0;		assign debug_phy = debug_phy0;

	// debug_phy0[15:0]};		`ifdef USE_DATASCOPE
	// debug_phy0[19:0]};

	/*
	// Data/type FIFO, device -> host
	output [31:0] d2h_data, // FIFO input data
	output [ 1:0] d2h_mask, // set to 2'b11
	output [ 1:0] d2h_type, // 0 - data, 1 - FIS head, 2 - R_OK, 3 - R_ERR (last two - after data, so ignore data with R_OK/R_ERR)
	output d2h_valid, // Data available from the transport layer in FIFO
	output d2h_many, // Multiple DWORDs available from the transport layer in FIFO
	input d2h_ready, // This module or DMA consumes DWORD
	*/
	// .comreset_send (comreset_send), // input
	// .cominit_got (cominit_got), // output wire
	// .comwake_got (serr_DW), // output wire

	`ifdef DATASCOPE_INCOMING_RAW		`ifdef DATASCOPE_INCOMING_RAW
	assign datascope_di = {5'b0,debug_link[5],datascope0_di[25:0]};// aligns_pair tx		assign datascope_di = {5'b0,debug_link[5],datascope0_di[25:0]};// aligns_pair tx
	`else		`else
	@@ -332,7 +264,7 @@ assign debug_phy = debug_phy0;
	);		);

	assign datascope_di = {dbg_was_link5,datascope0_di[30:0]};// aligns_pair tx		assign datascope_di = {dbg_was_link5,datascope0_di[30:0]};// aligns_pair tx
			`endif
	`endif		`endif
	link #(		link #(
	.DATA_BYTE_WIDTH(4)		.DATA_BYTE_WIDTH(4)

ahci/ahci_top.v

+4 −16

Original line number	Original line	Diff line number	Diff line
	@@ -767,14 +767,6 @@ end
	.afi_cache_set (set_axi_cache_mode), // output		.afi_cache_set (set_axi_cache_mode), // output
	.was_hba_rst (was_hba_rst), // output		.was_hba_rst (was_hba_rst), // output
	.was_port_rst (was_port_rst), // output		.was_port_rst (was_port_rst), // output
	/*
	.debug_in0 ({ debug_data_in_ready, // output
	debug_fis_end_w, // output
	xfer_cntr_zero,
	debug_fis_end_r[0], // debug_fis_end_r[1:0], // output[1:0]
	debug_get_fis_busy_r[1:0], // output[1:0]
	debug_dma[25:0]}), // input[31:0]
	*/
	.debug_in0 ({ 2'b0,		.debug_in0 ({ 2'b0,
	was_good_bad_prev,		was_good_bad_prev,
	debug_d2h_length_prev[12:0],		debug_d2h_length_prev[12:0],
	@@ -783,13 +775,6 @@ end
	debug_d2h_length[12:0]		debug_d2h_length[12:0]
	}),		}),

	/*
	reg [12:0] debug_d2h_length;
	reg [12:0] debug_d2h_length_prev;
	reg was_good_bad;
	reg was_good_bad_prev;

	*/
	// .debug_in1 ({xclk_period[7:0], // lower 8 bits of 12-bit value. Same frequency would be 0x800 (msb opposite to 3 next bits)		// .debug_in1 ({xclk_period[7:0], // lower 8 bits of 12-bit value. Same frequency would be 0x800 (msb opposite to 3 next bits)
	// debug_dma1[23:0]}), // debug_in_link), // input[31:0]		// debug_dma1[23:0]}), // debug_in_link), // input[31:0]
	.debug_in1 ({debug_in_link[15:8],		.debug_in1 ({debug_in_link[15:8],
	@@ -798,10 +783,13 @@ reg was_good_bad_prev;
	// .debug_in3 ({22'b0, last_jump_addr[9:0]}) // input[31:0]// Last jump address in the AHDCI sequencer		// .debug_in3 ({22'b0, last_jump_addr[9:0]}) // input[31:0]// Last jump address in the AHDCI sequencer
	.debug_in3 ({debug_in_link[7:0],		.debug_in3 ({debug_in_link[7:0],
	frcv_busy,frcv_ok, // 2'b0,		frcv_busy,frcv_ok, // 2'b0,
			`ifdef USE_DATASCOPE
	datascope_waddr[9:0],		datascope_waddr[9:0],
			`else
			10'b0,
			`endif
	frcv_err,frcv_ferr, // 2'b0,		frcv_err,frcv_ferr, // 2'b0,
	last_jump_addr[9:0]}) // input[31:0]// Last jump address in the AHDCI sequencer		last_jump_addr[9:0]}) // input[31:0]// Last jump address in the AHDCI sequencer

	`ifdef USE_DRP		`ifdef USE_DRP
	,.drp_en (drp_en), // output reg		,.drp_en (drp_en), // output reg
	.drp_we (drp_we), // output reg		.drp_we (drp_we), // output reg

ahci/axi_ahci_regs.v

+11 −10

Original line number	Original line	Diff line number	Diff line
	@@ -213,7 +213,7 @@ module axi_ahci_regs#(
	reg [2:0] arst_r = ~0; // previous state of arst		reg [2:0] arst_r = ~0; // previous state of arst
	reg wait_first_access = RESET_TO_FIRST_ACCESS; // keep port reset until first access		reg wait_first_access = RESET_TO_FIRST_ACCESS; // keep port reset until first access
	wire any_access = bram_wen_r \|\| bram_ren[0];		wire any_access = bram_wen_r \|\| bram_ren[0];
	reg debug_rd_r;		reg debug_rd_r = 0;
	reg [31:0] debug_r;		reg [31:0] debug_r;


	@@ -258,6 +258,7 @@ module axi_ahci_regs#(
	bram_wen_r <= bram_wen;		bram_wen_r <= bram_wen;

	if (bram_wen) bram_waddr_r <= bram_waddr[ADDRESS_BITS-1:0];		if (bram_wen) bram_waddr_r <= bram_waddr[ADDRESS_BITS-1:0];
			`ifndef NO_DEBUG_OUT
	`ifdef USE_DATASCOPE		`ifdef USE_DATASCOPE
	if (bram_ren[0]) debug_rd_r <= (&bram_raddr[ADDRESS_BITS-1:4]) &&		if (bram_ren[0]) debug_rd_r <= (&bram_raddr[ADDRESS_BITS-1:4]) &&
	// (bram_raddr[3:2] == 0) &&		// (bram_raddr[3:2] == 0) &&
	@@ -266,7 +267,7 @@ module axi_ahci_regs#(
	if (bram_ren[0]) debug_rd_r <= (&bram_raddr[ADDRESS_BITS-1:4]); // &&		if (bram_ren[0]) debug_rd_r <= (&bram_raddr[ADDRESS_BITS-1:4]); // &&
	// (bram_raddr[3:2] == 0); //		// (bram_raddr[3:2] == 0); //
	`endif		`endif
			`endif // `else `ifdef NO_DEBUG_OUT
	if (bram_ren[0]) debug_r <= bram_raddr[1]? (bram_raddr[0] ? debug_in3: debug_in2):		if (bram_ren[0]) debug_r <= bram_raddr[1]? (bram_raddr[0] ? debug_in3: debug_in2):
	(bram_raddr[0] ? debug_in1: debug_in0);		(bram_raddr[0] ? debug_in1: debug_in0);

ahci_timing.xdc

+20 −2

Original line number	Original line	Diff line number	Diff line
	@@ -6,12 +6,15 @@ create_clock -name axi_aclk0 -period 20.000 -waveform {0.000 10.000} [get_nets a
	create_clock -name gtrefclk -period 6.666 -waveform {0.000 3.333} [get_nets sata_top/ahci_sata_layers_i/phy/gtrefclk]		create_clock -name gtrefclk -period 6.666 -waveform {0.000 3.333} [get_nets sata_top/ahci_sata_layers_i/phy/gtrefclk]

	# after plls inside of GTX:		# after plls inside of GTX:
	create_clock -name txoutclk -period 6.666 -waveform {0.000 3.333} [get_nets sata_top/ahci_sata_layers_i/phy/txoutclk]		#create_clock -name txoutclk -period 6.666 -waveform {0.000 3.333} [get_nets sata_top/ahci_sata_layers_i/phy/txoutclk]
			#create_clock -name txoutclk -period 6.666 -waveform {0.000 3.333} [get_nets sata_top/ahci_sata_layers_i/phy/gtx_wrap/bufg_txoutclk/valid_reg]
			###create_clock -name txoutclk -period 6.666 -waveform {0.000 3.333} [get_nets sata_top/ahci_sata_layers_i/phy/gtx_wrap/bufg_txoutclk/txoutclk_gtx]

	# recovered sata parallel clock		# recovered sata parallel clock
	##create_clock -name xclk -period 6.666 -waveform {0.000 3.333} [get_nets sata_top/ahci_sata_layers_i/phy/gtx_wrap/xclk]		##create_clock -name xclk -period 6.666 -waveform {0.000 3.333} [get_nets sata_top/ahci_sata_layers_i/phy/gtx_wrap/xclk]
	create_clock -name xclk -period 6.666 -waveform {0.000 3.333} [get_nets sata_top/ahci_sata_layers_i/phy/gtx_wrap/xclk_gtx]		create_clock -name xclk -period 6.666 -waveform {0.000 3.333} [get_nets sata_top/ahci_sata_layers_i/phy/gtx_wrap/xclk_gtx]
	###sata_top/ahci_sata_layers_i/phy/gtx_wrap/xclk_gtx sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/xclk_gtx		###sata_top/ahci_sata_layers_i/phy/gtx_wrap/xclk_gtx sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/xclk_gtx
			create_clock -name txoutclk -period 6.666 -waveform {0.000 3.333} [get_nets sata_top/ahci_sata_layers_i/phy/gtx_wrap/txoutclk_gtx]

	# txoutclk -> userpll, which gives us 2 clocks: userclk (150MHz) and userclk2 (75MHz) . The second one is sata host clk		# txoutclk -> userpll, which gives us 2 clocks: userclk (150MHz) and userclk2 (75MHz) . The second one is sata host clk
	###create_generated_clock -name usrclk [get_nets sata_top/ahci_sata_layers_i/phy/CLK]		###create_generated_clock -name usrclk [get_nets sata_top/ahci_sata_layers_i/phy/CLK]
	@@ -21,14 +24,29 @@ create_clock -name xclk -period 6.666 -waveform {0.000 3.333} [get_nets sata_top
	###These clocks are already automatically extracted		###These clocks are already automatically extracted
	#create_generated_clock -name usrclk [get_nets sata_top/ahci_sata_layers_i/phy/usrclk]		#create_generated_clock -name usrclk [get_nets sata_top/ahci_sata_layers_i/phy/usrclk]
	#create_generated_clock -name usrclk2 [get_nets sata_top/ahci_sata_layers_i/phy/usrclk2]		#create_generated_clock -name usrclk2 [get_nets sata_top/ahci_sata_layers_i/phy/usrclk2]
			#create_clock -name usrclk2 -period 15.333 -waveform {0.000 6.666} [get_nets sata_top/ahci_sata_layers_i/phy/bufg_sclk/usrclk2_r]
			#create_clock -name usrclk2 -period 15.333 -waveform {0.000 6.666} [get_nets sata_top/ahci_sata_layers_i/phy/bufg_sclk/rclk]
			create_clock -name usrclk2 -period 13.333 -waveform {0.000 6.666} [get_nets sata_top/ahci_sata_layers_i/phy/usrclk2_r]
			#

			#create_generated_clock -name usrclk2 [get_nets sata_top/ahci_sata_layers_i/phy/usrclk2_r]
			#puts [get_nets sata_top/ahci_sata_layers_i/phy/usrclk2_r]
			#set_clock_groups -name async_clocks -asynchronous \
			#-group {gtrefclk} \
			#-group {axi_aclk0} \
			#-group {xclk} \
			#-group {usrclk} \
			#-group {usrclk2} \
			#-group {clk_axihp_pre} \
			#-group {txoutclk}

	set_clock_groups -name async_clocks -asynchronous \		set_clock_groups -name async_clocks -asynchronous \
	-group {gtrefclk} \		-group {gtrefclk} \
	-group {axi_aclk0} \		-group {axi_aclk0} \
	-group {xclk} \		-group {xclk} \
	-group {usrclk} \
	-group {usrclk2} \		-group {usrclk2} \
	-group {clk_axihp_pre} \		-group {clk_axihp_pre} \
	-group {txoutclk}		-group {txoutclk}


	###-group {sclk} \		###-group {sclk} \

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