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Commit 44c2590f authored by Andrey Filippov's avatar Andrey Filippov
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fixing ifdef for debug features

parent 7de9f2a3
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.project
View file @ 44c2590f
...@@ -52,87 +52,87 @@ ...@@ -52,87 +52,87 @@
<link> <link>
<name>vivado_logs/VivadoBitstream.log</name> <name>vivado_logs/VivadoBitstream.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoBitstream-20160312231527798.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoBitstream-20160313145236495.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOpt.log</name> <name>vivado_logs/VivadoOpt.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOpt-20160312231527798.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoOpt-20160313145236495.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOptPhys.log</name> <name>vivado_logs/VivadoOptPhys.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPhys-20160312231527798.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPhys-20160313145236495.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOptPower.log</name> <name>vivado_logs/VivadoOptPower.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPower-20160312231527798.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPower-20160313145236495.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoPlace.log</name> <name>vivado_logs/VivadoPlace.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoPlace-20160312231527798.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoPlace-20160313145236495.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoRoute.log</name> <name>vivado_logs/VivadoRoute.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoRoute-20160312231527798.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoRoute-20160313145236495.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoSynthesis.log</name> <name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoSynthesis-20160312231356578.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoSynthesis-20160313145052718.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name> <name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportImplemented-20160312231527798.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportImplemented-20160313145236495.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name> <name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160312231356578.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160313145052718.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimingReportImplemented.log</name> <name>vivado_logs/VivadoTimingReportImplemented.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportImplemented-20160312231527798.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportImplemented-20160313145236495.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimingReportSynthesis.log</name> <name>vivado_logs/VivadoTimingReportSynthesis.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportSynthesis-20160312231356578.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportSynthesis-20160313145052718.log</location>
</link> </link>
<link> <link>
<name>vivado_state/x393_sata-opt-phys.dcp</name> <name>vivado_state/x393_sata-opt-phys.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-phys-20160312231527798.dcp</location> <location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-phys-20160313145236495.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/x393_sata-opt-power.dcp</name> <name>vivado_state/x393_sata-opt-power.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-power-20160312231527798.dcp</location> <location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-power-20160313145236495.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/x393_sata-opt.dcp</name> <name>vivado_state/x393_sata-opt.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-20160312231527798.dcp</location> <location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-20160313145236495.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/x393_sata-place.dcp</name> <name>vivado_state/x393_sata-place.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-place-20160312231527798.dcp</location> <location>/home/andrey/git/x393_sata/vivado_state/x393_sata-place-20160313145236495.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/x393_sata-route.dcp</name> <name>vivado_state/x393_sata-route.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-route-20160312231527798.dcp</location> <location>/home/andrey/git/x393_sata/vivado_state/x393_sata-route-20160313145236495.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/x393_sata-synth.dcp</name> <name>vivado_state/x393_sata-synth.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-synth-20160312231356578.dcp</location> <location>/home/andrey/git/x393_sata/vivado_state/x393_sata-synth-20160313145052718.dcp</location>
</link> </link>
</linkedResources> </linkedResources>
</projectDescription> </projectDescription>
ahci/ahci_sata_layers.v
View file @ 44c2590f
This diff is collapsed.
ahci/ahci_top.v
View file @ 44c2590f
...@@ -767,14 +767,6 @@ end ...@@ -767,14 +767,6 @@ end
.afi_cache_set (set_axi_cache_mode), // output .afi_cache_set (set_axi_cache_mode), // output
.was_hba_rst (was_hba_rst), // output .was_hba_rst (was_hba_rst), // output
.was_port_rst (was_port_rst), // output .was_port_rst (was_port_rst), // output
/*
.debug_in0 ({ debug_data_in_ready, // output
debug_fis_end_w, // output
xfer_cntr_zero,
debug_fis_end_r[0], // debug_fis_end_r[1:0], // output[1:0]
debug_get_fis_busy_r[1:0], // output[1:0]
debug_dma[25:0]}), // input[31:0]
*/
.debug_in0 ({ 2'b0, .debug_in0 ({ 2'b0,
was_good_bad_prev, was_good_bad_prev,
debug_d2h_length_prev[12:0], debug_d2h_length_prev[12:0],
...@@ -783,13 +775,6 @@ end ...@@ -783,13 +775,6 @@ end
debug_d2h_length[12:0] debug_d2h_length[12:0]
}), }),
/*
reg [12:0] debug_d2h_length;
reg [12:0] debug_d2h_length_prev;
reg was_good_bad;
reg was_good_bad_prev;
*/
// .debug_in1 ({xclk_period[7:0], // lower 8 bits of 12-bit value. Same frequency would be 0x800 (msb opposite to 3 next bits) // .debug_in1 ({xclk_period[7:0], // lower 8 bits of 12-bit value. Same frequency would be 0x800 (msb opposite to 3 next bits)
// debug_dma1[23:0]}), // debug_in_link), // input[31:0] // debug_dma1[23:0]}), // debug_in_link), // input[31:0]
.debug_in1 ({debug_in_link[15:8], .debug_in1 ({debug_in_link[15:8],
...@@ -798,10 +783,13 @@ reg was_good_bad_prev; ...@@ -798,10 +783,13 @@ reg was_good_bad_prev;
// .debug_in3 ({22'b0, last_jump_addr[9:0]}) // input[31:0]// Last jump address in the AHDCI sequencer // .debug_in3 ({22'b0, last_jump_addr[9:0]}) // input[31:0]// Last jump address in the AHDCI sequencer
.debug_in3 ({debug_in_link[7:0], .debug_in3 ({debug_in_link[7:0],
frcv_busy,frcv_ok, // 2'b0, frcv_busy,frcv_ok, // 2'b0,
`ifdef USE_DATASCOPE
datascope_waddr[9:0], datascope_waddr[9:0],
`else
10'b0,
`endif
frcv_err,frcv_ferr, // 2'b0, frcv_err,frcv_ferr, // 2'b0,
last_jump_addr[9:0]}) // input[31:0]// Last jump address in the AHDCI sequencer last_jump_addr[9:0]}) // input[31:0]// Last jump address in the AHDCI sequencer
`ifdef USE_DRP `ifdef USE_DRP
,.drp_en (drp_en), // output reg ,.drp_en (drp_en), // output reg
.drp_we (drp_we), // output reg .drp_we (drp_we), // output reg
......
ahci/axi_ahci_regs.v
View file @ 44c2590f
...@@ -213,7 +213,7 @@ module axi_ahci_regs#( ...@@ -213,7 +213,7 @@ module axi_ahci_regs#(
reg [2:0] arst_r = ~0; // previous state of arst reg [2:0] arst_r = ~0; // previous state of arst
reg wait_first_access = RESET_TO_FIRST_ACCESS; // keep port reset until first access reg wait_first_access = RESET_TO_FIRST_ACCESS; // keep port reset until first access
wire any_access = bram_wen_r || bram_ren[0]; wire any_access = bram_wen_r || bram_ren[0];
reg debug_rd_r; reg debug_rd_r = 0;
reg [31:0] debug_r; reg [31:0] debug_r;
...@@ -258,15 +258,16 @@ module axi_ahci_regs#( ...@@ -258,15 +258,16 @@ module axi_ahci_regs#(
bram_wen_r <= bram_wen; bram_wen_r <= bram_wen;
if (bram_wen) bram_waddr_r <= bram_waddr[ADDRESS_BITS-1:0]; if (bram_wen) bram_waddr_r <= bram_waddr[ADDRESS_BITS-1:0];
`ifdef USE_DATASCOPE `ifndef NO_DEBUG_OUT
`ifdef USE_DATASCOPE
if (bram_ren[0]) debug_rd_r <= (&bram_raddr[ADDRESS_BITS-1:4]) && if (bram_ren[0]) debug_rd_r <= (&bram_raddr[ADDRESS_BITS-1:4]) &&
// (bram_raddr[3:2] == 0) && // (bram_raddr[3:2] == 0) &&
!bram_raddr[ADDRESS_BITS]; // !bram_raddr[ADDRESS_BITS]; //
`else `else
if (bram_ren[0]) debug_rd_r <= (&bram_raddr[ADDRESS_BITS-1:4]); // && if (bram_ren[0]) debug_rd_r <= (&bram_raddr[ADDRESS_BITS-1:4]); // &&
// (bram_raddr[3:2] == 0); // // (bram_raddr[3:2] == 0); //
`endif `endif
`endif // `else `ifdef NO_DEBUG_OUT
if (bram_ren[0]) debug_r <= bram_raddr[1]? (bram_raddr[0] ? debug_in3: debug_in2): if (bram_ren[0]) debug_r <= bram_raddr[1]? (bram_raddr[0] ? debug_in3: debug_in2):
(bram_raddr[0] ? debug_in1: debug_in0); (bram_raddr[0] ? debug_in1: debug_in0);
......
ahci_timing.xdc
View file @ 44c2590f
...@@ -6,12 +6,15 @@ create_clock -name axi_aclk0 -period 20.000 -waveform {0.000 10.000} [get_nets a ...@@ -6,12 +6,15 @@ create_clock -name axi_aclk0 -period 20.000 -waveform {0.000 10.000} [get_nets a
create_clock -name gtrefclk -period 6.666 -waveform {0.000 3.333} [get_nets sata_top/ahci_sata_layers_i/phy/gtrefclk] create_clock -name gtrefclk -period 6.666 -waveform {0.000 3.333} [get_nets sata_top/ahci_sata_layers_i/phy/gtrefclk]
# after plls inside of GTX: # after plls inside of GTX:
create_clock -name txoutclk -period 6.666 -waveform {0.000 3.333} [get_nets sata_top/ahci_sata_layers_i/phy/txoutclk] #create_clock -name txoutclk -period 6.666 -waveform {0.000 3.333} [get_nets sata_top/ahci_sata_layers_i/phy/txoutclk]
#create_clock -name txoutclk -period 6.666 -waveform {0.000 3.333} [get_nets sata_top/ahci_sata_layers_i/phy/gtx_wrap/bufg_txoutclk/valid_reg]
###create_clock -name txoutclk -period 6.666 -waveform {0.000 3.333} [get_nets sata_top/ahci_sata_layers_i/phy/gtx_wrap/bufg_txoutclk/txoutclk_gtx]
# recovered sata parallel clock # recovered sata parallel clock
##create_clock -name xclk -period 6.666 -waveform {0.000 3.333} [get_nets sata_top/ahci_sata_layers_i/phy/gtx_wrap/xclk] ##create_clock -name xclk -period 6.666 -waveform {0.000 3.333} [get_nets sata_top/ahci_sata_layers_i/phy/gtx_wrap/xclk]
create_clock -name xclk -period 6.666 -waveform {0.000 3.333} [get_nets sata_top/ahci_sata_layers_i/phy/gtx_wrap/xclk_gtx] create_clock -name xclk -period 6.666 -waveform {0.000 3.333} [get_nets sata_top/ahci_sata_layers_i/phy/gtx_wrap/xclk_gtx]
###sata_top/ahci_sata_layers_i/phy/gtx_wrap/xclk_gtx sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/xclk_gtx ###sata_top/ahci_sata_layers_i/phy/gtx_wrap/xclk_gtx sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/xclk_gtx
create_clock -name txoutclk -period 6.666 -waveform {0.000 3.333} [get_nets sata_top/ahci_sata_layers_i/phy/gtx_wrap/txoutclk_gtx]
# txoutclk -> userpll, which gives us 2 clocks: userclk (150MHz) and userclk2 (75MHz) . The second one is sata host clk # txoutclk -> userpll, which gives us 2 clocks: userclk (150MHz) and userclk2 (75MHz) . The second one is sata host clk
###create_generated_clock -name usrclk [get_nets sata_top/ahci_sata_layers_i/phy/CLK] ###create_generated_clock -name usrclk [get_nets sata_top/ahci_sata_layers_i/phy/CLK]
...@@ -21,14 +24,29 @@ create_clock -name xclk -period 6.666 -waveform {0.000 3.333} [get_nets sata_top ...@@ -21,14 +24,29 @@ create_clock -name xclk -period 6.666 -waveform {0.000 3.333} [get_nets sata_top
###These clocks are already automatically extracted ###These clocks are already automatically extracted
#create_generated_clock -name usrclk [get_nets sata_top/ahci_sata_layers_i/phy/usrclk] #create_generated_clock -name usrclk [get_nets sata_top/ahci_sata_layers_i/phy/usrclk]
#create_generated_clock -name usrclk2 [get_nets sata_top/ahci_sata_layers_i/phy/usrclk2] #create_generated_clock -name usrclk2 [get_nets sata_top/ahci_sata_layers_i/phy/usrclk2]
#create_clock -name usrclk2 -period 15.333 -waveform {0.000 6.666} [get_nets sata_top/ahci_sata_layers_i/phy/bufg_sclk/usrclk2_r]
#create_clock -name usrclk2 -period 15.333 -waveform {0.000 6.666} [get_nets sata_top/ahci_sata_layers_i/phy/bufg_sclk/rclk]
create_clock -name usrclk2 -period 13.333 -waveform {0.000 6.666} [get_nets sata_top/ahci_sata_layers_i/phy/usrclk2_r]
#
#create_generated_clock -name usrclk2 [get_nets sata_top/ahci_sata_layers_i/phy/usrclk2_r]
#puts [get_nets sata_top/ahci_sata_layers_i/phy/usrclk2_r]
#set_clock_groups -name async_clocks -asynchronous \
#-group {gtrefclk} \
#-group {axi_aclk0} \
#-group {xclk} \
#-group {usrclk} \
#-group {usrclk2} \
#-group {clk_axihp_pre} \
#-group {txoutclk}
set_clock_groups -name async_clocks -asynchronous \ set_clock_groups -name async_clocks -asynchronous \
-group {gtrefclk} \ -group {gtrefclk} \
-group {axi_aclk0} \ -group {axi_aclk0} \
-group {xclk} \ -group {xclk} \
-group {usrclk} \
-group {usrclk2} \ -group {usrclk2} \
-group {clk_axihp_pre} \ -group {clk_axihp_pre} \
-group {txoutclk} -group {txoutclk}
###-group {sclk} \ ###-group {sclk} \
host/drp_other_registers.v 0 → 100644
View file @ 44c2590f
/*******************************************************************************
* Module: drp_other_registers
* Date:2016-03-13
* Author: andrey
* Description: Additional registers controlled/read back over DRP
*
* Copyright (c) 2016 Elphel, Inc .
* drp_other_registers.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* drp_other_registers.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module drp_other_registers#(
parameter DRP_ABITS = 8,
parameter DRP_REG0 = 8,
parameter DRP_REG1 = 9,
parameter DRP_REG2 = 10,
parameter DRP_REG3 = 11
)(
input drp_rst,
input drp_clk,
input drp_en, // @aclk strobes drp_ad
input drp_we,
input [DRP_ABITS-1:0] drp_addr,
input [15:0] drp_di,
output reg drp_rdy,
output reg [15:0] drp_do,
output [15:0] drp_register0,
output [15:0] drp_register1,
output [15:0] drp_register2,
output [15:0] drp_register3
);
reg [DRP_ABITS-1:0] drp_addr_r;
reg drp_wr_r;
reg [ 1:0] drp_rd_r;
reg [15:0] drp_di_r;
reg drp_reg0_set;
reg drp_reg1_set;
reg drp_reg2_set;
reg drp_reg3_set;
reg drp_reg0_get;
reg drp_reg1_get;
reg drp_reg2_get;
reg drp_reg3_get;
reg [15:0] drp_register0_r;
reg [15:0] drp_register1_r;
reg [15:0] drp_register2_r;
reg [15:0] drp_register3_r;
assign drp_register0 = drp_register0_r;
assign drp_register1 = drp_register1_r;
assign drp_register2 = drp_register2_r;
assign drp_register3 = drp_register3_r;
// DRP interface
always @ (posedge drp_clk) begin
drp_addr_r <= drp_addr;
drp_wr_r <= drp_we && drp_en;
drp_rd_r <= {drp_rd_r[0],~drp_we & drp_en};
drp_di_r <= drp_di;
drp_reg0_set <= drp_wr_r && (drp_addr_r == DRP_REG0);
drp_reg1_set <= drp_wr_r && (drp_addr_r == DRP_REG1);
drp_reg2_set <= drp_wr_r && (drp_addr_r == DRP_REG2);
drp_reg3_set <= drp_wr_r && (drp_addr_r == DRP_REG3);
drp_reg0_get <= drp_rd_r[0] && (drp_addr_r == DRP_REG0);
drp_reg1_get <= drp_rd_r[0] && (drp_addr_r == DRP_REG1);
drp_reg2_get <= drp_rd_r[0] && (drp_addr_r == DRP_REG2);
drp_reg3_get <= drp_rd_r[0] && (drp_addr_r == DRP_REG3);
drp_rdy <= drp_wr_r || drp_rd_r[1];
drp_do <= ({16{drp_reg0_get}} & drp_register0_r) |
({16{drp_reg1_get}} & drp_register1_r) |
({16{drp_reg2_get}} & drp_register2_r) |
({16{drp_reg3_get}} & drp_register3_r);
if (drp_rst) drp_register0_r <= 0;
else if (drp_reg0_set) drp_register0_r <= drp_di_r;
if (drp_rst) drp_register1_r <= 0;
else if (drp_reg1_set) drp_register1_r <= drp_di_r;
if (drp_rst) drp_register2_r <= 0;
else if (drp_reg2_set) drp_register2_r <= drp_di_r;
if (drp_rst) drp_register3_r <= 0;
else if (drp_reg3_set) drp_register3_r <= drp_di_r;
end
endmodule
host/gtx_wrap.v
View file @ 44c2590f
This diff is collapsed.
host/link.v
View file @ 44c2590f
This diff is collapsed.
host/sata_phy.v
View file @ 44c2590f
This diff is collapsed.
host/sipo_to_xclk_measure.v deleted 100644 → 0
View file @ 7de9f2a3
/*******************************************************************************
* Module: sipo_to_xclk_measure
* Date:2016-02-09
* Author: andrey
* Description: Measuring phase of the SIPO data output relative to (global) xclk
* This module allow select all/some of the input data lines and see if the data
* sampled at negedge of the xclk differs from sampled at the previous or next
* posedge on any of the selected bits. Mismatch with previous posedge means that
* data comes while xclk == 0 (input data too late), mismatch with next posedge
* means that data changes while xclk == 1 (too early).
* Input selection for low 16 bits is written at address DRP_MASK_ADDR (0), next
* 16 bits - at DRP_MASK_ADDR + 1.
* Measurement starts by writing duration to DRP_TIMER_ADDR (8).
* Results (number of mismatches) are available as 15-bit numbers at
* DRP_EARLY_ADDR (9) and DRP_LATE_ADDR (10), MSB indicates that measurement is
* still in progress (wait it clears, small latency for 0 -> 1 should not be
* a problem).
*
* Copyright (c) 2016 Elphel, Inc .
* sipo_to_xclk_measure.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* sipo_to_xclk_measure.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module sipo_to_xclk_measure#(
parameter DATA_WIDTH = 20, // Number of data bits to measure
parameter DRP_ABITS = 8,
parameter DRP_MASK_ADDR = 0,
parameter DRP_MASK_BITS = 3,
parameter DRP_TIMER_ADDR = 8, // write timer value (how long to count early/late)
parameter DRP_EARLY_ADDR = 9, // write timer value (how long to count early/late)
parameter DRP_LATE_ADDR = 10, // write timer value (how long to count early/late)
parameter DRP_OTHERCTRL_ADDR = 11
)(
input xclk,
input drp_rst, // for other_control
input [DATA_WIDTH-1:0] sipo_di,
output [DATA_WIDTH-1:0] sipo_do, // input data registered @ posedge xclk (to be used by other modules)
input drp_clk,
input drp_en, // @aclk strobes drp_ad
input drp_we,
input [DRP_ABITS-1:0] drp_addr,
input [15:0] drp_di,
output reg drp_rdy,
output reg [15:0] drp_do,
output reg [15:0] other_control // set/reset some control bits not related to this module
);
localparam MASK_WORDS = (DATA_WIDTH + 15) >> 4;
reg [DATA_WIDTH-1:0] sipo_p; // input data registered @ posedge xclk
reg [DATA_WIDTH-1:0] sipo_n; // input data registered @ negedge xclk
reg [DATA_WIDTH-1:0] sipo_pp; // input data registered twice @ posedge xclk
reg [DATA_WIDTH-1:0] sipo_np; // input data registered @ negedge xclk, then @ posedge xclk
reg [(16 * MASK_WORDS) - 1:0] dmask; // bits to consider (or)
reg input_early_r; // SIPO data is intended to be registered @ posedge xclk
reg input_late_r;
reg [15:0] timer_cntr;
reg [14:0] early_cntr;
reg [14:0] late_cntr;
wire timer_start;
reg timer_run;
reg [DRP_ABITS-1:0] drp_addr_r;
reg drp_wr_r;
reg [ 1:0] drp_rd_r;
reg [15:0] drp_di_r;
reg drp_mask_wr;
reg drp_timer_wr;
reg drp_read_early;
reg drp_read_late;
reg drp_other_ctrl;
reg drp_read_other_ctrl;
localparam DRP_MASK_MASK = (1 << DRP_MASK_BITS) -1;
assign sipo_do = sipo_p;
always @ (negedge xclk) sipo_n <= sipo_di; // only data registered @negedge
always @ (posedge xclk) begin
sipo_p <= sipo_di;
sipo_np <= sipo_n;
sipo_pp <= sipo_p;
input_early_r <= |(dmask[DATA_WIDTH-1:0] & (sipo_np ^ sipo_pp));
input_late_r <= |(dmask[DATA_WIDTH-1:0] & (sipo_np ^ sipo_p));
if (timer_start) timer_cntr <= drp_di_r;
else if (timer_run) timer_cntr <= timer_cntr - 1;
if (timer_start) timer_run <= 1;
else if (!(|timer_cntr[15:1])) timer_run <= 0;
if (timer_start) early_cntr <= 0;
else if (timer_run && input_early_r) early_cntr <= early_cntr + 1;
if (timer_start) late_cntr <= 0;
else if (timer_run && input_late_r) late_cntr <= late_cntr + 1;
end
// DRP interface
always @ (posedge drp_clk) begin
drp_addr_r <= drp_addr;
drp_wr_r <= drp_we && drp_en;
drp_rd_r <= {drp_rd_r[0],~drp_we & drp_en};
drp_di_r <= drp_di;
drp_mask_wr <= drp_wr_r && ((drp_addr_r & ~DRP_MASK_MASK) == DRP_MASK_ADDR);
drp_timer_wr <= drp_wr_r && (drp_addr_r == DRP_TIMER_ADDR);
drp_read_early <= drp_rd_r[0] && (drp_addr_r == DRP_EARLY_ADDR);
drp_read_late <= drp_rd_r[0] && (drp_addr_r == DRP_LATE_ADDR);
drp_other_ctrl <= drp_wr_r && (drp_addr_r == DRP_OTHERCTRL_ADDR);
drp_read_other_ctrl <= drp_rd_r[0] && (drp_addr_r == DRP_OTHERCTRL_ADDR);
drp_rdy <= drp_wr_r || drp_rd_r[1];
drp_do <= ({16{drp_read_early}} & {timer_run,early_cntr}) |
({16{drp_read_late}} & {timer_run,late_cntr}) |
({16{drp_read_other_ctrl}} & {other_control}) ;
if (drp_rst) other_control <= 0;
else if (drp_other_ctrl) other_control <= drp_di_r;
end
// 0..7 - data mask
genvar i1;
generate
for (i1 = 0; i1 < MASK_WORDS; i1 = i1 + 1) begin: gen_drp_mask
always @ (posedge drp_clk)
if (drp_mask_wr && ((drp_addr_r & DRP_MASK_MASK) ==i1)) dmask[16*i1 +: 16] <= drp_di_r;
end
endgenerate
pulse_cross_clock #(
.EXTRA_DLY(0)
) timer_set_i (
.rst (drp_mask_wr), // input
.src_clk (drp_clk), // input
.dst_clk (xclk), // input
.in_pulse (drp_timer_wr), // input
.out_pulse (timer_start), // output
.busy() // output
);
endmodule
py393sata/x393sata.py
View file @ 44c2590f
...@@ -320,6 +320,7 @@ class x393sata(object): ...@@ -320,6 +320,7 @@ class x393sata(object):
''' '''
def bitstream(self, def bitstream(self,
bitfile=None, bitfile=None,
ss_off=True,
quiet=1): quiet=1):
""" """
Turn FPGA clock OFF, reset ON, load bitfile, turn clock ON and reset OFF Turn FPGA clock OFF, reset ON, load bitfile, turn clock ON and reset OFF
...@@ -335,11 +336,14 @@ class x393sata(object): ...@@ -335,11 +336,14 @@ class x393sata(object):
print("vcc_sens01 vp33sens01 vcc_sens23 vp33sens23", file = f) print("vcc_sens01 vp33sens01 vcc_sens23 vp33sens23", file = f)
""" """
#Spread Spectrum off on channel 3 #Spread Spectrum off on channel 3
if ss_off:
if quiet < 2: if quiet < 2:
print ("Spread Spectrum off on channel 3") print ("Spread Spectrum off on channel 3")
with open (SI5338_PATH+"/spread_spectrum/ss3_values","w") as f: with open (SI5338_PATH+"/spread_spectrum/ss3_values","w") as f:
print ("0",file=f) print ("0",file=f)
else:
if quiet < 2:
print ("Keeping Spread Spectrum on on channel 3")
if quiet < 2: if quiet < 2:
print ("FPGA clock OFF") print ("FPGA clock OFF")
self.x393_mem.write_mem(FPGA0_THR_CTRL,1) self.x393_mem.write_mem(FPGA0_THR_CTRL,1)
...@@ -1545,7 +1549,7 @@ sata = x393sata.x393sata() # 1,0,"10389B") ...@@ -1545,7 +1549,7 @@ sata = x393sata.x393sata() # 1,0,"10389B")
sata.reinit_mux() sata.reinit_mux()
sata.bitstream() sata.bitstream(None, False) # False - keep SS on
#sata.drp_write (0x20b,0x401) # bypass, clock align #sata.drp_write (0x20b,0x401) # bypass, clock align
sata.drp (0x20b,0x221) # bypass, clock align sata.drp (0x20b,0x221) # bypass, clock align
......
system_defines.vh
View file @ 44c2590f
...@@ -8,7 +8,7 @@ ...@@ -8,7 +8,7 @@
// `define DATASCOPE_INCOMING_RAW // `define DATASCOPE_INCOMING_RAW
`define PRELOAD_BRAMS `define PRELOAD_BRAMS
// `define AHCI_SATA 1 // `define AHCI_SATA 1
`define DEBUG_ELASTIC // `define DEBUG_ELASTIC
// Enviroment-dependent options // Enviroment-dependent options
`ifdef IVERILOG `ifdef IVERILOG
`define SIMULATION `define SIMULATION
......
x393_sata.bit
View file @ 44c2590f
No preview for this file type
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