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x393_sata
Commit 4190b627 authored by Andrey Filippov's avatar Andrey Filippov
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more debugging

parent 10efc04b
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ahci/ahci_fis_receive.v
View file @ 4190b627
......@@ -325,7 +325,8 @@ localparam DATA_TYPE_ERR = 3;
if (store_sig[1]) sig_r[31:8] <= hba_data_in[23:0];
if (store_sig[3]) sig_r[ 7:0] <= hba_data_in[ 7:0];
if (reg_d2h) tf_err_sts <= hba_data_in[31:16]; // 15:0];
if (hba_rst) tf_err_sts <= 0;
else if (reg_d2h) tf_err_sts <= hba_data_in[31:16]; // 15:0];
// Sets pPioErr[pPmpCur] to Error field of the FIS
// Updates PxTFD.STS.ERR with pPioErr[pPmpCur] ??
else if (reg_ps[0]) tf_err_sts <= {hba_data_in[31:24],hba_data_in[23:16]};
......
ahci/axi_ahci_regs.v
View file @ 4190b627
......@@ -187,13 +187,13 @@ module axi_ahci_regs#(
reg [2:0] arst_r = ~0; // previous state of arst
reg wait_first_access = RESET_TO_FIRST_ACCESS; // keep port reset until first access
wire any_access = bram_wen_r || bram_ren[0];
reg bram_ren0_r;
wire [1:0] bram_ren_w = {bram_ren0_r, bram_ren[0] & ~write_busy_w}; // axibram_read does not mask bram_ren and bram_regen with dev_ready !
// reg bram_ren0_r;
// wire [1:0] bram_ren_w = {bram_ren0_r, bram_ren[0] & ~write_busy_w}; // FIXED: axibram_read does not mask bram_ren and bram_regen with dev_ready !
// assign bram_addr = bram_ren[0] ? bram_raddr : (bram_wen ? bram_waddr : pre_awaddr);
// assign bram_addr = bram_ren[0] ? bram_raddr : (bram_wen_r ? bram_waddr_r : bram_waddr);
assign bram_addr = bram_ren_w[0] ? bram_raddr : (bram_wen_r ? bram_waddr_r : bram_waddr);
assign bram_addr = bram_ren[0] ? bram_raddr : (bram_wen_r ? bram_waddr_r : bram_waddr);
// assign bram_addr = bram_ren_w[0] ? bram_raddr : (bram_wen_r ? bram_waddr_r : bram_waddr);
assign hba_arst = hba_rst_r; // hba _reset (currently does ~ the same as port reset)
assign port_arst = port_rst_r; // port _reset by software
......@@ -203,7 +203,7 @@ module axi_ahci_regs#(
always @(posedge aclk) begin
bram_ren0_r <= bram_ren_w[0];
/// bram_ren0_r <= bram_ren_w[0];
if (arst) write_busy_r <= 0;
else if (write_start_burst) write_busy_r <= 1;
......@@ -211,7 +211,8 @@ module axi_ahci_regs#(
if (bram_wen) bram_wdata_r <= bram_wdata;
if (bram_ren_w[1]) bram_rdata_r <= bram_rdata;
/// if (bram_ren_w[1]) bram_rdata_r <= bram_rdata;
if (bram_ren[1]) bram_rdata_r <= bram_rdata;
bram_wstb_r <= {4{bram_wen}} & bram_wstb;
......@@ -403,8 +404,8 @@ sata_phy_rst_out will be released after the sata clock is stable
.clk_a (aclk), // input
.addr_a (bram_addr), // input[9:0]
/// .en_a (bram_ren[0] || write_busy_w), // input
/// .en_a (bram_ren[0] || bram_wen || bram_wen_r), // input
.en_a (bram_ren_w[0] || bram_wen || bram_wen_r), // input
.en_a (bram_ren[0] || bram_wen || bram_wen_r), // input
/// .en_a (bram_ren_w[0] || bram_wen || bram_wen_r), // input
.regen_a (1'b0), // input
// .we_a (write_busy_r && !nowrite), // input
.we_a (bram_wstb_r), //bram_wen_d), // input[3:0]
......
device/sata_device.v
View file @ 4190b627
......@@ -43,7 +43,7 @@ module sata_device(
);
`include "includes/fis_types.vh"
//`ifdef SIMULATION
reg [639:0] DEV_TITLE; // to show human-readable state in the GTKWave
reg [639:0] DEV_TITLE = 'bz; // to show human-readable state in the GTKWave
// reg [31:0] DEV_DATA;
integer DEV_DATA;
//`endif
......
generated/action_decoder.v
View file @ 4190b627
/*******************************************************************************
* Module: action_decoder
* Date:2016-01-22
* Date:2016-01-24
* Author: auto-generated file, see ahci_fsm_sequence.py
* Description: Decode sequencer code to 1-hot actions
*******************************************************************************/
......
generated/condition_mux.v
View file @ 4190b627
/*******************************************************************************
* Module: condition_mux
* Date:2016-01-22
* Date:2016-01-24
* Author: auto-generated file, see ahci_fsm_sequence.py
* Description: Select condition
*******************************************************************************/
......
helpers/ahci_fsm_sequence.py
View file @ 4190b627
......@@ -142,6 +142,10 @@ sequence = [{LBL:'POR', ADDR: 0x0, ACT: NOP},
{LBL:'P:RegFisAccept', ACT: 'R_OK'}, # send R_OK
{ ACT: 'UPDATE_SIG'}, # update_sig
{ ACT: 'UPDATE_ERR_STS'}, # update_err_sts
{IF: 'FIS_I', GOTO:'P:RegFisSetIS'}, # ** Not it docs - setting DHRS interrupt if "i" bit was set in D2HR FIS
{ GOTO:'P:NotRunning'},
# Not in documentation - do we need to issue DWRS interrupt if "i" bit is set? Adding such state
{LBL:'P:RegFisSetIS', ACT: 'SIRQ_DHR'}, # sirq_DHR
{ GOTO:'P:NotRunning'},
# {IF: 'PCMD_FRE', GOTO:'P:RegFisPostToMem'}, # pxcmd_fre hardware always copies signature FIS to 'memory' if expected
......
helpers/create_ahci_registers.py
View file @ 4190b627
......@@ -266,12 +266,12 @@ src=[{gN:"PCI_Header", gS: PCIHEAD, gE:PCIHEAD+0x3f, gD:" PCI header emulation w
{ fS:25, fT:RO, fC:0, fD:"Reserved"},
{fN:"OFE", fS:24, fT:RW, fC:0, fD:"Overflow Enable"},
{fN:"IPME", fS:23, fT:RW, fC:0, fD:"Incorrect Port Multiplier Enable"},
{fN:"PRCE", fS:22, fT:RO, fC:0, fD:"PhyRdy changed Enable"}, #Indirect clear
{fN:"PRCE", fS:22, fT:RW, fC:0, fD:"PhyRdy changed Enable"}, #Indirect clear
{ fS: 8, fE:21, fT:RO, fC:0, fD:"Reserved"},
{fN:"DMPE", fS: 7, fT:RO, fC:0, fD:"Device Mechanical Presence Interrupt Enable"}, #Indirect clear
{fN:"PCE", fS: 6, fT:RO, fC:0, fD:"Port Connect Change Interrupt Enable"}, #Indirect clear
{fN:"PCE", fS: 6, fT:RW, fC:0, fD:"Port Connect Change Interrupt Enable"}, #Indirect clear
{fN:"DPE", fS: 5, fT:RW, fC:0, fD:"Descriptor Processed Interrupt Enable"},
{fN:"UFE", fS: 4, fT:RO, fC:0, fD:"Unknown FIS"}, #Indirect clear
{fN:"UFE", fS: 4, fT:RW, fC:0, fD:"Unknown FIS"}, #Indirect clear
{fN:"SDBE", fS: 3, fT:RW, fC:0, fD:"Device Bits Interrupt Enable"},
{fN:"DSE", fS: 2, fT:RW, fC:0, fD:"DMA Setup FIS Interrupt Enable"},
{fN:"PSE", fS: 1, fT:RW, fC:0, fD:"PIO Setup FIS Interrupt Enable"},
......
host/oob.v
View file @ 4190b627
......@@ -120,7 +120,7 @@ module oob #(
);
`ifdef SIMULATION
reg [639:0] HOST_OOB_TITLE; // to show human-readable state in the GTKWave
reg [639:0] HOST_OOB_TITLE ='bz; // to show human-readable state in the GTKWave
`endif
......
includes/ahci_localparams.vh
View file @ 4190b627
......@@ -466,7 +466,7 @@
localparam HBA_PORT__PxIE__IPME__ADDR = 'h45;
localparam HBA_PORT__PxIE__IPME__MASK = 'h800000;
localparam HBA_PORT__PxIE__IPME__DFLT = 'h0;
// RO: PhyRdy changed Enable
// RW: PhyRdy changed Enable
localparam HBA_PORT__PxIE__PRCE__ADDR = 'h45;
localparam HBA_PORT__PxIE__PRCE__MASK = 'h400000;
localparam HBA_PORT__PxIE__PRCE__DFLT = 'h0;
......@@ -474,7 +474,7 @@
localparam HBA_PORT__PxIE__DMPE__ADDR = 'h45;
localparam HBA_PORT__PxIE__DMPE__MASK = 'h80;
localparam HBA_PORT__PxIE__DMPE__DFLT = 'h0;
// RO: Port Connect Change Interrupt Enable
// RW: Port Connect Change Interrupt Enable
localparam HBA_PORT__PxIE__PCE__ADDR = 'h45;
localparam HBA_PORT__PxIE__PCE__MASK = 'h40;
localparam HBA_PORT__PxIE__PCE__DFLT = 'h0;
......@@ -482,7 +482,7 @@
localparam HBA_PORT__PxIE__DPE__ADDR = 'h45;
localparam HBA_PORT__PxIE__DPE__MASK = 'h20;
localparam HBA_PORT__PxIE__DPE__DFLT = 'h0;
// RO: Unknown FIS
// RW: Unknown FIS
localparam HBA_PORT__PxIE__UFE__ADDR = 'h45;
localparam HBA_PORT__PxIE__UFE__MASK = 'h10;
localparam HBA_PORT__PxIE__UFE__DFLT = 'h0;
......
includes/ahci_types.vh
View file @ 4190b627
, .INIT_00 (256'h0000000000000000AAAAAAAAAAAAAAAA00000000000000070000000000000000)
, .INIT_10 (256'h0000000000000000555555555555000000000000000000005555555555500000)
, .INIT_11 (256'h000000000000000055054004000001C15551400000000455AAA28000000008AA)
, .INIT_11 (256'h000000000000000055054004000001C15551500000001555AAA28000000008AA)
, .INIT_12 (256'h0000000000550000000000000000000000000000000000000000000000000000)
, .INIT_13 (256'h00000000AAAAAAAAFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF002AAAAA00AA000A)
, .INIT_14 (256'h000000000000000000000000000000000001555555555550000000000055000D)
......
includes/ahxi_fsm_code.vh
View file @ 4190b627
, .INIT_00 (256'h00100000000E0000000C00000030000000200000000A0000000A0000000A0000)
, .INIT_01 (256'h0019444F1C369443542D44170000001900480019040802020204008400220006)
, .INIT_02 (256'h0019010200500019000C04020090002924F824FF014000190003004204040000)
, .INIT_03 (256'h021000368C68844F84BB44344C652C3F14190012003600480018000A01080022)
, .INIT_04 (256'h00000036000000190090003600900019144301020408020202040036B07A7077)
, .INIT_05 (256'h98A458D4387F64510C2504550000004B24F824FF0420004924F824FF04200059)
, .INIT_06 (256'h30ED008800FFA46E50F590360060010400680202003000DFA89068ED18E618C8)
, .INIT_07 (256'h01400099D0F80410003600000036B07A0000004D004400220036B07A70773074)
, .INIT_08 (256'h004D0402008E0005008EC88C00220024008E288828FB000C0090008324F824FF)
, .INIT_09 (256'h00220024003648A2289E28FB00140036487C0CAA28FB0090009424F824FF00C0)
, .INIT_0A (256'h50F500A000AE88360899020800AA009000A824F824FF0420004D0081004D48A2)
, .INIT_0B (256'h24F824F8012000BD020800368899020800090036889950B70024002800B2D0F8)
, .INIT_0C (256'h001100D1C8CF009000CC24F824FF02200036889950B700240028009000C2C4FF)
, .INIT_0D (256'h0440004D0101004DC8DD28FB000C009000D824F824FF0240003634CF000000D1)
, .INIT_0E (256'h24F824FF042000F30082009000EA24F824FF042000360401009000E324F824FF)
, .INIT_0F (256'h000000FD000000FD020100FD0021011000FD0021004400F3000000F3009000F1)
, .INIT_10 (256'h0000000000000000000000000000000000000000000000000000000000360041)
, .INITP_00 (256'hC3208802605C240900789C9C8888A000C250620020809C802018880022222222)
, .INITP_01 (256'h088820889C827209C828270882271A009C86068072E227218168AA2722081A09)
, .INITP_02 (256'h0000000000000000000000000000000000000000000000000000000000000002)
, .INIT_00 (256'h00100000000E0000000C00000033000000200000000A0000000A0000000A0000)
, .INIT_01 (256'h001944521C399446543044170000001900480019040802020204008400220006)
, .INIT_02 (256'h001900050019C82E000C04020090002924FB2502014000190003004204040000)
, .INIT_03 (256'h845284BE44374C682C4214190012003900480018000A01080022001901020050)
, .INIT_04 (256'h00190090003900900019144601020408020202040039B07D707A021000398C6B)
, .INIT_05 (256'h64540C2504580000004E24FB25020420004C24FB25020420005C000000390000)
, .INIT_06 (256'hA47150F8903900600104006B0202003000E2A89368F018E918CB98A758D73882)
, .INIT_07 (256'h0410003900000039B07D00000050004400220039B07D707A307730F000880102)
, .INIT_08 (256'h00050091C88F002200240091288B28FE000C0090008624FB25020140009CD0FB)
, .INIT_09 (256'h48A528A128FE00140039487F0CAD28FE0090009724FB250200C0005004020091)
, .INIT_0A (256'h8839089C020800AD009000AB24FB2502042000500081005048A5002200240039)
, .INIT_0B (256'h00C002080039889C020800090039889C50BA0024002800B5D0FB50F800A000B1)
, .INIT_0C (256'h009000CF24FB250202200039889C50BA00240028009000C5C50224FB24FB0120)
, .INIT_0D (256'h0050C8E028FE000C009000DB24FB25020240003934D2000000D4001100D4C8D2)
, .INIT_0E (256'h00F60082009000ED24FB2502042000390401009000E624FB2502044000500101)
, .INIT_0F (256'h0100020101000021011001000021004400F6000000F6009000F424FB25020420)
, .INIT_10 (256'h0000000000000000000000000000000000000000000000390041000001000000)
, .INITP_00 (256'hC8220098170902401E272722222800309418800820809C802018880022222222)
, .INITP_01 (256'h22082227209C82720A09C22089C680272181A01CB889C8605A2A89C882068270)
, .INITP_02 (256'h0000000000000000000000000000000000000000000000000000000000000082)
tb/tb_ahci.tf
View file @ 4190b627
......@@ -63,11 +63,11 @@ module tb_ahci #(
`endif // CVC
`endif // IVERILOG
reg [639:0] TESTBENCH_TITLE = "RESET"; // to show human-readable state in the GTKWave
reg [639:0] TESTBENCH_TITLE = 'bz; // to show human-readable state in the GTKWave
reg [31:0] TESTBENCH_DATA;
reg [11:0] TESTBENCH_ID;
reg [639:0] DEVICE_TITLE = "RESET"; // to show human-readable state in the GTKWave
reg [639:0] DEVICE_TITLE = 'bz; // to show human-readable state in the GTKWave
reg [31:0] DEVICE_DATA;
reg [11:0] Device_ID;
......@@ -151,6 +151,7 @@ integer NUM_WORDS_EXPECTED;
// integer SCANLINE_CUR_Y;
wire AXI_RD_EMPTY=NUM_WORDS_READ==NUM_WORDS_EXPECTED; //SuppressThisWarning VEditor : may be unused, just for simulation
assign SIMUL_AXI_EMPTY= ~rvalid && rready && (rid==LAST_ARID); //SuppressThisWarning VEditor : may be unused, just for simulation // use it to wait for?
wire IRQ = dut.ps7_i.IRQF2P[0];
wire [11:0] #(AXI_TASK_HOLD) ARID_IN = ARID_IN_r;
wire [31:0] #(AXI_TASK_HOLD) ARADDR_IN = ARADDR_IN_r;
......@@ -652,6 +653,11 @@ localparam MAXIGP1 = 32'h80000000; // Start of the MAXIGP1 address range (use ah
end
endtask
//localparam CLB_OFFS32 = 'h200; // # In the second half of the register space (0x800..0xbff - 1KB)
localparam HBA_OFFS32 = 0;
localparam HBA_PORT0_OFFS32 = 'h40;
localparam PXSIG_OFFS32 = HBA_OFFS32 + HBA_PORT0_OFFS32 + 'h9;
localparam PXTFD_OFFS32 = HBA_OFFS32 + HBA_PORT0_OFFS32 + 'h8;
initial begin //Host
wait (!RST);
......@@ -663,6 +669,14 @@ initial begin //Host
end
axi_set_rd_lag(0);
axi_set_b_lag(0);
maxigp1_writep (PXSIG_OFFS32 << 2, 'h12345678); //
maxigp1_writep (PXTFD_OFFS32 << 2, 'h87654321); //
maxigp1_print (PXSIG_OFFS32 << 2);
maxigp1_print (PXTFD_OFFS32 << 2);
maxigp1_print (PCI_Header__CAP__CAP__ADDR << 2);
maxigp1_print (GHC__PI__PI__ADDR << 2);
......@@ -670,12 +684,25 @@ initial begin //Host
maxigp1_print (GHC__GHC__IE__ADDR << 2);
maxigp1_writep (GHC__GHC__IE__ADDR << 2, GHC__GHC__IE__MASK); // enable interrupts (global)
maxigp1_print (HBA_PORT__PxIE__CPDE__ADDR << 2);
maxigp1_writep (HBA_PORT__PxIE__CPDE__ADDR << 2, ~0); // allow all interrupts
// maxigp1_writep (HBA_PORT__PxIE__CPDE__ADDR << 2, ~0); // allow all interrupts
maxigp1_writep (HBA_PORT__PxIE__CPDE__ADDR << 2, HBA_PORT__PxIE__DHRE__MASK); // =='h1: allow DHRS only interrupts (D2HR received (signature)
maxigp1_print (GHC__GHC__IE__ADDR << 2);
maxigp1_print (HBA_PORT__PxIE__CPDE__ADDR << 2);
maxigp1_print (PXSIG_OFFS32 << 2);
maxigp1_print (PXTFD_OFFS32 << 2);
TESTBENCH_TITLE = "Waiting D2H IRQ";
$display("[Testbench]: %s @%t", TESTBENCH_TITLE, $time);
wait (IRQ);
TESTBENCH_TITLE = "Got D2H IRQ";
$display("[Testbench]: %s @%t", TESTBENCH_TITLE, $time);
maxigp1_print (PXSIG_OFFS32 << 2);
maxigp1_print (PXTFD_OFFS32 << 2);
// $finish;
//HBA_PORT__PxIE__DHRE__MASK = 'h1;
end
integer status;
......
tb_ahci_01.sav
View file @ 4190b627
This diff is collapsed.
wrapper/GTXE2_GPL.v
View file @ 4190b627
......@@ -1019,8 +1019,8 @@ reg oob_in_process;
always @ (posedge TXUSRCLK)
oob_in_process <= reset | TXCOMFINISH ? 1'b0 : TXCOMINIT | TXCOMWAKE ? 1'b1 : oob_in_process;
assign TXP = ~line_idle ? serial_data : 1'bx;
assign TXN = ~line_idle ? ~serial_data : 1'bx;
assign TXP = ~line_idle ? serial_data : 1'bz;
assign TXN = ~line_idle ? ~serial_data : 1'bz;
assign line_idle_pcs = (TXELECIDLE | oob_in_process) & ~oob_active | reset;
......
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