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x393_sata
Commit 340db2c6 authored by Alexey Grebenkin's avatar Alexey Grebenkin
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VDT-only support added. For non-VDT applications, see non-vdt branch

parent 680098f2
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.gitmodules
View file @ 340db2c6
[submodule "x393"]
path = x393
url = https://github.com/Elphel/x393.git
[submodule "gtxe2_gpl"]
path = gtxe2_gpl
url = https://github.com/Elphel/gtxe2_gpl
.project 0 → 100644
View file @ 340db2c6
<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>x393_sata</name>
<comment></comment>
<projects>
</projects>
<buildSpec>
<buildCommand>
<name>com.elphel.vdt.veditor.simulateBuilder</name>
<arguments>
<dictionary>
<key>com.elphel.vdt.veditor.simulateBuilder.00000000Default.CleanCommand</key>
<value>echo &apos;Clean&apos;</value>
</dictionary>
<dictionary>
<key>com.elphel.vdt.veditor.simulateBuilder.00000000Default.buildOrder</key>
<value>0</value>
</dictionary>
<dictionary>
<key>com.elphel.vdt.veditor.simulateBuilder.00000000Default.command</key>
<value>echo &apos;No Build Configuration Specified&apos;</value>
</dictionary>
<dictionary>
<key>com.elphel.vdt.veditor.simulateBuilder.00000000Default.enable</key>
<value>true</value>
</dictionary>
<dictionary>
<key>com.elphel.vdt.veditor.simulateBuilder.00000000Default.name</key>
<value>Default</value>
</dictionary>
<dictionary>
<key>com.elphel.vdt.veditor.simulateBuilder.00000000Default.parser</key>
<value></value>
</dictionary>
<dictionary>
<key>com.elphel.vdt.veditor.simulateBuilder.00000000Default.workFolder</key>
<value></value>
</dictionary>
</arguments>
</buildCommand>
</buildSpec>
<natures>
<nature>com.elphel.vdt.veditor.HdlNature</nature>
</natures>
</projectDescription>
.settings/com.elphel.vdt.FPGA_project.prefs 0 → 100644
View file @ 340db2c6
FPGA_project_0_SimulationTopFile=tb/tb_top.v
FPGA_project_1_SimulationTopModule=tb
FPGA_project_2_ImplementationTopFile=dma/top.v
FPGA_project_4_part=xc7z030fbg484-1
com.elphel.store.context.FPGA_project=FPGA_project_2_ImplementationTopFile<-@\#\#@->FPGA_project_4_part<-@\#\#@->FPGA_project_0_SimulationTopFile<-@\#\#@->FPGA_project_1_SimulationTopModule<-@\#\#@->
eclipse.preferences.version=1
.settings/com.elphel.vdt.ISExst.prefs 0 → 100644
View file @ 340db2c6
ISExst_170_constraints=ddrc_test01.xcf
ISExst_96_OtherProblems=HDLCompiler\:413<-@\#\#@->
com.elphel.store.context.ISExst=ISExst_170_constraints<-@\#\#@->ISExst_96_OtherProblems<-@\#\#@->
eclipse.preferences.version=1
.settings/com.elphel.vdt.VivadoBitstream.prefs 0 → 100644
View file @ 340db2c6
VivadoBitstream_103_PreBitstreamTCL=set_property BITSTREAM.STARTUP.MATCH_CYCLE NoWait [current_design]<-@\#\#@->
VivadoBitstream_105_force=true
com.elphel.store.context.VivadoBitstream=VivadoBitstream_105_force<-@\#\#@->VivadoBitstream_103_PreBitstreamTCL<-@\#\#@->
eclipse.preferences.version=1
.settings/com.elphel.vdt.VivadoPlace.prefs 0 → 100644
View file @ 340db2c6
VivadoPlace_111_verbose_place=true
com.elphel.store.context.VivadoPlace=VivadoPlace_111_verbose_place<-@\#\#@->
eclipse.preferences.version=1
.settings/com.elphel.vdt.VivadoSynthesis.prefs 0 → 100644
View file @ 340db2c6
VivadoSynthesis_101_MaxMsg=10000
VivadoSynthesis_102_ConstraintsFiles=x393.xdc<-@\#\#@->x393_timing.xdc<-@\#\#@->
VivadoSynthesis_115_flatten_hierarchy=none
VivadoSynthesis_127_verbose=true
VivadoSynthesis_81_parser_mode=1
VivadoSynthesis_93_OtherProblems=Netlist 29-345<-@\#\#@->Board 49-26<-@\#\#@->
VivadoSynthesis_95_ShowInfo=false
com.elphel.store.context.VivadoSynthesis=VivadoSynthesis_102_ConstraintsFiles<-@\#\#@->VivadoSynthesis_95_ShowInfo<-@\#\#@->VivadoSynthesis_115_flatten_hierarchy<-@\#\#@->VivadoSynthesis_101_MaxMsg<-@\#\#@->VivadoSynthesis_127_verbose<-@\#\#@->VivadoSynthesis_93_OtherProblems<-@\#\#@->VivadoSynthesis_81_parser_mode<-@\#\#@->
eclipse.preferences.version=1
.settings/com.elphel.vdt.VivadoTimimgSummaryReportSynthesis.prefs 0 → 100644
View file @ 340db2c6
VivadoTimimgSummaryReportSynthesis_102_DisableVivadoTimingSummary=true
com.elphel.store.context.VivadoTimimgSummaryReportSynthesis=VivadoTimimgSummaryReportSynthesis_102_DisableVivadoTimingSummary<-@\#\#@->
eclipse.preferences.version=1
.settings/com.elphel.vdt.VivadoTimingReportImplemented.prefs 0 → 100644
View file @ 340db2c6
com.elphel.store.context.VivadoTimingReportImplemented=VivadoTimingReportImplemented_132_rawfile<-@\#\#@->
eclipse.preferences.version=1
.settings/com.elphel.vdt.VivadoTimingReportSynthesis.prefs 0 → 100644
View file @ 340db2c6
VivadoTimingReportSynthesis_102_DisableVivadoTiming=true
com.elphel.store.context.VivadoTimingReportSynthesis=VivadoTimingReportSynthesis_102_DisableVivadoTiming<-@\#\#@->
eclipse.preferences.version=1
.settings/com.elphel.vdt.iverilog.prefs 0 → 100644
View file @ 340db2c6
com.elphel.store.context.iverilog=iverilog_81_TopModulesOther<-@\#\#@->iverilog_83_ExtraFiles<-@\#\#@->iverilog_88_ShowNoProblem<-@\#\#@->iverilog_77_Param_Exe<-@\#\#@->iverilog_78_VVP_Exe<-@\#\#@->iverilog_99_GrepFindErrWarn<-@\#\#@->iverilog_89_ShowNoProblem<-@\#\#@->iverilog_79_GtkWave_Exe<-@\#\#@->iverilog_103_ExtraFiles<-@\#\#@->iverilog_104_IncludeDir<-@\#\#@->iverilog_101_TopModulesOther<-@\#\#@->iverilog_122_IVerilogOther<-@\#\#@->
eclipse.preferences.version=1
iverilog_101_TopModulesOther=glbl<-@\#\#@->
iverilog_103_ExtraFiles=x393/glbl.v<-@\#\#@->
iverilog_104_IncludeDir=${verilog_project_loc}/x393<-@\#\#@->${verilog_project_loc}/x393/includes<-@\#\#@->${verilog_project_loc}/host<-@\#\#@->${verilog_project_loc}/tb<-@\#\#@->
iverilog_122_IVerilogOther=-D OPEN_SOURCE_ONLY
iverilog_77_Param_Exe=/usr/local/bin/iverilog
iverilog_78_VVP_Exe=/usr/local/bin/vvp
iverilog_79_GtkWave_Exe=/usr/local/bin/gtkwave
iverilog_81_TopModulesOther=glbl<-@\#\#@->
iverilog_83_ExtraFiles=glbl.v<-@\#\#@->
iverilog_88_ShowNoProblem=true
iverilog_89_ShowNoProblem=true
iverilog_99_GrepFindErrWarn=error|warning|sorry
.settings/com.elphel.vdt.prefs 0 → 100644
View file @ 340db2c6
com.elphel.store.context.=com.elphel.vdt.PROJECT_DESING_MENU<-@\#\#@->
com.elphel.vdt.PROJECT_DESING_MENU=MainDesignMenu
eclipse.preferences.version=1
device/dev_phy.v deleted 100644 → 0
View file @ 680098f2
This diff is collapsed.
device/device_tasks.v deleted 100644 → 0
View file @ 680098f2
wire [31:0] phy2dev_data;
wire [3:0] phy2dev_charisk;
wire [3:0] phy2dev_err;
wire dev_clk;
wire dev_rst;
reg [31:0] dev2phy_data;
reg [3:0] dev2phy_charisk;
force dev.dev2phy_data =
force dev.dev2phy_charisk =
task
device/oob_ctrl_dev.v deleted 100644 → 0
View file @ 680098f2
/*******************************************************************************
* Module: oob_ctrl
* Date: 2015-07-11
* Author: Alexey
* Description: module to start oob sequences and to handle errors
*
* Copyright (c) 2015 Elphel, Inc.
* oob_ctrl.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* oob_ctrl.v file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`include "oob.v"
module oob_ctrl_dev #(
parameter DATA_BYTE_WIDTH = 4,
parameter CLK_SPEED_GRADE = 2 // 1 - 75 Mhz, 2 - 150Mhz, 4 - 300Mhz
)
(
// sata clk = usrclk2
input wire clk,
// reset oob
input wire rst,
// gtx is ready = all resets are done
input wire gtx_ready,
// oob responces
input wire rxcominitdet_in,
input wire rxcomwakedet_in,
input wire rxelecidle_in,
// oob issues
output wire txcominit,
output wire txcomwake,
output wire txelecidle,
// input data stream (if any data during OOB setting => ignored)
input wire [DATA_BYTE_WIDTH*8 - 1:0] txdata_in,
input wire [DATA_BYTE_WIDTH - 1:0] txcharisk_in,
// output data stream to gtx
output wire [DATA_BYTE_WIDTH*8 - 1:0] txdata_out,
output wire [DATA_BYTE_WIDTH - 1:0] txcharisk_out,
// input data from gtx
input wire [DATA_BYTE_WIDTH*8 - 1:0] rxdata_in,
input wire [DATA_BYTE_WIDTH - 1:0] rxcharisk_in,
// bypassed data from gtx
output wire [DATA_BYTE_WIDTH*8 - 1:0] rxdata_out,
output wire [DATA_BYTE_WIDTH - 1:0] rxcharisk_out,
// obvious
input wire rxbyteisaligned,
// shows if channel is ready
output wire phy_ready
);
// oob sequence needs to be issued
wire oob_start;
// connection established, all further data is valid
wire oob_done;
// doc p265, link is established after 3back-to-back non-ALIGNp
wire link_up;
wire link_down;
// the device itself sends cominit
wire cominit_req;
// allow to respond to cominit
wire cominit_allow;
// status information to handle by a control block if any exists
// incompatible host-device speed grades (host cannot lock to alignp)
wire oob_incompatible; // TODO
// timeout in an unexpected place
wire oob_error;
// noone responds to our cominits
wire oob_silence;
// obvious
wire oob_busy;
// for the resync sake
reg rxbyteisaligned_r;
reg rxbyteisaligned_rr;
always @ (posedge clk)
begin
rxbyteisaligned_rr <= rxbyteisaligned_r;
rxbyteisaligned_r <= rxbyteisaligned;
end
// 1 - link is up and running, 0 - probably not
reg link_state;
// 1 - connection is being established OR already established, 0 - is not
reg oob_state;
assign phy_ready = link_state & gtx_ready & rxbyteisaligned_rr;
always @ (posedge clk)
link_state <= (link_state | link_up) & ~link_down & ~rst;
always @ (posedge clk)
oob_state <= (oob_state | oob_start | cominit_req & cominit_allow) & ~oob_error & ~oob_silence & link_down & ~rst;
// decide when to issue oob: always when gtx is ready
assign oob_start = gtx_ready & ~oob_state & ~oob_busy;
// set line to idle state before if we're waiting for a device to answer AND while oob sequence
wire txelecidle_inner;
assign txelecidle = ~oob_state | txelecidle_inner;
// let devices always begin oob sequence, if only it's not a glitch
assign cominit_allow = cominit_req & link_state;
oob_dev #(
.DATA_BYTE_WIDTH (DATA_BYTE_WIDTH),
.CLK_SPEED_GRADE (CLK_SPEED_GRADE)
)
oob_dev
(
// sata clk = usrclk2
.clk (clk),
// reset oob
.rst (rst),
// oob responces
.rxcominitdet_in (rxcominitdet_in),
.rxcomwakedet_in (rxcomwakedet_in),
.rxelecidle_in (rxelecidle_in),
// oob issues
.txcominit (txcominit),
.txcomwake (txcomwake),
.txelecidle (txelecidle_inner),
// input data stream (if any data during OOB setting => ignored)
.txdata_in (txdata_in),
.txcharisk_in (txcharisk_in),
// output data stream to gtx
.txdata_out (txdata_out),
.txcharisk_out (txcharisk_out),
// input data from gtx
.rxdata_in (rxdata_in),
.rxcharisk_in (rxcharisk_in),
// bypassed data from gtx
.rxdata_out (rxdata_out),
.rxcharisk_out (rxcharisk_out),
// oob sequence needs to be issued
.oob_start (oob_start),
// connection established, all further data is valid
.oob_done (oob_done),
// doc p265, link is established after 3back-to-back non-ALIGNp
.link_up (link_up),
.link_down (link_down),
// the device itself sends cominit
.cominit_req (cominit_req),
// allow to respond to cominit
.cominit_allow (cominit_allow),
// status information to handle by a control block if any exists
// incompatible host-device speed grades (host cannot lock to alignp)
.oob_incompatible (oob_incompatible),
// timeout in an unexpected place
.oob_error (oob_error),
// noone responds to our cominits
.oob_silence (oob_silence),
// oob can't handle new start request
.oob_busy (oob_busy)
);
endmodule
device/sata_device.v
View file @ 340db2c6
......@@ -18,7 +18,7 @@
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`include "sata_phy_dev.v"
//`include "sata_phy_dev.v"
module sata_device(
input wire rst,
input wire RXN,
......
device/sata_phy_dev.v
View file @ 340db2c6
......@@ -18,7 +18,7 @@
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`include "oob_dev.v"
//`include "oob_dev.v"
module sata_phy_dev #(
parameter DATA_BYTE_WIDTH = 4
)
......
dma/axi_regs.v
View file @ 340db2c6
......@@ -18,8 +18,8 @@
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`include "axibram_read.v"
`include "axibram_write.v"
//`include "axibram_read.v"
//`include "axibram_write.v"
module axi_regs #(
parameter REGISTERS_CNT = 20
)
......
dma/sata_top.v
View file @ 340db2c6
......@@ -19,12 +19,12 @@
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
`include "axi_regs.v"
`include "dma_regs.v"
`include "sata_host.v"
`include "dma_adapter.v"
`include "dma_control.v"
`include "membridge.v"
//`include "axi_regs.v"
//`include "dma_regs.v"
//`include "sata_host.v"
//`include "dma_adapter.v"
//`include "dma_control.v"
//`include "membridge.v"
/*
* Takes commands from axi iface as a slave, transfers data with another axi iface as a master
*/
......
dma/send_dma.v deleted 100644 → 0
View file @ 680098f2
This diff is collapsed.
dma/top.v
View file @ 340db2c6
......@@ -24,7 +24,7 @@
* what is called now 'axi_regs' and connect it
*/
`include "system_defines.vh"
`include "sata_top.v"
//`include "sata_top.v"
module top #(
`include "includes/x393_parameters.vh"
)
......
gtxe2_gpl @ c4c7e576
Subproject commit c4c7e57675cc07463b0c9c09937281652a60a6bf
host/gtx_wrap.v
View file @ 340db2c6
......@@ -18,10 +18,10 @@
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`include "gtx_8x10enc.v"
`include "gtx_10x8dec.v"
`include "gtx_comma_align.v"
`include "gtx_elastic.v"
//`include "gtx_8x10enc.v"
//`include "gtx_10x8dec.v"
//`include "gtx_comma_align.v"
//`include "gtx_elastic.v"
// All computations have been done in assumption of GTX interface being 20 bits wide!
module gtx_wrap #(
parameter DATA_BYTE_WIDTH = 4,
......@@ -391,7 +391,7 @@ else begin
end
endgenerate
GTXE2_CHANNEL #(
gtxe2_channel_wrapper #(
.SIM_RECEIVER_DETECT_PASS ("TRUE"),
.SIM_TX_EIDLE_DRIVE_LEVEL ("X"),
.SIM_RESET_SPEEDUP ("FALSE"),
......@@ -592,7 +592,7 @@ GTXE2_CHANNEL #(
.RX_DFE_XYD_CFG (13'b0000000000000),
.TX_PREDRIVER_MODE (1'b0)
)
gtx(
gtxe2_channel_wrapper(
.CPLLFBCLKLOST (),
.CPLLLOCK (cplllock),
.CPLLLOCKDETCLK (cplllockdetclk),
......
host/link.v
View file @ 340db2c6
......@@ -18,8 +18,8 @@
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`include "scrambler.v"
`include "crc.v"
//`include "scrambler.v"
//`include "crc.v"
module link #(
// 4 = dword. 4-bytes aligned data transfers TODO 2 = word - easy, 8 = qword - difficult
parameter DATA_BYTE_WIDTH = 4
......
host/oob.v
View file @ 340db2c6
......@@ -299,8 +299,8 @@ generate
else
if (DATA_BYTE_WIDTH == 8)
begin
assign detected_alignp = ~|(rxdata ^ {2{8'b01111011, 8'b01001010, 8'b01001010, 8'b10111100}}) & ~|(rxcharisk ^ 8'h11); // {D27.3, D10.2, D10.2, K28.5}
assign detected_syncp = ~|(rxdata ^ {2{8'b10110101, 8'b10110101, 8'b10010101, 8'b01111100}}) & ~|(rxcharisk ^ 8'h11); // {D21.5, D21.5, D21.4, K28.3}
assign detected_alignp = ~|(rxdata ^ {8'b01111011, 8'b01001010, 8'b01001010, 8'b10111100, 8'b01111011, 8'b01001010, 8'b01001010, 8'b10111100}) & ~|(rxcharisk ^ 8'h11); // {D27.3, D10.2, D10.2, K28.5}
assign detected_syncp = ~|(rxdata ^ {8'b10110101, 8'b10110101, 8'b10010101, 8'b01111100, 8'b10110101, 8'b10110101, 8'b10010101, 8'b01111100}) & ~|(rxcharisk ^ 8'h11); // {D21.5, D21.5, D21.4, K28.3}
end
else
begin
......@@ -381,7 +381,7 @@ generate
if (DATA_BYTE_WIDTH == 8)
begin
assign txcharisk_align = 8'h11;
assign txdata_align = {2{8'b01111011, 8'b01001010, 8'b01001010, 8'b10111100}}; // 2x{D27.3, D10.2, D10.2, K28.5}
assign txdata_align = {8'b01111011, 8'b01001010, 8'b01001010, 8'b10111100, 8'b01111011, 8'b01001010, 8'b01001010, 8'b10111100}; // 2x{D27.3, D10.2, D10.2, K28.5}
end
else
always @ (posedge clk)
......
host/oob_ctrl.v
View file @ 340db2c6
......@@ -18,7 +18,7 @@
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`include "oob.v"
//`include "oob.v"
module oob_ctrl #(
parameter DATA_BYTE_WIDTH = 4,
parameter CLK_SPEED_GRADE = 1 // 1 - 75 Mhz, 2 - 150Mhz, 4 - 300Mhz
......
host/sata_host.v
View file @ 340db2c6
......@@ -18,10 +18,10 @@
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`include "sata_phy.v"
`include "link.v"
`include "transport.v"
`include "command.v"
//`include "sata_phy.v"
//`include "link.v"
//`include "transport.v"
//`include "command.v"
module sata_host(
input wire extrst,
......
host/sata_phy.v
View file @ 340db2c6
......@@ -18,8 +18,8 @@
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`include "oob_ctrl.v"
`include "gtx_wrap.v"
//`include "oob_ctrl.v"
//`include "gtx_wrap.v"
module sata_phy #(
parameter DATA_BYTE_WIDTH = 4
)
......
simul/build deleted 100755 → 0
View file @ 680098f2
#!/bin/bash
LOGFILE_PATH="bld.log"
rm a.out
if [ "$SATA_PATH" == '' ]
then
export SATA_PATH=".."
fi
if [ "$UNISIMS_PATH" == '' ]
then
export UNISIMS_PATH="../x393/unisims"
fi
if [ "$HOST_PATH" == '' ]
then
export HOST_PATH="../host"
fi
if [ "$GTX_PATH" == '' ]
then
export GTX_PATH=$SATA_PATH
fi
#iverilog $SATA_PATH/tb/tb_top.v $SATA_PATH/x393/glbl.v $SATA_PATH/gtxe2_gpl/GTXE2_CHANNEL.v -I$SATA_PATH/device -I$SATA_PATH/host -I$SATA_PATH/dma -I$SATA_PATH/tb -I$SATA_PATH -I$SATA_PATH/x393/axi -I$SATA_PATH/x393 -I$SATA_PATH/x393/wrap -y$SATA_PATH/x393/util_modules -y$SATA_PATH/x393/wrap -y$UNISIMS_PATH -y$SATA_PATH/x393/memctrl -y$SATA_PATH/x393/axi -y$SATA_PATH/x393/simulation_modules $SATA_PATH/x393/simulation_modules/simul_axi_fifo_out.v -y$SATA_PATH/x393/ -D SIMULATION -D CHECKERS_ENABLED
iverilog $SATA_PATH/tb/tb_top.v $SATA_PATH/x393/glbl.v $SATA_PATH/gtxe2_gpl/GTXE2_CHANNEL.v -I$SATA_PATH/device -I$SATA_PATH/host -I$SATA_PATH/dma -I$SATA_PATH/tb -I$SATA_PATH -I$SATA_PATH/x393/axi -I$SATA_PATH/x393 -I$SATA_PATH/x393/wrap -y$SATA_PATH/x393/util_modules -y$SATA_PATH/x393/wrap -y$UNISIMS_PATH -y$SATA_PATH/x393/memctrl -y$SATA_PATH/x393/axi -y$SATA_PATH/x393/simulation_modules $SATA_PATH/x393/simulation_modules/simul_axi_fifo_out.v -y$SATA_PATH/x393/ -D SIMULATION -D CHECKERS_ENABLED
#iverilog $SATA_PATH/neat_phy.v $SATA_PATH/x393/glbl.v $SATA_PATH/gtxe2_gpl/GTXE2_CHANNEL.v $SATA_PATH/neat_oob.v -y$UNISIMS_PATH
#iverilog $SATA_PATH/tb/tb_top.v $SATA_PATH/x393/glbl.v -f opts -stb -sglbl $1 2>&1| tee $LOGFILE_PATH
#-y$SATA_PATH/x393/util_modules -I$SATA_PATH/x393/ -I$SATA_PATH/x393/axi/ $SATA_PATH/tb/tb_axiregs.v -I$SATA_PATH/ -I$SATA_PATH/tb/
simul/doall deleted 100755 → 0
View file @ 680098f2
#!/bin/bash
if [ ! -z "$1" ]
then
SAV_FILE=$1
else
SAV_FILE="save.gtkw"
fi
./build #-pfileline=1
./simul
if [ $? != 0 ]
then
echo "BUILD FAILED"
exit
else
gtkwave test.vcd $SAV_FILE &> waves.log &
fi
echo all done
simul/opts deleted 100644 → 0
View file @ 680098f2
-v ${SATA_PATH}/x393/simulation_modules/simul_axi_fifo_out.v
-y ${SATA_PATH}/x393/simulation_modules
-y ${SATA_PATH}/x393/memctrl
-y ${SATA_PATH}/x393/wrap
-y ${UNISIMS_PATH}/
-y ${SATA_PATH}/x393/util_modules
-v ${SATA_PATH}/x393/axi_hp_clk.v
+incdir+${SATA_PATH}/tb/
+incdir+${SATA_PATH}/x393/
+incdir+${SATA_PATH}/x393/axi/
+incdir+${SATA_PATH}/
simul/simul deleted 100755 → 0
View file @ 680098f2
#!/bin/bash
LOGFILE_PATH="sim.log"
/usr/local/bin/vvp a.out -v $1 #|tee $LOGFILE_PATH
#2>&1 | tee $LOGFILE_PATH
tb/tb_axiregs.v deleted 100644 → 0
View file @ 680098f2
/*******************************************************************************
* Module: tb
* Date: 2015-07-11
* Author: Alexey
* Description: testbench for axi_regs.v
*
* Copyright (c) 2015 Elphel, Inc.
* tb_axiregs.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* tb_axiregs.v file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ns
`include "axi_regs.v"
`include "test_axi_regs.v"
module tb();
initial #1 $display("HI THERE");
initial
begin
$dumpfile("test.vcd");
$dumpvars(0,tb);
end
wire ACLK; // AXI PS Master GP1 Clock , input
wire ARESETN; // AXI PS Master GP1 Reset, output
wire [31:0] ARADDR; // AXI PS Master GP1 ARADDR[31:0], output
wire ARVALID; // AXI PS Master GP1 ARVALID, output
wire ARREADY; // AXI PS Master GP1 ARREADY, input
wire [11:0] ARID; // AXI PS Master GP1 ARID[11:0], output
wire [1:0] ARLOCK; // AXI PS Master GP1 ARLOCK[1:0], output
wire [3:0] ARCACHE; // AXI PS Master GP1 ARCACHE[3:0], output
wire [2:0] ARPROT; // AXI PS Master GP1 ARPROT[2:0], output
wire [3:0] ARLEN; // AXI PS Master GP1 ARLEN[3:0], output
wire [1:0] ARSIZE; // AXI PS Master GP1 ARSIZE[1:0], output
wire [1:0] ARBURST; // AXI PS Master GP1 ARBURST[1:0], output
wire [3:0] ARQOS; // AXI PS Master GP1 ARQOS[3:0], output
wire [31:0] RDATA; // AXI PS Master GP1 RDATA[31:0], input
wire RVALID; // AXI PS Master GP1 RVALID, input
wire RREADY; // AXI PS Master GP1 RREADY, output
wire [11:0] RID; // AXI PS Master GP1 RID[11:0], input
wire RLAST; // AXI PS Master GP1 RLAST, input
wire [1:0] RRESP; // AXI PS Master GP1 RRESP[1:0], input
wire [31:0] AWADDR; // AXI PS Master GP1 AWADDR[31:0], output
wire AWVALID; // AXI PS Master GP1 AWVALID, output
wire AWREADY; // AXI PS Master GP1 AWREADY, input
wire [11:0] AWID; // AXI PS Master GP1 AWID[11:0], output
wire [1:0] AWLOCK; // AXI PS Master GP1 AWLOCK[1:0], output
wire [3:0] AWCACHE; // AXI PS Master GP1 AWCACHE[3:0], output
wire [2:0] AWPROT; // AXI PS Master GP1 AWPROT[2:0], output
wire [3:0] AWLEN; // AXI PS Master GP1 AWLEN[3:0], outpu:t
wire [1:0] AWSIZE; // AXI PS Master GP1 AWSIZE[1:0], output
wire [1:0] AWBURST; // AXI PS Master GP1 AWBURST[1:0], output
wire [3:0] AWQOS; // AXI PS Master GP1 AWQOS[3:0], output
wire [31:0] WDATA; // AXI PS Master GP1 WDATA[31:0], output
wire WVALID; // AXI PS Master GP1 WVALID, output
wire WREADY; // AXI PS Master GP1 WREADY, input
wire [11:0] WID; // AXI PS Master GP1 WID[11:0], output
wire WLAST; // AXI PS Master GP1 WLAST, output
wire [3:0] WSTRB; // AXI PS Master GP1 WSTRB[3:0], output
wire BVALID; // AXI PS Master GP1 BVALID, input
wire BREADY; // AXI PS Master GP1 BREADY, output
wire [11:0] BID; // AXI PS Master GP1 BID[11:0], input
wire [1:0] BRESP; // AXI PS Master GP1 BRESP[1:0], input
/*
axibram_write dut(
.aclk (ACLK),
.rst (~ARESETN),
.awaddr (AWADDR),
.awvalid (AWVALID),
.awready (AWREADY),
.awid (AWID),
.awlen (AWLEN),
.awsize (AWSIZE),
.awburst (AWBURST),
.wdata (WDATA),
.wvalid (WVALID),
.wready (WREADY),
.wid (WID),
.wlast (WLAST),
.wstb (WSTRB),
.bvalid (BVALID),
.bready (BREADY),
.bid (BID),
.bresp (BRESP),
.pre_awaddr (),
.start_burst (),
.dev_ready (1'b1),
.bram_wclk (),
.bram_waddr (),
.bram_wen (),
.bram_wstb (),
.bram_wdata ()
);
axibram_read dut2(
.aclk (ACLK),
.rst (~ARESETN),
.araddr (ARADDR),
.arvalid (ARVALID),
.arready (ARREADY),
.arid (ARID),
.arlen (ARLEN),
.arsize (ARSIZE),
.arburst (ARBURST),
.rdata (RDATA),
.rvalid (RVALID),
.rready (RREADY),
.rid (RID),
.rlast (RLAST),
.rresp (RRESP),
.pre_araddr (),
.start_burst (),
.dev_ready (1'b1),
.bram_rclk (),
.bram_raddr (),
.bram_ren (bram_ren),
.bram_regen (),
.bram_rdata (bram_ren ? 32'hdeadbeef : 0)
);
*/
axi_regs dut(
.ACLK (ACLK),
.ARESETN (ARESETN),
.ARADDR (ARADDR),
.ARVALID (ARVALID),
.ARREADY (ARREADY),
.ARID (ARID),
.ARLOCK (ARLOCK),
.ARCACHE (ARCACHE),
.ARPROT (ARPROT),
.ARLEN (ARLEN),
.ARSIZE (ARSIZE),
.ARBURST (ARBURST),
.ARQOS (ARQOS),
.RDATA (RDATA),
.RVALID (RVALID),
.RREADY (RREADY),
.RID (RID),
.RLAST (RLAST),
.RRESP (RRESP),
.AWADDR (AWADDR),
.AWVALID (AWVALID),
.AWREADY (AWREADY),
.AWID (AWID),
.AWLOCK (AWLOCK),
.AWCACHE (AWCACHE),
.AWPROT (AWPROT),
.AWLEN (AWLEN),
.AWSIZE (AWSIZE),
.AWBURST (AWBURST),
.AWQOS (AWQOS),
.WDATA (WDATA),
.WVALID (WVALID),
.WREADY (WREADY),
.WID (WID),
.WLAST (WLAST),
.WSTRB (WSTRB),
.BVALID (BVALID),
.BREADY (BREADY),
.BID (BID),
.BRESP (BRESP)
);
test_axi_regs test(
.ACLK (ACLK),
.ARESETN (ARESETN),
.ARADDR (ARADDR),
.ARVALID (ARVALID),
.ARREADY (ARREADY),
.ARID (ARID),
.ARLOCK (ARLOCK),
.ARCACHE (ARCACHE),
.ARPROT (ARPROT),
.ARLEN (ARLEN),
.ARSIZE (ARSIZE),
.ARBURST (ARBURST),
.ARQOS (ARQOS),
.RDATA (RDATA),
.RVALID (RVALID),
.RREADY (RREADY),
.RID (RID),
.RLAST (RLAST),
.RRESP (RRESP),
.AWADDR (AWADDR),
.AWVALID (AWVALID),
.AWREADY (AWREADY),
.AWID (AWID),
.AWLOCK (AWLOCK),
.AWCACHE (AWCACHE),
.AWPROT (AWPROT),
.AWLEN (AWLEN),
.AWSIZE (AWSIZE),
.AWBURST (AWBURST),
.AWQOS (AWQOS),
.WDATA (WDATA),
.WVALID (WVALID),
.WREADY (WREADY),
.WID (WID),
.WLAST (WLAST),
.WSTRB (WSTRB),
.BVALID (BVALID),
.BREADY (BREADY),
.BID (BID),
.BRESP (BRESP)
);
endmodule
tb/tb_top.v
View file @ 340db2c6
......@@ -18,12 +18,17 @@
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
// set of global defines
`define SIMULATION
`define CHECKERS_ENABLED
`define OPEN_SOURCE_ONLY
/*
* using x393_testbench01.tf style, contains a lot of copy-pasted code from there
*/
`timescale 1ns/1ps
`include "top.v"
`include "sata_device.v"
//`include "top.v"
//`include "sata_device.v"
module tb #(
`include "includes/x393_parameters.vh" // SuppressThisWarning VEditor - not used
......@@ -31,10 +36,16 @@ module tb #(
)
(
);
`ifdef IVERILOG
`include "IVERILOG_INCLUDE.v"
`else // IVERILOG
parameter lxtname = "x393.lxt";
`endif // IVERILOG
initial #1 $display("HI THERE");
initial
begin
$dumpfile("test.vcd");
$dumpfile(lxtname);
$dumpvars(0,tb);
end
......
tb/test_axi_regs.v deleted 100644 → 0
View file @ 680098f2
/*******************************************************************************
* Module: test_axi_regs
* Date: 2015-07-11
* Author: Alexey
* Description: test generator for axi_regs.v
*
* Copyright (c) 2015 Elphel, Inc.
* test_axi_regs.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* test_axi_regs.v file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
module test_axi_regs(
output reg ACLK,
output reg ARESETN,
// AXI PS Master GP1: Read Address
output reg [31:0] ARADDR,
output reg ARVALID,
input wire ARREADY,
output reg [11:0] ARID,
output reg [1:0] ARLOCK,
output reg [3:0] ARCACHE,
output reg [2:0] ARPROT,
output reg [3:0] ARLEN,
output reg [1:0] ARSIZE,
output reg [1:0] ARBURST,
output reg [3:0] ARQOS,
// AXI PS Master GP1: Read Data
input wire [31:0] RDATA,
input wire RVALID,
output reg RREADY,
input wire [11:0] RID,
input wire RLAST,
input wire [1:0] RRESP,
// AXI PS Master GP1: Write Address
output reg [31:0] AWADDR,
output reg AWVALID,
input wire AWREADY,
output reg [11:0] AWID,
output reg [1:0] AWLOCK,
output reg [3:0] AWCACHE,
output reg [2:0] AWPROT,
output reg [3:0] AWLEN,
output reg [1:0] AWSIZE,
output reg [1:0] AWBURST,
output reg [3:0] AWQOS,
// AXI PS Master GP1: Write Data
output reg [31:0] WDATA,
output reg WVALID,
input wire WREADY,
output reg [11:0] WID,
output reg WLAST,
output reg [3:0] WSTRB,
// AXI PS Master GP1: Write Responce
input wire BVALID,
output reg BREADY,
input wire [11:0] BID,
input wire [1:0] BRESP
);
// finish
initial #5000 $finish;
// clock
initial
ACLK = 0;
always #5
ACLK = ~ACLK;
// reset
initial
begin
#50;
ARESETN <= 1'b1;
#50;
ARESETN <= 1'b0;
#50;
ARESETN <= 1'b1;
end
// Trying to write a word
initial
begin
ARVALID <= 1'b0;
ARADDR <= 1'b0;
ARID <= 1'b0;
ARLOCK <= 1'b0;
ARCACHE <= 1'b0;
ARPROT <= 1'b0;
ARLEN <= 1'b0;
ARSIZE <= 1'b0;
ARBURST <= 1'b0;
RREADY <= 1'b0;
AWVALID <= 1'b0;
AWADDR <= 1'b0;
AWID <= 1'b0;
AWLOCK <= 1'b0;
AWCACHE <= 1'b0;
AWPROT <= 1'b0;
AWLEN <= 1'b0;
AWSIZE <= 1'b0;
AWBURST <= 1'b0;
WVALID <= 1'b0;
WID <= 1'b0;
WSTRB <= 1'b0;
#220;
repeat (10)
@ (posedge ACLK);
AWVALID <= 1'b1;
AWADDR <= 32'h5;
AWID <= 1'b0;
AWLOCK <= 1'b0;
AWCACHE <= 1'b0;
AWPROT <= 1'b0;
AWLEN <= 1'b0;
AWSIZE <= 2'b10;
AWBURST <= 1'b0;
if (AWREADY == 1'b0)
@ (posedge AWREADY);
@ (posedge ACLK);
AWVALID <= 1'b0;
WDATA <= 32'hdeadbeef;
WVALID <= 1'b1;
WSTRB <= 4'b1011;
WID <= 12'h123;
if (WREADY == 1'b0)
@ (posedge WREADY);
@ (posedge ACLK);
WVALID <= 1'b0;
repeat (10)
@ (posedge ACLK);
// Trying to read a word
#170;
repeat (10)
@ (posedge ACLK);
ARADDR <= 32'h5;
ARVALID <= 1'b1;
ARID <= 1'b0;
ARLOCK <= 1'b0;
ARCACHE <= 1'b0;
ARPROT <= 1'b0;
ARLEN <= 1'b0;
ARSIZE <= 1'b0;
ARBURST <= 1'b0;
if (ARREADY == 1'b0)
@ (posedge ARREADY);
@ (posedge ACLK);
ARVALID <= 1'b0;
RREADY <= 1'b1;
if (RVALID == 1'b0)
@ (posedge RVALID);
@ (posedge ACLK);
RREADY <= 1'b0;
end
*/
// Simulation modules
simul_axi_master_rdaddr
#(
.ID_WIDTH(12),
.ADDRESS_WIDTH(32),
.LATENCY(AXI_RDADDR_LATENCY), // minimal delay between inout and output ( 0 - next cycle)
.DEPTH(8), // maximal number of commands in FIFO
.DATA_DELAY(3.5),
.VALID_DELAY(4.0)
) simul_axi_master_rdaddr_i (
.clk(CLK),
.reset(RST),
.arid_in(ARID_IN[11:0]),
.araddr_in(ARADDR_IN[31:0]),
.arlen_in(ARLEN_IN[3:0]),
.arsize_in(ARSIZE_IN[2:0]),
.arburst_in(ARBURST_IN[1:0]),
.arcache_in(4'b0),
.arprot_in(3'b0), // .arprot_in(2'b0),
.arid(arid[11:0]),
.araddr(araddr[31:0]),
.arlen(arlen[3:0]),
.arsize(arsize[2:0]),
.arburst(arburst[1:0]),
.arcache(arcache[3:0]),
.arprot(arprot[2:0]),
.arvalid(arvalid),
.arready(arready),
.set_cmd(AR_SET_CMD), // latch all other input data at posedge of clock
.ready(AR_READY) // command/data FIFO can accept command
);
simul_axi_master_wraddr
#(
.ID_WIDTH(12),
.ADDRESS_WIDTH(32),
.LATENCY(AXI_WRADDR_LATENCY), // minimal delay between inout and output ( 0 - next cycle)
.DEPTH(8), // maximal number of commands in FIFO
.DATA_DELAY(3.5),
.VALID_DELAY(4.0)
) simul_axi_master_wraddr_i (
.clk(CLK),
.reset(RST),
.awid_in(AWID_IN[11:0]),
.awaddr_in(AWADDR_IN[31:0]),
.awlen_in(AWLEN_IN[3:0]),
.awsize_in(AWSIZE_IN[2:0]),
.awburst_in(AWBURST_IN[1:0]),
.awcache_in(4'b0),
.awprot_in(3'b0), //.awprot_in(2'b0),
.awid(awid[11:0]),
.awaddr(awaddr[31:0]),
.awlen(awlen[3:0]),
.awsize(awsize[2:0]),
.awburst(awburst[1:0]),
.awcache(awcache[3:0]),
.awprot(awprot[2:0]),
.awvalid(awvalid),
.awready(awready),
.set_cmd(AW_SET_CMD), // latch all other input data at posedge of clock
.ready(AW_READY) // command/data FIFO can accept command
);
simul_axi_master_wdata
#(
.ID_WIDTH(12),
.DATA_WIDTH(32),
.WSTB_WIDTH(4),
.LATENCY(AXI_WRDATA_LATENCY), // minimal delay between inout and output ( 0 - next cycle)
.DEPTH(8), // maximal number of commands in FIFO
.DATA_DELAY(3.2),
.VALID_DELAY(3.6)
) simul_axi_master_wdata_i (
.clk(CLK),
.reset(RST),
.wid_in(WID_IN[11:0]),
.wdata_in(WDATA_IN[31:0]),
.wstrb_in(WSTRB_IN[3:0]),
.wlast_in(WLAST_IN),
.wid(wid[11:0]),
.wdata(wdata[31:0]),
.wstrb(wstrb[3:0]),
.wlast(wlast),
.wvalid(wvalid),
.wready(wready),
.set_cmd(W_SET_CMD), // latch all other input data at posedge of clock
.ready(W_READY) // command/data FIFO can accept command
);
simul_axi_slow_ready simul_axi_slow_ready_read_i(
.clk(CLK),
.reset(RST), //input reset,
.delay(RD_LAG), //input [3:0] delay,
.valid(rvalid), // input valid,
.ready(rready) //output ready
);
simul_axi_slow_ready simul_axi_slow_ready_write_resp_i(
.clk(CLK),
.reset(RST), //input reset,
.delay(B_LAG), //input [3:0] delay,
.valid(bvalid), // input ADDRESS_NUMBER+2:0 valid,
.ready(bready) //output ready
);
simul_axi_read #(
.ADDRESS_WIDTH(SIMUL_AXI_READ_WIDTH)
) simul_axi_read_i(
.clk(CLK),
.reset(RST),
.last(rlast),
.data_stb(rstb),
.raddr(ARADDR_IN[SIMUL_AXI_READ_WIDTH+1:2]),
.rlen(ARLEN_IN),
.rcmd(AR_SET_CMD),
.addr_out(SIMUL_AXI_ADDR_W[SIMUL_AXI_READ_WIDTH-1:0]),
.burst(), // burst in progress - just debug
.err_out()); // data last does not match predicted or FIFO over/under run - just debug
endmodule
wrapper/GTXE2_GPL.v 0 → 100644
View file @ 340db2c6
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wrapper/gtxe2_channel_wrapper.v 0 → 100644
View file @ 340db2c6
This diff is collapsed.
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