Commit 340db2c6 authored by Alexey Grebenkin's avatar Alexey Grebenkin
Browse files

VDT-only support added. For non-VDT applications, see non-vdt branch

parent 680098f2

.gitmodules

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[submodule "x393"]

[submodule "x393"]

	path = x393

	path = x393

	url = https://github.com/Elphel/x393.git
 
	url = https://github.com/Elphel/x393.git
 
[submodule "gtxe2_gpl"]

	path = gtxe2_gpl

	url = https://github.com/Elphel/gtxe2_gpl

.project

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<?xml version="1.0" encoding="UTF-8"?>

<projectDescription>

	<name>x393_sata</name>

	<comment></comment>

	<projects>

	</projects>

	<buildSpec>

		<buildCommand>

			<name>com.elphel.vdt.veditor.simulateBuilder</name>

			<arguments>

				<dictionary>

					<key>com.elphel.vdt.veditor.simulateBuilder.00000000Default.CleanCommand</key>

					<value>echo &apos;Clean&apos;</value>

				</dictionary>

				<dictionary>

					<key>com.elphel.vdt.veditor.simulateBuilder.00000000Default.buildOrder</key>

					<value>0</value>

				</dictionary>

				<dictionary>

					<key>com.elphel.vdt.veditor.simulateBuilder.00000000Default.command</key>

					<value>echo &apos;No Build Configuration Specified&apos;</value>

				</dictionary>

				<dictionary>

					<key>com.elphel.vdt.veditor.simulateBuilder.00000000Default.enable</key>

					<value>true</value>

				</dictionary>

				<dictionary>

					<key>com.elphel.vdt.veditor.simulateBuilder.00000000Default.name</key>

					<value>Default</value>

				</dictionary>

				<dictionary>

					<key>com.elphel.vdt.veditor.simulateBuilder.00000000Default.parser</key>

					<value></value>

				</dictionary>

				<dictionary>

					<key>com.elphel.vdt.veditor.simulateBuilder.00000000Default.workFolder</key>

					<value></value>

				</dictionary>

			</arguments>

		</buildCommand>

	</buildSpec>

	<natures>

		<nature>com.elphel.vdt.veditor.HdlNature</nature>

	</natures>

</projectDescription>

.settings/com.elphel.vdt.FPGA_project.prefs

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FPGA_project_0_SimulationTopFile=tb/tb_top.v

FPGA_project_1_SimulationTopModule=tb

FPGA_project_2_ImplementationTopFile=dma/top.v

FPGA_project_4_part=xc7z030fbg484-1

com.elphel.store.context.FPGA_project=FPGA_project_2_ImplementationTopFile<-@\#\#@->FPGA_project_4_part<-@\#\#@->FPGA_project_0_SimulationTopFile<-@\#\#@->FPGA_project_1_SimulationTopModule<-@\#\#@->

eclipse.preferences.version=1

.settings/com.elphel.vdt.ISExst.prefs

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ISExst_170_constraints=ddrc_test01.xcf

ISExst_96_OtherProblems=HDLCompiler\:413<-@\#\#@->

com.elphel.store.context.ISExst=ISExst_170_constraints<-@\#\#@->ISExst_96_OtherProblems<-@\#\#@->

eclipse.preferences.version=1

.settings/com.elphel.vdt.VivadoBitstream.prefs

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VivadoBitstream_103_PreBitstreamTCL=set_property BITSTREAM.STARTUP.MATCH_CYCLE NoWait [current_design]<-@\#\#@->

VivadoBitstream_105_force=true

com.elphel.store.context.VivadoBitstream=VivadoBitstream_105_force<-@\#\#@->VivadoBitstream_103_PreBitstreamTCL<-@\#\#@->

eclipse.preferences.version=1