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x393_sata
Commit 340db2c6 authored by Alexey Grebenkin's avatar Alexey Grebenkin
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VDT-only support added. For non-VDT applications, see non-vdt branch

parent 680098f2
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.gitmodules
View file @ 340db2c6
[submodule "x393"]
path = x393
url = https://github.com/Elphel/x393.git
[submodule "gtxe2_gpl"]
path = gtxe2_gpl
url = https://github.com/Elphel/gtxe2_gpl
.project 0 → 100644
View file @ 340db2c6
<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>x393_sata</name>
<comment></comment>
<projects>
</projects>
<buildSpec>
<buildCommand>
<name>com.elphel.vdt.veditor.simulateBuilder</name>
<arguments>
<dictionary>
<key>com.elphel.vdt.veditor.simulateBuilder.00000000Default.CleanCommand</key>
<value>echo &apos;Clean&apos;</value>
</dictionary>
<dictionary>
<key>com.elphel.vdt.veditor.simulateBuilder.00000000Default.buildOrder</key>
<value>0</value>
</dictionary>
<dictionary>
<key>com.elphel.vdt.veditor.simulateBuilder.00000000Default.command</key>
<value>echo &apos;No Build Configuration Specified&apos;</value>
</dictionary>
<dictionary>
<key>com.elphel.vdt.veditor.simulateBuilder.00000000Default.enable</key>
<value>true</value>
</dictionary>
<dictionary>
<key>com.elphel.vdt.veditor.simulateBuilder.00000000Default.name</key>
<value>Default</value>
</dictionary>
<dictionary>
<key>com.elphel.vdt.veditor.simulateBuilder.00000000Default.parser</key>
<value></value>
</dictionary>
<dictionary>
<key>com.elphel.vdt.veditor.simulateBuilder.00000000Default.workFolder</key>
<value></value>
</dictionary>
</arguments>
</buildCommand>
</buildSpec>
<natures>
<nature>com.elphel.vdt.veditor.HdlNature</nature>
</natures>
</projectDescription>
.settings/com.elphel.vdt.FPGA_project.prefs 0 → 100644
View file @ 340db2c6
FPGA_project_0_SimulationTopFile=tb/tb_top.v
FPGA_project_1_SimulationTopModule=tb
FPGA_project_2_ImplementationTopFile=dma/top.v
FPGA_project_4_part=xc7z030fbg484-1
com.elphel.store.context.FPGA_project=FPGA_project_2_ImplementationTopFile<-@\#\#@->FPGA_project_4_part<-@\#\#@->FPGA_project_0_SimulationTopFile<-@\#\#@->FPGA_project_1_SimulationTopModule<-@\#\#@->
eclipse.preferences.version=1
.settings/com.elphel.vdt.ISExst.prefs 0 → 100644
View file @ 340db2c6
ISExst_170_constraints=ddrc_test01.xcf
ISExst_96_OtherProblems=HDLCompiler\:413<-@\#\#@->
com.elphel.store.context.ISExst=ISExst_170_constraints<-@\#\#@->ISExst_96_OtherProblems<-@\#\#@->
eclipse.preferences.version=1
.settings/com.elphel.vdt.VivadoBitstream.prefs 0 → 100644
View file @ 340db2c6
VivadoBitstream_103_PreBitstreamTCL=set_property BITSTREAM.STARTUP.MATCH_CYCLE NoWait [current_design]<-@\#\#@->
VivadoBitstream_105_force=true
com.elphel.store.context.VivadoBitstream=VivadoBitstream_105_force<-@\#\#@->VivadoBitstream_103_PreBitstreamTCL<-@\#\#@->
eclipse.preferences.version=1
.settings/com.elphel.vdt.VivadoPlace.prefs 0 → 100644
View file @ 340db2c6
VivadoPlace_111_verbose_place=true
com.elphel.store.context.VivadoPlace=VivadoPlace_111_verbose_place<-@\#\#@->
eclipse.preferences.version=1
.settings/com.elphel.vdt.VivadoSynthesis.prefs 0 → 100644
View file @ 340db2c6
VivadoSynthesis_101_MaxMsg=10000
VivadoSynthesis_102_ConstraintsFiles=x393.xdc<-@\#\#@->x393_timing.xdc<-@\#\#@->
VivadoSynthesis_115_flatten_hierarchy=none
VivadoSynthesis_127_verbose=true
VivadoSynthesis_81_parser_mode=1
VivadoSynthesis_93_OtherProblems=Netlist 29-345<-@\#\#@->Board 49-26<-@\#\#@->
VivadoSynthesis_95_ShowInfo=false
com.elphel.store.context.VivadoSynthesis=VivadoSynthesis_102_ConstraintsFiles<-@\#\#@->VivadoSynthesis_95_ShowInfo<-@\#\#@->VivadoSynthesis_115_flatten_hierarchy<-@\#\#@->VivadoSynthesis_101_MaxMsg<-@\#\#@->VivadoSynthesis_127_verbose<-@\#\#@->VivadoSynthesis_93_OtherProblems<-@\#\#@->VivadoSynthesis_81_parser_mode<-@\#\#@->
eclipse.preferences.version=1
.settings/com.elphel.vdt.VivadoTimimgSummaryReportSynthesis.prefs 0 → 100644
View file @ 340db2c6
VivadoTimimgSummaryReportSynthesis_102_DisableVivadoTimingSummary=true
com.elphel.store.context.VivadoTimimgSummaryReportSynthesis=VivadoTimimgSummaryReportSynthesis_102_DisableVivadoTimingSummary<-@\#\#@->
eclipse.preferences.version=1
.settings/com.elphel.vdt.VivadoTimingReportImplemented.prefs 0 → 100644
View file @ 340db2c6
com.elphel.store.context.VivadoTimingReportImplemented=VivadoTimingReportImplemented_132_rawfile<-@\#\#@->
eclipse.preferences.version=1
.settings/com.elphel.vdt.VivadoTimingReportSynthesis.prefs 0 → 100644
View file @ 340db2c6
VivadoTimingReportSynthesis_102_DisableVivadoTiming=true
com.elphel.store.context.VivadoTimingReportSynthesis=VivadoTimingReportSynthesis_102_DisableVivadoTiming<-@\#\#@->
eclipse.preferences.version=1
.settings/com.elphel.vdt.iverilog.prefs 0 → 100644
View file @ 340db2c6
com.elphel.store.context.iverilog=iverilog_81_TopModulesOther<-@\#\#@->iverilog_83_ExtraFiles<-@\#\#@->iverilog_88_ShowNoProblem<-@\#\#@->iverilog_77_Param_Exe<-@\#\#@->iverilog_78_VVP_Exe<-@\#\#@->iverilog_99_GrepFindErrWarn<-@\#\#@->iverilog_89_ShowNoProblem<-@\#\#@->iverilog_79_GtkWave_Exe<-@\#\#@->iverilog_103_ExtraFiles<-@\#\#@->iverilog_104_IncludeDir<-@\#\#@->iverilog_101_TopModulesOther<-@\#\#@->iverilog_122_IVerilogOther<-@\#\#@->
eclipse.preferences.version=1
iverilog_101_TopModulesOther=glbl<-@\#\#@->
iverilog_103_ExtraFiles=x393/glbl.v<-@\#\#@->
iverilog_104_IncludeDir=${verilog_project_loc}/x393<-@\#\#@->${verilog_project_loc}/x393/includes<-@\#\#@->${verilog_project_loc}/host<-@\#\#@->${verilog_project_loc}/tb<-@\#\#@->
iverilog_122_IVerilogOther=-D OPEN_SOURCE_ONLY
iverilog_77_Param_Exe=/usr/local/bin/iverilog
iverilog_78_VVP_Exe=/usr/local/bin/vvp
iverilog_79_GtkWave_Exe=/usr/local/bin/gtkwave
iverilog_81_TopModulesOther=glbl<-@\#\#@->
iverilog_83_ExtraFiles=glbl.v<-@\#\#@->
iverilog_88_ShowNoProblem=true
iverilog_89_ShowNoProblem=true
iverilog_99_GrepFindErrWarn=error|warning|sorry
.settings/com.elphel.vdt.prefs 0 → 100644
View file @ 340db2c6
com.elphel.store.context.=com.elphel.vdt.PROJECT_DESING_MENU<-@\#\#@->
com.elphel.vdt.PROJECT_DESING_MENU=MainDesignMenu
eclipse.preferences.version=1
device/dev_phy.v deleted 100644 → 0
View file @ 680098f2
/*******************************************************************************
* Module: dev_phy
* Date: 2015-07-11
* Author: Alexey
* Description: sata device phy level
*
* Copyright (c) 2015 Elphel, Inc.
* dev_phy.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* dev_phy.v file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
/*
* Has minor differences from host's phy. After host would be rewritten all differences
* shall be eliminated.
* Despite having phy-level, the device for now is planned to be simulation purposes only.
*/
module sata_phy(
input wire RXP0_IN, // Receiver input
input wire RXN0_IN, // Receiver input
input wire GTXRESET_IN, // Main reset
input wire CLKIN_150, // external 150 mhz clock input
// Input from Link Layer
input wire [31:0] tx_datain,
input wire [3:0] tx_charisk_in,
output wire DCMLOCKED_OUT, // DCM locked
output wire PLLLKDET_OUT_N, // PLL Lock Detect
output wire TXP0_OUT,
output wire TXN0_OUT,
output wire LINKUP,
output wire LINKUP_led,
output wire GEN2_led,
output wire align_en_out,
output wire sata_user_clk,
// Outputs to Link Layer
output wire [31:0] rx_dataout,
output wire [3:0] rx_charisk_out,
output wire [7:0] CurrentState_out,
output wire rxelecidle_out,
// Rudiments
input wire [35:0] sata_phy_ila_control,
input wire [35:0] oob_control_ila_control
);
parameter CHIPSCOPE = "FALSE";
wire [31:0] txdata;
wire txcharisk;
wire [63:0] rxdata;
wire [7:0] rxcharisk;
wire [31:0] rxdata_out;
wire [3:0] rxcharisk_out;
wire linkup;
wire linkup_led;
wire rxcomwakedet;
wire rxcominitdet;
wire cplllock;
wire txcominit;
wire txcomwake;
wire rxreset;
wire rxelecidle;
wire txelecidle;
wire rxbyteisaligned;
OOB_control oob_control(
.oob_control_ila_control (36'h0),
//-------- GTX Ports --------/
.clk (sata_user_clk),
.reset (GTXRESET_IN),
.rxreset (/*rxreset*/),
.rx_locked (cplllock),
// OOB generation and detection signals from GTX
.txcominit (txcominit),
.txcomwake (txcomwake),
.cominitdet (rxcominitdet),
.comwakedet (rxcomwakedet),
.rxelecidle (rxelecidle),
.txelecidle_out (txelecidle),
.rxbyteisaligned (rxbyteisaligned),
.tx_dataout (txdata), // outgoing GTX data
.tx_charisk_out (txcharisk), // GTX charisk out
.rx_datain (rxdata[31:0]), // incoming GTX data
.rx_charisk_in (rxcharisk[3:0]), // GTX charisk in
.gen2 (1'b1), // for SATA Generation 2
//----- USER DATA PORTS---------//
.tx_datain (tx_datain), // User datain port
.tx_charisk_in (tx_charisk_in), // User charisk in port
.rx_dataout (rxdata_out), // User dataout port
.rx_charisk_out (rxcharisk_out), // User charisk out port
.linkup (linkup),
.linkup_led_out (linkup_led),
.align_en_out (align_en_out),
.CurrentState_out (CurrentState_out)
);
wire cplllockdetclk; // TODO
wire drpclk; // TODO
wire cpllreset;
wire gtrefclk;
wire rxresetdone;
wire txresetdone;
wire txreset;
wire txuserrdy;
wire rxuserrdy;
wire txusrclk;
wire txusrclk2;
wire rxusrclk;
wire rxusrclk2;
wire txp;
wire txn;
wire rxp;
wire rxn;
wire txoutclk;
wire txpmareset_done;
wire rxeyereset_done;
// tx reset sequence; waves @ ug476 p67
localparam TXPMARESET_TIME = 5'h1;
reg [2:0] txpmareset_cnt;
assign txpmareset_done = txpmareset_cnt == TXPMARESET_TIME;
always @ (posedge gtrefclk)
txpmareset_cnt <= txreset ? 3'h0 : txpmareset_done ? txpmareset_cnt : txpmareset_cnt + 1'b1;
// rx reset sequence; waves @ ug476 p77
localparam RXPMARESET_TIME = 5'h11;
localparam RXCDRPHRESET_TIME = 5'h1;
localparam RXCDRFREQRESET_TIME = 5'h1;
localparam RXDFELPMRESET_TIME = 7'hf;
localparam RXISCANRESET_TIME = 5'h1;
localparam RXEYERESET_TIME = 7'h0 + RXPMARESET_TIME + RXCDRPHRESET_TIME + RXCDRFREQRESET_TIME + RXDFELPMRESET_TIME + RXISCANRESET_TIME;
reg [6:0] rxeyereset_cnt;
assign rxeyereset_done = rxeyereset_cnt == RXEYERESET_TIME;
always @ (posedge gtrefclk)
rxeyereset_cnt <= rxreset ? 3'h0 : rxeyereset_done ? rxeyereset_cnt : rxeyereset_cnt + 1'b1;
/*
* Resets
*/
wire usrpll_locked;
assign cpllreset = GTXRESET_IN;
assign rxreset = ~cplllock | cpllreset;
assign txreset = ~cplllock | cpllreset;
assign rxuserrdy = usrpll_locked & cplllock & ~cpllreset & ~rxreset & rxeyereset_done;
assign txuserrdy = usrpll_locked & cplllock & ~cpllreset & ~txreset & txpmareset_done;
/*
* USRCLKs generation. USRCLK @ 150MHz, same as TXOUTCLK; USRCLK2 @ 75Mhz -> sata_clk === sclk
* It's recommended to use MMCM instead of PLL, whatever
*/
wire usrpll_fb_clk;
wire usrclk;
wire usrclk2;
assign txusrclk = usrclk;
assign txusrclk2 = usrclk2;
assign rxusrclk = usrclk;
assign rxusrclk2 = usrclk2;
PLLE2_ADV #(
.BANDWIDTH ("OPTIMIZED"),
.CLKFBOUT_MULT (8),
.CLKFBOUT_PHASE (0.000),
.CLKIN1_PERIOD (6.666),
.CLKIN2_PERIOD (0.000),
.CLKOUT0_DIVIDE (8),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_PHASE (0.000),
.CLKOUT1_DIVIDE (16),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT1_PHASE (0.000),
/* .CLKOUT2_DIVIDE = 1,
.CLKOUT2_DUTY_CYCLE = 0.500,
.CLKOUT2_PHASE = 0.000,
.CLKOUT3_DIVIDE = 1,
.CLKOUT3_DUTY_CYCLE = 0.500,
.CLKOUT3_PHASE = 0.000,
.CLKOUT4_DIVIDE = 1,
.CLKOUT4_DUTY_CYCLE = 0.500,
.CLKOUT4_PHASE = 0.000,
.CLKOUT5_DIVIDE = 1,
.CLKOUT5_DUTY_CYCLE = 0.500,
.CLKOUT5_PHASE = 0.000,*/
.COMPENSATION ("ZHOLD"),
.DIVCLK_DIVIDE (1),
.IS_CLKINSEL_INVERTED (1'b0),
.IS_PWRDWN_INVERTED (1'b0),
.IS_RST_INVERTED (1'b0),
.REF_JITTER1 (0.010),
.REF_JITTER2 (0.010),
.STARTUP_WAIT ("FALSE")
)
usrclk_pll(
.CLKFBOUT (usrpll_fb_clk),
.CLKOUT0 (usrclk),
.CLKOUT1 (usrclk2),
.CLKOUT2 (),
.CLKOUT3 (),
.CLKOUT4 (),
.CLKOUT5 (),
.DO (),
.DRDY (),
.LOCKED (usrpll_locked),
.CLKFBIN (usrpll_fb_clk),
.CLKIN1 (txoutclk),
.CLKIN2 (1'b0),
.CLKINSEL (1'b1),
.DADDR (7'h0),
.DCLK (drpclk),
.DEN (1'b0),
.DI (16'h0),
.DWE (1'b0),
.PWRDWN (1'b0),
.RST (~cplllock)
);
/*
* Padding for an external input clock @ 150 MHz
* TODO !!! Temporary moved to sata_top
*/
assign gtrefclk = CLKIN_150;
/*localparam [1:0] CLKSWING_CFG = 2'b11;
IBUFDS_GTE2 #(
.CLKRCV_TRST ("TRUE"),
.CLKCM_CFG ("TRUE"),
.CLKSWING_CFG (CLKSWING_CFG)
)
ext_clock_buf(
.I (REFCLK_PAD_P_IN),
.IB (REFCLK_PAD_N_IN),
.CEB (1'b0),
.O (gtrefclk),
.ODIV2 ()
);
*/
GTXE2_CHANNEL #(
.SIM_RECEIVER_DETECT_PASS ("TRUE"),
.SIM_TX_EIDLE_DRIVE_LEVEL ("X"),
.SIM_RESET_SPEEDUP ("FALSE"),
.SIM_CPLLREFCLK_SEL (3'b001),
.SIM_VERSION ("4.0"),
.ALIGN_COMMA_DOUBLE ("FALSE"),
.ALIGN_COMMA_ENABLE (10'b1111111111),
.ALIGN_COMMA_WORD (1),
.ALIGN_MCOMMA_DET ("TRUE"),
.ALIGN_MCOMMA_VALUE (10'b1010000011),
.ALIGN_PCOMMA_DET ("TRUE"),
.ALIGN_PCOMMA_VALUE (10'b0101111100),
.SHOW_REALIGN_COMMA ("TRUE"),
.RXSLIDE_AUTO_WAIT (7),
.RXSLIDE_MODE ("OFF"),
.RX_SIG_VALID_DLY (10),
.RX_DISPERR_SEQ_MATCH ("TRUE"),
.DEC_MCOMMA_DETECT ("TRUE"),
.DEC_PCOMMA_DETECT ("TRUE"),
.DEC_VALID_COMMA_ONLY ("FALSE"),
.CBCC_DATA_SOURCE_SEL ("DECODED"),
.CLK_COR_SEQ_2_USE ("FALSE"),
.CLK_COR_KEEP_IDLE ("FALSE"),
.CLK_COR_MAX_LAT (9),
.CLK_COR_MIN_LAT (7),
.CLK_COR_PRECEDENCE ("TRUE"),
.CLK_COR_REPEAT_WAIT (0),
.CLK_COR_SEQ_LEN (1),
.CLK_COR_SEQ_1_ENABLE (4'b1111),
.CLK_COR_SEQ_1_1 (10'b0100000000),
.CLK_COR_SEQ_1_2 (10'b0000000000),
.CLK_COR_SEQ_1_3 (10'b0000000000),
.CLK_COR_SEQ_1_4 (10'b0000000000),
.CLK_CORRECT_USE ("FALSE"),
.CLK_COR_SEQ_2_ENABLE (4'b1111),
.CLK_COR_SEQ_2_1 (10'b0100000000),
.CLK_COR_SEQ_2_2 (10'b0000000000),
.CLK_COR_SEQ_2_3 (10'b0000000000),
.CLK_COR_SEQ_2_4 (10'b0000000000),
.CHAN_BOND_KEEP_ALIGN ("FALSE"),
.CHAN_BOND_MAX_SKEW (1),
.CHAN_BOND_SEQ_LEN (1),
.CHAN_BOND_SEQ_1_1 (10'b0000000000),
.CHAN_BOND_SEQ_1_2 (10'b0000000000),
.CHAN_BOND_SEQ_1_3 (10'b0000000000),
.CHAN_BOND_SEQ_1_4 (10'b0000000000),
.CHAN_BOND_SEQ_1_ENABLE (4'b1111),
.CHAN_BOND_SEQ_2_1 (10'b0000000000),
.CHAN_BOND_SEQ_2_2 (10'b0000000000),
.CHAN_BOND_SEQ_2_3 (10'b0000000000),
.CHAN_BOND_SEQ_2_4 (10'b0000000000),
.CHAN_BOND_SEQ_2_ENABLE (4'b1111),
.CHAN_BOND_SEQ_2_USE ("FALSE"),
.FTS_DESKEW_SEQ_ENABLE (4'b1111),
.FTS_LANE_DESKEW_CFG (4'b1111),
.FTS_LANE_DESKEW_EN ("FALSE"),
.ES_CONTROL (6'b000000),
.ES_ERRDET_EN ("FALSE"),
.ES_EYE_SCAN_EN ("TRUE"),
.ES_HORZ_OFFSET (12'h000),
.ES_PMA_CFG (10'b0000000000),
.ES_PRESCALE (5'b00000),
.ES_QUALIFIER (80'h00000000000000000000),
.ES_QUAL_MASK (80'h00000000000000000000),
.ES_SDATA_MASK (80'h00000000000000000000),
.ES_VERT_OFFSET (9'b000000000),
.RX_DATA_WIDTH (20),
.OUTREFCLK_SEL_INV (2'b11),
.PMA_RSV (32'h00018480),
.PMA_RSV2 (16'h2050),
.PMA_RSV3 (2'b00),
.PMA_RSV4 (32'h00000000),
.RX_BIAS_CFG (12'b000000000100),
.DMONITOR_CFG (24'h000A00),
.RX_CM_SEL (2'b11),
.RX_CM_TRIM (3'b010),
.RX_DEBUG_CFG (12'b000000000000),
.RX_OS_CFG (13'b0000010000000),
.TERM_RCAL_CFG (5'b10000),
.TERM_RCAL_OVRD (1'b0),
.TST_RSV (32'h00000000),
.RX_CLK25_DIV (6),
.TX_CLK25_DIV (6),
.UCODEER_CLR (1'b0),
.PCS_PCIE_EN ("FALSE"),
.PCS_RSVD_ATTR (48'h0100),
.RXBUF_ADDR_MODE ("FAST"),
.RXBUF_EIDLE_HI_CNT (4'b1000),
.RXBUF_EIDLE_LO_CNT (4'b0000),
.RXBUF_EN ("TRUE"),
.RX_BUFFER_CFG (6'b000000),
.RXBUF_RESET_ON_CB_CHANGE ("TRUE"),
.RXBUF_RESET_ON_COMMAALIGN ("FALSE"),
.RXBUF_RESET_ON_EIDLE ("FALSE"),
.RXBUF_RESET_ON_RATE_CHANGE ("TRUE"),
.RXBUFRESET_TIME (5'b00001),
.RXBUF_THRESH_OVFLW (61),
.RXBUF_THRESH_OVRD ("FALSE"),
.RXBUF_THRESH_UNDFLW (4),
.RXDLY_CFG (16'h001F),
.RXDLY_LCFG (9'h030),
.RXDLY_TAP_CFG (16'h0000),
.RXPH_CFG (24'h000000),
.RXPHDLY_CFG (24'h084020),
.RXPH_MONITOR_SEL (5'b00000),
.RX_XCLK_SEL ("RXREC"),
.RX_DDI_SEL (6'b000000),
.RX_DEFER_RESET_BUF_EN ("TRUE"),
.RXCDR_CFG (72'h03000023ff10200020),
.RXCDR_FR_RESET_ON_EIDLE (1'b0),
.RXCDR_HOLD_DURING_EIDLE (1'b0),
.RXCDR_PH_RESET_ON_EIDLE (1'b0),
.RXCDR_LOCK_CFG (6'b010101),
.RXCDRFREQRESET_TIME (RXCDRFREQRESET_TIME),
.RXCDRPHRESET_TIME (RXCDRPHRESET_TIME),
.RXISCANRESET_TIME (RXISCANRESET_TIME),
.RXPCSRESET_TIME (5'b00001),
.RXPMARESET_TIME (RXPMARESET_TIME),
.RXOOB_CFG (7'b0000110),
.RXGEARBOX_EN ("FALSE"),
.GEARBOX_MODE (3'b000),
.RXPRBS_ERR_LOOPBACK (1'b0),
.PD_TRANS_TIME_FROM_P2 (12'h03c),
.PD_TRANS_TIME_NONE_P2 (8'h3c),
.PD_TRANS_TIME_TO_P2 (8'h64),
.SAS_MAX_COM (64),
.SAS_MIN_COM (36),
.SATA_BURST_SEQ_LEN (4'b0111),
.SATA_BURST_VAL (3'b110),
.SATA_EIDLE_VAL (3'b110),
.SATA_MAX_BURST (8),
.SATA_MAX_INIT (21),
.SATA_MAX_WAKE (7),
.SATA_MIN_BURST (4),
.SATA_MIN_INIT (12),
.SATA_MIN_WAKE (4),
.TRANS_TIME_RATE (8'h0E),
.TXBUF_EN ("TRUE"),
.TXBUF_RESET_ON_RATE_CHANGE ("TRUE"),
.TXDLY_CFG (16'h001F),
.TXDLY_LCFG (9'h030),
.TXDLY_TAP_CFG (16'h0000),
.TXPH_CFG (16'h0780),
.TXPHDLY_CFG (24'h084020),
.TXPH_MONITOR_SEL (5'b00000),
.TX_XCLK_SEL ("TXOUT"),
.TX_DATA_WIDTH (40),
.TX_DEEMPH0 (5'b00000),
.TX_DEEMPH1 (5'b00000),
.TX_EIDLE_ASSERT_DELAY (3'b110),
.TX_EIDLE_DEASSERT_DELAY (3'b100),
.TX_LOOPBACK_DRIVE_HIZ ("FALSE"),
.TX_MAINCURSOR_SEL (1'b0),
.TX_DRIVE_MODE ("DIRECT"),
.TX_MARGIN_FULL_0 (7'b1001110),
.TX_MARGIN_FULL_1 (7'b1001001),
.TX_MARGIN_FULL_2 (7'b1000101),
.TX_MARGIN_FULL_3 (7'b1000010),
.TX_MARGIN_FULL_4 (7'b1000000),
.TX_MARGIN_LOW_0 (7'b1000110),
.TX_MARGIN_LOW_1 (7'b1000100),
.TX_MARGIN_LOW_2 (7'b1000010),
.TX_MARGIN_LOW_3 (7'b1000000),
.TX_MARGIN_LOW_4 (7'b1000000),
.TXGEARBOX_EN ("FALSE"),
.TXPCSRESET_TIME (5'b00001),
.TXPMARESET_TIME (TXPMARESET_TIME),
.TX_RXDETECT_CFG (14'h1832),
.TX_RXDETECT_REF (3'b100),
.CPLL_CFG (24'hBC07DC),
.CPLL_FBDIV (4),
.CPLL_FBDIV_45 (5),
.CPLL_INIT_CFG (24'h00001E),
.CPLL_LOCK_CFG (16'h01E8),
.CPLL_REFCLK_DIV (1),
.RXOUT_DIV (2),
.TXOUT_DIV (2),
.SATA_CPLL_CFG ("VCO_3000MHZ"),
.RXDFELPMRESET_TIME (RXDFELPMRESET_TIME),
.RXLPM_HF_CFG (14'b00000011110000),
.RXLPM_LF_CFG (14'b00000011110000),
.RX_DFE_GAIN_CFG (23'h020FEA),
.RX_DFE_H2_CFG (12'b000000000000),
.RX_DFE_H3_CFG (12'b000001000000),
.RX_DFE_H4_CFG (11'b00011110000),
.RX_DFE_H5_CFG (11'b00011100000),
.RX_DFE_KL_CFG (13'b0000011111110),
.RX_DFE_LPM_CFG (16'h0954),
.RX_DFE_LPM_HOLD_DURING_EIDLE (1'b0),
.RX_DFE_UT_CFG (17'b10001111000000000),
.RX_DFE_VP_CFG (17'b00011111100000011),
.RX_CLKMUX_PD (1'b1),
.TX_CLKMUX_PD (1'b1),
.RX_INT_DATAWIDTH (0),
.TX_INT_DATAWIDTH (0),
.TX_QPI_STATUS_EN (1'b0),
.RX_DFE_KL_CFG2 (32'h301148AC),
.RX_DFE_XYD_CFG (13'b0000000000000),
.TX_PREDRIVER_MODE (1'b0)
)
dut(
.CPLLFBCLKLOST (),
.CPLLLOCK (cplllock),
.CPLLLOCKDETCLK (cplllockdetclk),
.CPLLLOCKEN (1'b1),
.CPLLPD (1'b0),
.CPLLREFCLKLOST (),
.CPLLREFCLKSEL (3'b001),
.CPLLRESET (cpllreset),
.GTRSVD (1'b0),
.PCSRSVDIN (1'b0),
.PCSRSVDIN2 (1'b0),
.PMARSVDIN (1'b0),
.PMARSVDIN2 (1'b0),
.TSTIN (1'b1),
.TSTOUT (),
.CLKRSVD (4'b0000),
.GTGREFCLK (1'b0),
.GTNORTHREFCLK0 (1'b0),
.GTNORTHREFCLK1 (1'b0),
.GTREFCLK0 (gtrefclk),
.GTREFCLK1 (1'b0),
.GTSOUTHREFCLK0 (1'b0),
.GTSOUTHREFCLK1 (1'b0),
.DRPADDR (9'b0),
.DRPCLK (drpclk),
.DRPDI (16'b0),
.DRPDO (),
.DRPEN (1'b0),
.DRPRDY (),
.DRPWE (1'b0),
.GTREFCLKMONITOR (),
.QPLLCLK (gtrefclk),
.QPLLREFCLK (gtrefclk),
.RXSYSCLKSEL (2'b00),
.TXSYSCLKSEL (2'b00),
.DMONITOROUT (),
.TX8B10BEN (1'b1),
.LOOPBACK (3'd0),
.PHYSTATUS (),
.RXRATE (3'd0),
.RXVALID (),
.RXPD (2'b00),
.TXPD (2'b00),
.SETERRSTATUS (1'b0),
.EYESCANRESET (1'b0),//rxreset), // p78
.RXUSERRDY (rxuserrdy),
.EYESCANDATAERROR (),
.EYESCANMODE (1'b0),
.EYESCANTRIGGER (1'b0),
.RXCDRFREQRESET (1'b0),
.RXCDRHOLD (1'b0),
.RXCDRLOCK (),
.RXCDROVRDEN (1'b0),
.RXCDRRESET (1'b0),
.RXCDRRESETRSV (1'b0),
.RXCLKCORCNT (),
.RX8B10BEN (1'b1),
.RXUSRCLK (rxusrclk),
.RXUSRCLK2 (rxusrclk2),
.RXDATA (rxdata),
.RXPRBSERR (),
.RXPRBSSEL (3'd0),
.RXPRBSCNTRESET (1'b0),
.RXDFEXYDEN (1'b1),
.RXDFEXYDHOLD (1'b0),
.RXDFEXYDOVRDEN (1'b0),
.RXDISPERR (),
.RXNOTINTABLE (),
.GTXRXP (rxp),
.GTXRXN (rxn),
.RXBUFRESET (1'b0),
.RXBUFSTATUS (),
.RXDDIEN (1'b0),
.RXDLYBYPASS (1'b1),
.RXDLYEN (1'b0),
.RXDLYOVRDEN (1'b0),
.RXDLYSRESET (1'b0),
.RXDLYSRESETDONE (),
.RXPHALIGN (1'b0),
.RXPHALIGNDONE (),
.RXPHALIGNEN (1'b0),
.RXPHDLYPD (1'b0),
.RXPHDLYRESET (1'b0),
.RXPHMONITOR (),
.RXPHOVRDEN (1'b0),
.RXPHSLIPMONITOR (),
.RXSTATUS (),
.RXBYTEISALIGNED (rxbyteisaligned),
.RXBYTEREALIGN (),
.RXCOMMADET (),
.RXCOMMADETEN (1'b1),
.RXMCOMMAALIGNEN (1'b1),
.RXPCOMMAALIGNEN (1'b1),
.RXCHANBONDSEQ (),
.RXCHBONDEN (1'b0),
.RXCHBONDLEVEL (3'd0),
.RXCHBONDMASTER (1'b0),
.RXCHBONDO (),
.RXCHBONDSLAVE (1'b0),
.RXCHANISALIGNED (),
.RXCHANREALIGN (),
.RXLPMHFHOLD (1'b0),
.RXLPMHFOVRDEN (1'b0),
.RXLPMLFHOLD (1'b0),
.RXDFEAGCHOLD (1'b0),
.RXDFEAGCOVRDEN (1'b0),
.RXDFECM1EN (1'b0),
.RXDFELFHOLD (1'b0),
.RXDFELFOVRDEN (1'b1),
.RXDFELPMRESET (rxreset),
.RXDFETAP2HOLD (1'b0),
.RXDFETAP2OVRDEN (1'b0),
.RXDFETAP3HOLD (1'b0),
.RXDFETAP3OVRDEN (1'b0),
.RXDFETAP4HOLD (1'b0),
.RXDFETAP4OVRDEN (1'b0),
.RXDFETAP5HOLD (1'b0),
.RXDFETAP5OVRDEN (1'b0),
.RXDFEUTHOLD (1'b0),
.RXDFEUTOVRDEN (1'b0),
.RXDFEVPHOLD (1'b0),
.RXDFEVPOVRDEN (1'b0),
// .RXDFEVSEN (1'b0),
.RXLPMLFKLOVRDEN (1'b0),
.RXMONITOROUT (),
.RXMONITORSEL (2'b01),
.RXOSHOLD (1'b0),
.RXOSOVRDEN (1'b0),
.RXRATEDONE (),
.RXOUTCLK (),
.RXOUTCLKFABRIC (),
.RXOUTCLKPCS (),
.RXOUTCLKSEL (3'b010),
.RXDATAVALID (),
.RXHEADER (),
.RXHEADERVALID (),
.RXSTARTOFSEQ (),
.RXGEARBOXSLIP (1'b0),
.GTRXRESET (rxreset),
.RXOOBRESET (1'b0),
.RXPCSRESET (1'b0),
.RXPMARESET (1'b0),//rxreset), // p78
.RXLPMEN (1'b0),
.RXCOMSASDET (),
.RXCOMWAKEDET (rxcomwakedet),
.RXCOMINITDET (rxcominitdet),
.RXELECIDLE (rxelecidle),
.RXELECIDLEMODE (2'b00),
.RXPOLARITY (1'b0),
.RXSLIDE (1'b0),
.RXCHARISCOMMA (),
.RXCHARISK (rxcharisk),
.RXCHBONDI (5'b00000),
.RXRESETDONE (rxresetdone),
.RXQPIEN (1'b0),
.RXQPISENN (),
.RXQPISENP (),
.TXPHDLYTSTCLK (1'b0),
.TXPOSTCURSOR (5'b00000),
.TXPOSTCURSORINV (1'b0),
.TXPRECURSOR (5'd0),
.TXPRECURSORINV (1'b0),
.TXQPIBIASEN (1'b0),
.TXQPISTRONGPDOWN (1'b0),
.TXQPIWEAKPUP (1'b0),
.CFGRESET (1'b0),
.GTTXRESET (txreset),
.PCSRSVDOUT (),
.TXUSERRDY (txuserrdy),
.GTRESETSEL (1'b0),
.RESETOVRD (1'b0),
.TXCHARDISPMODE (8'd0),
.TXCHARDISPVAL (8'd0),
.TXUSRCLK (txusrclk),
.TXUSRCLK2 (txusrclk2),
.TXELECIDLE (txelecidle),
.TXMARGIN (3'd0),
.TXRATE (3'd0),
.TXSWING (1'b0),
.TXPRBSFORCEERR (1'b0),
.TXDLYBYPASS (1'b1),
.TXDLYEN (1'b0),
.TXDLYHOLD (1'b0),
.TXDLYOVRDEN (1'b0),
.TXDLYSRESET (1'b0),
.TXDLYSRESETDONE (),
.TXDLYUPDOWN (1'b0),
.TXPHALIGN (1'b0),
.TXPHALIGNDONE (),
.TXPHALIGNEN (1'b0),
.TXPHDLYPD (1'b0),
.TXPHDLYRESET (1'b0),
.TXPHINIT (1'b0),
.TXPHINITDONE (),
.TXPHOVRDEN (1'b0),
.TXBUFSTATUS (),
.TXBUFDIFFCTRL (3'b100),
.TXDEEMPH (1'b0),
.TXDIFFCTRL (4'b1000),
.TXDIFFPD (1'b0),
.TXINHIBIT (1'b0),
.TXMAINCURSOR (7'b0000000),
.TXPISOPD (1'b0),
.TXDATA ({32'h0, txdata}),
.GTXTXN (txn),
.GTXTXP (txp),
.TXOUTCLK (txoutclk),
.TXOUTCLKFABRIC (),
.TXOUTCLKPCS (),
.TXOUTCLKSEL (3'b010),
.TXRATEDONE (),
.TXCHARISK ({7'b0, txcharisk}),
.TXGEARBOXREADY (),
.TXHEADER (3'd0),
.TXSEQUENCE (7'd0),
.TXSTARTSEQ (1'b0),
.TXPCSRESET (1'b0),
.TXPMARESET (1'b0),
.TXRESETDONE (txresetdone),
.TXCOMFINISH (),
.TXCOMINIT (txcominit),
.TXCOMSAS (1'b0),
.TXCOMWAKE (txcomwake),
.TXPDELECIDLEMODE (1'b0),
.TXPOLARITY (1'b0),
.TXDETECTRX (1'b0),
.TX8B10BBYPASS (8'd0),
.TXPRBSSEL (3'd0),
.TXQPISENN (),
.TXQPISENP ()/*,
.TXSYNCMODE (1'b0),
.TXSYNCALLIN (1'b0),
.TXSYNCIN (1'b0)*/
);
/*
* Interfaces
*/
assign DCMLOCKED_OUT = usrpll_locked;
assign PLLLKDET_OUT_N = cplllock;
assign rxn = RXN0_IN;
assign rxp = RXP0_IN;
assign TXN0_OUT = txn;
assign TXP0_OUT = txp;
assign cplllockdetclk = CLKIN_150;
assign drpclk = CLKIN_150;
assign LINKUP = linkup;
assign LINKUP_led = linkup_led;
assign rx_dataout = rxdata_out;
assign rx_charisk_out = rxcharisk_out;
assign rxelecidle_out = rxelecidle;
assign GEN2_led = 1'b0;
assign sata_user_clk = usrclk2;
endmodule
device/device_tasks.v deleted 100644 → 0
View file @ 680098f2
wire [31:0] phy2dev_data;
wire [3:0] phy2dev_charisk;
wire [3:0] phy2dev_err;
wire dev_clk;
wire dev_rst;
reg [31:0] dev2phy_data;
reg [3:0] dev2phy_charisk;
force dev.dev2phy_data =
force dev.dev2phy_charisk =
task
device/oob_ctrl_dev.v deleted 100644 → 0
View file @ 680098f2
/*******************************************************************************
* Module: oob_ctrl
* Date: 2015-07-11
* Author: Alexey
* Description: module to start oob sequences and to handle errors
*
* Copyright (c) 2015 Elphel, Inc.
* oob_ctrl.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* oob_ctrl.v file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`include "oob.v"
module oob_ctrl_dev #(
parameter DATA_BYTE_WIDTH = 4,
parameter CLK_SPEED_GRADE = 2 // 1 - 75 Mhz, 2 - 150Mhz, 4 - 300Mhz
)
(
// sata clk = usrclk2
input wire clk,
// reset oob
input wire rst,
// gtx is ready = all resets are done
input wire gtx_ready,
// oob responces
input wire rxcominitdet_in,
input wire rxcomwakedet_in,
input wire rxelecidle_in,
// oob issues
output wire txcominit,
output wire txcomwake,
output wire txelecidle,
// input data stream (if any data during OOB setting => ignored)
input wire [DATA_BYTE_WIDTH*8 - 1:0] txdata_in,
input wire [DATA_BYTE_WIDTH - 1:0] txcharisk_in,
// output data stream to gtx
output wire [DATA_BYTE_WIDTH*8 - 1:0] txdata_out,
output wire [DATA_BYTE_WIDTH - 1:0] txcharisk_out,
// input data from gtx
input wire [DATA_BYTE_WIDTH*8 - 1:0] rxdata_in,
input wire [DATA_BYTE_WIDTH - 1:0] rxcharisk_in,
// bypassed data from gtx
output wire [DATA_BYTE_WIDTH*8 - 1:0] rxdata_out,
output wire [DATA_BYTE_WIDTH - 1:0] rxcharisk_out,
// obvious
input wire rxbyteisaligned,
// shows if channel is ready
output wire phy_ready
);
// oob sequence needs to be issued
wire oob_start;
// connection established, all further data is valid
wire oob_done;
// doc p265, link is established after 3back-to-back non-ALIGNp
wire link_up;
wire link_down;
// the device itself sends cominit
wire cominit_req;
// allow to respond to cominit
wire cominit_allow;
// status information to handle by a control block if any exists
// incompatible host-device speed grades (host cannot lock to alignp)
wire oob_incompatible; // TODO
// timeout in an unexpected place
wire oob_error;
// noone responds to our cominits
wire oob_silence;
// obvious
wire oob_busy;
// for the resync sake
reg rxbyteisaligned_r;
reg rxbyteisaligned_rr;
always @ (posedge clk)
begin
rxbyteisaligned_rr <= rxbyteisaligned_r;
rxbyteisaligned_r <= rxbyteisaligned;
end
// 1 - link is up and running, 0 - probably not
reg link_state;
// 1 - connection is being established OR already established, 0 - is not
reg oob_state;
assign phy_ready = link_state & gtx_ready & rxbyteisaligned_rr;
always @ (posedge clk)
link_state <= (link_state | link_up) & ~link_down & ~rst;
always @ (posedge clk)
oob_state <= (oob_state | oob_start | cominit_req & cominit_allow) & ~oob_error & ~oob_silence & link_down & ~rst;
// decide when to issue oob: always when gtx is ready
assign oob_start = gtx_ready & ~oob_state & ~oob_busy;
// set line to idle state before if we're waiting for a device to answer AND while oob sequence
wire txelecidle_inner;
assign txelecidle = ~oob_state | txelecidle_inner;
// let devices always begin oob sequence, if only it's not a glitch
assign cominit_allow = cominit_req & link_state;
oob_dev #(
.DATA_BYTE_WIDTH (DATA_BYTE_WIDTH),
.CLK_SPEED_GRADE (CLK_SPEED_GRADE)
)
oob_dev
(
// sata clk = usrclk2
.clk (clk),
// reset oob
.rst (rst),
// oob responces
.rxcominitdet_in (rxcominitdet_in),
.rxcomwakedet_in (rxcomwakedet_in),
.rxelecidle_in (rxelecidle_in),
// oob issues
.txcominit (txcominit),
.txcomwake (txcomwake),
.txelecidle (txelecidle_inner),
// input data stream (if any data during OOB setting => ignored)
.txdata_in (txdata_in),
.txcharisk_in (txcharisk_in),
// output data stream to gtx
.txdata_out (txdata_out),
.txcharisk_out (txcharisk_out),
// input data from gtx
.rxdata_in (rxdata_in),
.rxcharisk_in (rxcharisk_in),
// bypassed data from gtx
.rxdata_out (rxdata_out),
.rxcharisk_out (rxcharisk_out),
// oob sequence needs to be issued
.oob_start (oob_start),
// connection established, all further data is valid
.oob_done (oob_done),
// doc p265, link is established after 3back-to-back non-ALIGNp
.link_up (link_up),
.link_down (link_down),
// the device itself sends cominit
.cominit_req (cominit_req),
// allow to respond to cominit
.cominit_allow (cominit_allow),
// status information to handle by a control block if any exists
// incompatible host-device speed grades (host cannot lock to alignp)
.oob_incompatible (oob_incompatible),
// timeout in an unexpected place
.oob_error (oob_error),
// noone responds to our cominits
.oob_silence (oob_silence),
// oob can't handle new start request
.oob_busy (oob_busy)
);
endmodule
device/sata_device.v
View file @ 340db2c6
......@@ -18,7 +18,7 @@
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`include "sata_phy_dev.v"
//`include "sata_phy_dev.v"
module sata_device(
input wire rst,
input wire RXN,
......
device/sata_phy_dev.v
View file @ 340db2c6
......@@ -18,7 +18,7 @@
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`include "oob_dev.v"
//`include "oob_dev.v"
module sata_phy_dev #(
parameter DATA_BYTE_WIDTH = 4
)
......
dma/axi_regs.v
View file @ 340db2c6
......@@ -18,8 +18,8 @@
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`include "axibram_read.v"
`include "axibram_write.v"
//`include "axibram_read.v"
//`include "axibram_write.v"
module axi_regs #(
parameter REGISTERS_CNT = 20
)
......
dma/sata_top.v
View file @ 340db2c6
......@@ -19,12 +19,12 @@
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
`include "axi_regs.v"
`include "dma_regs.v"
`include "sata_host.v"
`include "dma_adapter.v"
`include "dma_control.v"
`include "membridge.v"
//`include "axi_regs.v"
//`include "dma_regs.v"
//`include "sata_host.v"
//`include "dma_adapter.v"
//`include "dma_control.v"
//`include "membridge.v"
/*
* Takes commands from axi iface as a slave, transfers data with another axi iface as a master
*/
......
dma/send_dma.v deleted 100644 → 0
View file @ 680098f2
/*******************************************************************************
* Module: send_dma
* Date: 2015-07-11
* Author: Alexey
* Description: temporary interconnect to membridge testing purposes only
*
* Copyright (c) 2015 Elphel, Inc.
* send_dma.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* send_dma.v file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
/*
* The module is temporary
* It could make transactions from DMA data buffer to membridge and vice versa.
* Processes 1 transaction of 16 x 64bit-words at a time.
* Waits until 1 read or 1 write is completely done.
* After that it deasserts busy and is ready to process a new transaction.
*
* The whole purpose of a module as a system block is to be a buffer between
* a big dma data storage and axi interface. So it shall recieve data and control
* for 1 burst and pass it to axi.
*/
/*
* For debug only:
* DMA write:
* 0x0c: |mem[:] => use dbg registers as a source of dma data
* 0x10: addr of the buffer
* 0x14: size
* 0x18: burst len
* 0x1c: start dma
* 0x20-0x3c - data
*/
module send_dma #(
parameter REGISTERS_CNT = 20
)
(
input wire clk,
input wire rst,
// dbg iface
input wire [32*REGISTERS_CNT - 1:0] mem,
input wire dbg_mode,
output wire clrstart,
// cmd iface
input wire cmd_type, // 1 = wr, 0 = rd
input wire cmd_val, // issue a cmd
input wire [31:7] cmd_addr, // [2:0] - 64-bit (8-bytes) word offset, [6:3] - 16-words transfer offset
output wire cmd_busy, // no-pipelined cmd execution, 1 cmd at a time
// data iface
input wire [63:0] wr_data_in,
output wire wr_val_out,
output wire [63:0] rd_data_out,
input wire rd_val_in,
// membridge iface
output wire [7:0] cmd_ad,
output wire cmd_stb,
input wire [7:0] status_ad,
input wire status_rq,
output wire status_start,
input wire frame_start_chn,
input wire next_page_chn,
output wire cmd_wrmem,
output wire page_ready_chn,
output wire frame_done_chn,
output wire [15:0] line_unfinished_chn1,
input wire suspend_chn1,
output wire xfer_reset_page_rd,
output wire buf_wpage_nxt,
output wire buf_wr,
output wire [63:0] buf_wdata,
output wire xfer_reset_page_wr,
output wire buf_rpage_nxt,
output wire buf_rd,
input wire [63:0] buf_rdata,
// additinal wire to indicate if membridge recieved a packet
input wire rdata_done // = membridge.is_last_in_page & membridge.afi_rready;
);
// cmd handling
// if not busy and got cmd with val => cmd recieved, assert busy, start a respective algorithm
wire wr_start;
wire rd_start;
reg wr_done;
reg rd_done;
reg cmd_type_r;
reg cmd_addr_r;
reg cmd_val_r;
reg cmd_busy_r;
wire set_busy;
wire clr_busy;
assign set_busy = ~cmd_busy_r & cmd_val;
assign clr_busy = cmd_busy_r & (wr_done | rd_done)
always @ (posedge clk)
begin
cmd_type_r <= rst ? 1'b0 :
cmd_addr_r <= rst ? 1'b0 :
cmd_val_r <= rst ? 1'b0 :
cmd_busy_r <= rst ? 1'b0 : ~cmd_busy_r & cmd_val_r
end
/*
* Read/write state machine
* For better readability the state machine is splitted to two pieces:
* the first one is responsible only for the CMD WRITE case handling,
* the second one, respectively, for CMD READ
*
* Each fsm starts a membridge fsm, which, if being 1st time launched, sets up
* membridge's registers, or, if have been launched before, just programs read/write
* address.
*
* Current implementation is extremely slow, but simple and reliable
* After all other parts are implemented and this place occurs to be a bottleneck
* then replace it (and may be membridge too) with something more ... pipelined
*/
reg [1:0] rdwr_state;
// Get data from buffer
localparam READ_IDLE = 0;
localparam READ_ON = 2;
localparam READ_DATA = 3;
reg rd_reset_page;
reg rd_next_page;
reg rd_data
always @ (posedge clk)
if (rst)
begin
rd_state <= READ_IDLE;
rd_done <=
end
else
case (rst)
READ_IDLE:
begin
end
READ_ON:
begin
end
// Put data into buffer
localparam WRITE_IDLE = 0;
localparam WRITE_ON = 1;
reg wr_en;
reg wr_reset_page;
reg wr_next_page;
reg [63:0] wr_data;
reg [6:0] wr_page_offset;
reg wr_page_ready;
reg wr_val;
wire [31:0] dw0 = mem[32*9-1:32*8];
wire [31:0] dw1 = mem[32*10-1:32*9];
wire [31:0] dw2 = mem[32*11-1:32*10];
wire [31:0] dw3 = mem[32*12-1:32*11];
wire [6:0] wr_cnt_to_push;
wire wr_stop;
assign wr_cnt_to_push = 7'hf;
assign wr_stop = wr_page_offset == wr_cnt_to_push;
assign wr_val_in = wr_val;
assign wr_data_in = wr_data;
// assuming for now we write only pre-defined 16 64-bit words
always @ (posedge clk)
if (rst)
begin
wr_done <= 1'b0;
wr_page_offset <= 7'd0;
wr_val <= 1'b0;
wr_data <= 64'h0;
wr_next_page <= 1'b0;
wr_reset_page <= 1'b0;
wr_en <= 1'b0;
wr_page_ready <= 1'b0;
rdwr_state <= WRITE_IDLE;
end
else
case (wr_state)
WRITE_IDLE:
begin
wr_page_offset <= 7'd0;
wr_done <= 1'b0;
wr_val <= 1'b0;
wr_data <= 64'h0;
wr_next_page <= 1'b0;
wr_reset_page <= wr_start ? 1'b1 : 1'b0;
wr_en <= 1'b0;
wr_page_ready <= 1'b0;
rdwr_state <= wr_start ? WRITE_ON : WRITE_IDLE;
end
WRITE_ON:
begin
wr_done <= wr_stop ? 1'b1 : 1'b0;
wr_page_offset <= wr_page_offset + 1'b1;
wr_val <= 1'b1;
wr_data <= ~dbg_mode ? in_data :
wr_page_offset[1:0] == 2'b00 ? {dw0, 25'h0, wr_page_offset} :
wr_page_offset[1:0] == 2'b01 ? {dw1, 25'h0, wr_page_offset} :
wr_page_offset[1:0] == 2'b10 ? {dw2, 25'h0, wr_page_offset} :
{dw3, 25'h0, wr_page_offset};
wr_next_page <= wr_stop ? 1'b1 : 1'b0;
wr_reset_page <= 1'b0;
wr_en <= 1'b1;
wr_page_ready <= wr_stop ? 1'b1 : 1'b0;
rdwr_state <= wr_stop ? WRITE_IDLE : WRITE_ON;
end
default: // read is executed
begin
wr_done <= 1'b0;
wr_page_offset <= 7'd0;
wr_val <= 1'b0;
wr_data <= 64'h0;
wr_next_page <= 1'b0;
wr_reset_page <= 1'b0;
wr_en <= 1'b0;
wr_page_ready <= 1'b0;
rdwr_state <= rdwr_state;
end
endcase
// temporary assigments
assign status_start = 1'b0; // no need until status is used
assign cmd_wrmem = 1'b0; // for now only writing
assign xfer_reset_page_wr = 1'b0; // for now only writing
assign buf_rpage_nxt = 1'b0; // for now only writing
assign buf_rd = 1'b0; // for now only writing
assign xfer_reset_page_wr = 1'b0;
assign buf_wdata = wr_data;
assign buf_wr = wr_en;
assign buf_wpage_nxt = wr_next_page;
assign xfer_reset_page_rd = wr_reset_page;
assign page_ready_chn = cmd_wrmem ? 1'b0 : wr_page_ready;
assign frame_done_chn = 1'b1;
// compute membridge parameters to corresponding mem register
// dma fsm
// mode = 0
// width = 4
// size = 0x14
// start = 0
// lo_address = 0x10
// ctrl = 0x1c
// len = 0x18
localparam MEMBR_IDLE = 0;
localparam MEMBR_MODE = 1;
localparam MEMBR_WIDTH = 2;
localparam MEMBR_LEN = 3;
localparam MEMBR_START = 4;
localparam MEMBR_SIZE = 5;
localparam MEMBR_LOADDR = 6;
localparam MEMBR_CTRL = 7;
reg [32:0] membr_data;
reg [15:0] membr_addr;
reg membr_start;
reg membr_done;
reg [2:0] membr_state;
reg membr_setup; // indicates the first tick of the state
wire membr_inprocess;
wire dma_start;
assign dma_start = |mem[32*8-1:32*7];
assign clrstart = dma_start & membr_state == MEMBR_IDLE;
//assign wr_start = membr_state == MEMBR_CTRL;
always @ (posedge clk)
if (rst)
begin
membr_data <= 32'h0;
membr_addr <= 16'h0;
membr_start <= 1'b0;
membr_setup <= 1'b0;
membr_state <= MEMBR_IDLE;
end
else
case (membr_state)
MEMBR_IDLE:
begin
membr_data <= 32'h0;
membr_addr <= 16'h200;
membr_start <= dma_start ? 1'b1 : 1'b0;
membr_setup <= dma_start ? 1'b1 : 1'b0;
membr_state <= dma_start ? MEMBR_MODE : MEMBR_IDLE;
end
MEMBR_MODE:
begin
membr_data <= 32'h3;
membr_addr <= 16'h207;
membr_start <= membr_inprocess ? 1'b0 : 1'b1;
membr_setup <= membr_inprocess | membr_setup ? 1'b0 : 1'b1;
membr_state <= membr_inprocess | membr_setup ? MEMBR_MODE : MEMBR_WIDTH;
end
MEMBR_WIDTH:
begin
membr_data <= 32'h10;
membr_addr <= 16'h206;
membr_start <= membr_inprocess ? 1'b0 : 1'b1;
membr_setup <= membr_inprocess | membr_setup ? 1'b0 : 1'b1;
membr_state <= membr_inprocess | membr_setup ? MEMBR_WIDTH : MEMBR_LEN;
end
MEMBR_LEN:
begin
membr_data <= 32'h10;
membr_addr <= 16'h205;
membr_start <= membr_inprocess ? 1'b0 : 1'b1;
membr_setup <= membr_inprocess | membr_setup ? 1'b0 : 1'b1;
membr_state <= membr_inprocess | membr_setup ? MEMBR_LEN : MEMBR_START;
end
MEMBR_START:
begin
membr_data <= 32'h0;
membr_addr <= 16'h204;
membr_start <= membr_inprocess ? 1'b0 : 1'b1;
membr_setup <= membr_inprocess | membr_setup ? 1'b0 : 1'b1;
membr_state <= membr_inprocess | membr_setup ? MEMBR_START : MEMBR_SIZE;
end
MEMBR_SIZE:
begin
membr_data <= 32'h10;
membr_addr <= 16'h203;
membr_start <= membr_inprocess ? 1'b0 : 1'b1;
membr_setup <= membr_inprocess | membr_setup ? 1'b0 : 1'b1;
membr_state <= membr_inprocess | membr_setup ? MEMBR_SIZE : MEMBR_LOADDR;
end
MEMBR_LOADDR:
begin
membr_data <= mem[32*5-1:32*4];
membr_addr <= 16'h202;
membr_start <= membr_inprocess ? 1'b0 : 1'b1;
membr_setup <= membr_inprocess | membr_setup ? 1'b0 : 1'b1;
membr_state <= membr_inprocess | membr_setup ? MEMBR_LOADDR : MEMBR_CTRL;
end
MEMBR_CTRL:
begin
membr_data <= {28'h0000000, 4'b0011};
membr_addr <= 16'h200;
membr_start <= membr_inprocess ? 1'b0 : 1'b1;
membr_setup <= 1'b0;
membr_state <= membr_inprocess | membr_setup ? MEMBR_CTRL : MEMBR_IDLE;
end
default:
begin
membr_data <= 32'h0;
membr_addr <= 16'h0;
membr_start <= 1'b0;
membr_setup <= 1'b0;
membr_state <= MEMBR_IDLE;
end
endcase
// write to memridge registers fsm
localparam STATE_IDLE = 3'h0;
localparam STATE_CMD_0 = 3'h1;
localparam STATE_CMD_1 = 3'h2;
localparam STATE_DATA_0 = 3'h3;
localparam STATE_DATA_1 = 3'h4;
localparam STATE_DATA_2 = 3'h5;
localparam STATE_DATA_3 = 3'h6;
reg [2:0] state;
reg [7:0] out_ad;
reg out_stb;
assign membr_inprocess = state != STATE_IDLE;
assign cmd_ad = out_ad;
assign cmd_stb = out_stb;
always @ (posedge clk)
if (rst)
begin
membr_done <= 1'b0;
state <= STATE_IDLE;
out_ad <= 8'h0;
out_stb <= 1'b0;
end
else
case (state)
STATE_IDLE:
begin
membr_done <= 1'b0;
out_ad <= 8'h0;
out_stb <= 1'b0;
state <= membr_setup ? STATE_CMD_0 : STATE_IDLE;
end
STATE_CMD_0:
begin
membr_done <= 1'b0;
out_ad <= membr_addr[7:0];
out_stb <= 1'b1;
state <= STATE_CMD_1;
end
STATE_CMD_1:
begin
membr_done <= 1'b0;
out_ad <= membr_addr[15:8];
out_stb <= 1'b0;
state <= STATE_DATA_0;
end
STATE_DATA_0:
begin
membr_done <= 1'b0;
out_ad <= membr_data[7:0];
out_stb <= 1'b0;
state <= STATE_DATA_1;
end
STATE_DATA_1:
begin
membr_done <= 1'b0;
out_ad <= membr_data[15:8];
out_stb <= 1'b0;
state <= STATE_DATA_2;
end
STATE_DATA_2:
begin
membr_done <= 1'b0;
out_ad <= membr_data[23:16];
out_stb <= 1'b0;
state <= STATE_DATA_3;
end
STATE_DATA_3:
begin
membr_done <= 1'b0;
out_ad <= membr_data[31:24];
out_stb <= 1'b0;
state <= STATE_IDLE;
end
default:
begin
membr_done <= 1'b1;
out_ad <= 8'hff;
out_stb <= 1'b0;
state <= STATE_IDLE;
end
endcase
endmodule
dma/top.v
View file @ 340db2c6
......@@ -24,7 +24,7 @@
* what is called now 'axi_regs' and connect it
*/
`include "system_defines.vh"
`include "sata_top.v"
//`include "sata_top.v"
module top #(
`include "includes/x393_parameters.vh"
)
......
gtxe2_gpl @ c4c7e576
Subproject commit c4c7e57675cc07463b0c9c09937281652a60a6bf
host/gtx_wrap.v
View file @ 340db2c6
......@@ -18,10 +18,10 @@
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`include "gtx_8x10enc.v"
`include "gtx_10x8dec.v"
`include "gtx_comma_align.v"
`include "gtx_elastic.v"
//`include "gtx_8x10enc.v"
//`include "gtx_10x8dec.v"
//`include "gtx_comma_align.v"
//`include "gtx_elastic.v"
// All computations have been done in assumption of GTX interface being 20 bits wide!
module gtx_wrap #(
parameter DATA_BYTE_WIDTH = 4,
......@@ -391,7 +391,7 @@ else begin
end
endgenerate
GTXE2_CHANNEL #(
gtxe2_channel_wrapper #(
.SIM_RECEIVER_DETECT_PASS ("TRUE"),
.SIM_TX_EIDLE_DRIVE_LEVEL ("X"),
.SIM_RESET_SPEEDUP ("FALSE"),
......@@ -592,7 +592,7 @@ GTXE2_CHANNEL #(
.RX_DFE_XYD_CFG (13'b0000000000000),
.TX_PREDRIVER_MODE (1'b0)
)
gtx(
gtxe2_channel_wrapper(
.CPLLFBCLKLOST (),
.CPLLLOCK (cplllock),
.CPLLLOCKDETCLK (cplllockdetclk),
......
host/link.v
View file @ 340db2c6
......@@ -18,8 +18,8 @@
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`include "scrambler.v"
`include "crc.v"
//`include "scrambler.v"
//`include "crc.v"
module link #(
// 4 = dword. 4-bytes aligned data transfers TODO 2 = word - easy, 8 = qword - difficult
parameter DATA_BYTE_WIDTH = 4
......
host/oob.v
View file @ 340db2c6
......@@ -299,8 +299,8 @@ generate
else
if (DATA_BYTE_WIDTH == 8)
begin
assign detected_alignp = ~|(rxdata ^ {2{8'b01111011, 8'b01001010, 8'b01001010, 8'b10111100}}) & ~|(rxcharisk ^ 8'h11); // {D27.3, D10.2, D10.2, K28.5}
assign detected_syncp = ~|(rxdata ^ {2{8'b10110101, 8'b10110101, 8'b10010101, 8'b01111100}}) & ~|(rxcharisk ^ 8'h11); // {D21.5, D21.5, D21.4, K28.3}
assign detected_alignp = ~|(rxdata ^ {8'b01111011, 8'b01001010, 8'b01001010, 8'b10111100, 8'b01111011, 8'b01001010, 8'b01001010, 8'b10111100}) & ~|(rxcharisk ^ 8'h11); // {D27.3, D10.2, D10.2, K28.5}
assign detected_syncp = ~|(rxdata ^ {8'b10110101, 8'b10110101, 8'b10010101, 8'b01111100, 8'b10110101, 8'b10110101, 8'b10010101, 8'b01111100}) & ~|(rxcharisk ^ 8'h11); // {D21.5, D21.5, D21.4, K28.3}
end
else
begin
......@@ -381,7 +381,7 @@ generate
if (DATA_BYTE_WIDTH == 8)
begin
assign txcharisk_align = 8'h11;
assign txdata_align = {2{8'b01111011, 8'b01001010, 8'b01001010, 8'b10111100}}; // 2x{D27.3, D10.2, D10.2, K28.5}
assign txdata_align = {8'b01111011, 8'b01001010, 8'b01001010, 8'b10111100, 8'b01111011, 8'b01001010, 8'b01001010, 8'b10111100}; // 2x{D27.3, D10.2, D10.2, K28.5}
end
else
always @ (posedge clk)
......
host/oob_ctrl.v
View file @ 340db2c6
......@@ -18,7 +18,7 @@
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`include "oob.v"
//`include "oob.v"
module oob_ctrl #(
parameter DATA_BYTE_WIDTH = 4,
parameter CLK_SPEED_GRADE = 1 // 1 - 75 Mhz, 2 - 150Mhz, 4 - 300Mhz
......
host/sata_host.v
View file @ 340db2c6
......@@ -18,10 +18,10 @@
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`include "sata_phy.v"
`include "link.v"
`include "transport.v"
`include "command.v"
//`include "sata_phy.v"
//`include "link.v"
//`include "transport.v"
//`include "command.v"
module sata_host(
input wire extrst,
......
host/sata_phy.v
View file @ 340db2c6
......@@ -18,8 +18,8 @@
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`include "oob_ctrl.v"
`include "gtx_wrap.v"
//`include "oob_ctrl.v"
//`include "gtx_wrap.v"
module sata_phy #(
parameter DATA_BYTE_WIDTH = 4
)
......
simul/build deleted 100755 → 0
View file @ 680098f2
#!/bin/bash
LOGFILE_PATH="bld.log"
rm a.out
if [ "$SATA_PATH" == '' ]
then
export SATA_PATH=".."
fi
if [ "$UNISIMS_PATH" == '' ]
then
export UNISIMS_PATH="../x393/unisims"
fi
if [ "$HOST_PATH" == '' ]
then
export HOST_PATH="../host"
fi
if [ "$GTX_PATH" == '' ]
then
export GTX_PATH=$SATA_PATH
fi
#iverilog $SATA_PATH/tb/tb_top.v $SATA_PATH/x393/glbl.v $SATA_PATH/gtxe2_gpl/GTXE2_CHANNEL.v -I$SATA_PATH/device -I$SATA_PATH/host -I$SATA_PATH/dma -I$SATA_PATH/tb -I$SATA_PATH -I$SATA_PATH/x393/axi -I$SATA_PATH/x393 -I$SATA_PATH/x393/wrap -y$SATA_PATH/x393/util_modules -y$SATA_PATH/x393/wrap -y$UNISIMS_PATH -y$SATA_PATH/x393/memctrl -y$SATA_PATH/x393/axi -y$SATA_PATH/x393/simulation_modules $SATA_PATH/x393/simulation_modules/simul_axi_fifo_out.v -y$SATA_PATH/x393/ -D SIMULATION -D CHECKERS_ENABLED
iverilog $SATA_PATH/tb/tb_top.v $SATA_PATH/x393/glbl.v $SATA_PATH/gtxe2_gpl/GTXE2_CHANNEL.v -I$SATA_PATH/device -I$SATA_PATH/host -I$SATA_PATH/dma -I$SATA_PATH/tb -I$SATA_PATH -I$SATA_PATH/x393/axi -I$SATA_PATH/x393 -I$SATA_PATH/x393/wrap -y$SATA_PATH/x393/util_modules -y$SATA_PATH/x393/wrap -y$UNISIMS_PATH -y$SATA_PATH/x393/memctrl -y$SATA_PATH/x393/axi -y$SATA_PATH/x393/simulation_modules $SATA_PATH/x393/simulation_modules/simul_axi_fifo_out.v -y$SATA_PATH/x393/ -D SIMULATION -D CHECKERS_ENABLED
#iverilog $SATA_PATH/neat_phy.v $SATA_PATH/x393/glbl.v $SATA_PATH/gtxe2_gpl/GTXE2_CHANNEL.v $SATA_PATH/neat_oob.v -y$UNISIMS_PATH
#iverilog $SATA_PATH/tb/tb_top.v $SATA_PATH/x393/glbl.v -f opts -stb -sglbl $1 2>&1| tee $LOGFILE_PATH
#-y$SATA_PATH/x393/util_modules -I$SATA_PATH/x393/ -I$SATA_PATH/x393/axi/ $SATA_PATH/tb/tb_axiregs.v -I$SATA_PATH/ -I$SATA_PATH/tb/
simul/doall deleted 100755 → 0
View file @ 680098f2
#!/bin/bash
if [ ! -z "$1" ]
then
SAV_FILE=$1
else
SAV_FILE="save.gtkw"
fi
./build #-pfileline=1
./simul
if [ $? != 0 ]
then
echo "BUILD FAILED"
exit
else
gtkwave test.vcd $SAV_FILE &> waves.log &
fi
echo all done
simul/opts deleted 100644 → 0
View file @ 680098f2
-v ${SATA_PATH}/x393/simulation_modules/simul_axi_fifo_out.v
-y ${SATA_PATH}/x393/simulation_modules
-y ${SATA_PATH}/x393/memctrl
-y ${SATA_PATH}/x393/wrap
-y ${UNISIMS_PATH}/
-y ${SATA_PATH}/x393/util_modules
-v ${SATA_PATH}/x393/axi_hp_clk.v
+incdir+${SATA_PATH}/tb/
+incdir+${SATA_PATH}/x393/
+incdir+${SATA_PATH}/x393/axi/
+incdir+${SATA_PATH}/
simul/simul deleted 100755 → 0
View file @ 680098f2
#!/bin/bash
LOGFILE_PATH="sim.log"
/usr/local/bin/vvp a.out -v $1 #|tee $LOGFILE_PATH
#2>&1 | tee $LOGFILE_PATH
tb/tb_axiregs.v deleted 100644 → 0
View file @ 680098f2
/*******************************************************************************
* Module: tb
* Date: 2015-07-11
* Author: Alexey
* Description: testbench for axi_regs.v
*
* Copyright (c) 2015 Elphel, Inc.
* tb_axiregs.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* tb_axiregs.v file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ns
`include "axi_regs.v"
`include "test_axi_regs.v"
module tb();
initial #1 $display("HI THERE");
initial
begin
$dumpfile("test.vcd");
$dumpvars(0,tb);
end
wire ACLK; // AXI PS Master GP1 Clock , input
wire ARESETN; // AXI PS Master GP1 Reset, output
wire [31:0] ARADDR; // AXI PS Master GP1 ARADDR[31:0], output
wire ARVALID; // AXI PS Master GP1 ARVALID, output
wire ARREADY; // AXI PS Master GP1 ARREADY, input
wire [11:0] ARID; // AXI PS Master GP1 ARID[11:0], output
wire [1:0] ARLOCK; // AXI PS Master GP1 ARLOCK[1:0], output
wire [3:0] ARCACHE; // AXI PS Master GP1 ARCACHE[3:0], output
wire [2:0] ARPROT; // AXI PS Master GP1 ARPROT[2:0], output
wire [3:0] ARLEN; // AXI PS Master GP1 ARLEN[3:0], output
wire [1:0] ARSIZE; // AXI PS Master GP1 ARSIZE[1:0], output
wire [1:0] ARBURST; // AXI PS Master GP1 ARBURST[1:0], output
wire [3:0] ARQOS; // AXI PS Master GP1 ARQOS[3:0], output
wire [31:0] RDATA; // AXI PS Master GP1 RDATA[31:0], input
wire RVALID; // AXI PS Master GP1 RVALID, input
wire RREADY; // AXI PS Master GP1 RREADY, output
wire [11:0] RID; // AXI PS Master GP1 RID[11:0], input
wire RLAST; // AXI PS Master GP1 RLAST, input
wire [1:0] RRESP; // AXI PS Master GP1 RRESP[1:0], input
wire [31:0] AWADDR; // AXI PS Master GP1 AWADDR[31:0], output
wire AWVALID; // AXI PS Master GP1 AWVALID, output
wire AWREADY; // AXI PS Master GP1 AWREADY, input
wire [11:0] AWID; // AXI PS Master GP1 AWID[11:0], output
wire [1:0] AWLOCK; // AXI PS Master GP1 AWLOCK[1:0], output
wire [3:0] AWCACHE; // AXI PS Master GP1 AWCACHE[3:0], output
wire [2:0] AWPROT; // AXI PS Master GP1 AWPROT[2:0], output
wire [3:0] AWLEN; // AXI PS Master GP1 AWLEN[3:0], outpu:t
wire [1:0] AWSIZE; // AXI PS Master GP1 AWSIZE[1:0], output
wire [1:0] AWBURST; // AXI PS Master GP1 AWBURST[1:0], output
wire [3:0] AWQOS; // AXI PS Master GP1 AWQOS[3:0], output
wire [31:0] WDATA; // AXI PS Master GP1 WDATA[31:0], output
wire WVALID; // AXI PS Master GP1 WVALID, output
wire WREADY; // AXI PS Master GP1 WREADY, input
wire [11:0] WID; // AXI PS Master GP1 WID[11:0], output
wire WLAST; // AXI PS Master GP1 WLAST, output
wire [3:0] WSTRB; // AXI PS Master GP1 WSTRB[3:0], output
wire BVALID; // AXI PS Master GP1 BVALID, input
wire BREADY; // AXI PS Master GP1 BREADY, output
wire [11:0] BID; // AXI PS Master GP1 BID[11:0], input
wire [1:0] BRESP; // AXI PS Master GP1 BRESP[1:0], input
/*
axibram_write dut(
.aclk (ACLK),
.rst (~ARESETN),
.awaddr (AWADDR),
.awvalid (AWVALID),
.awready (AWREADY),
.awid (AWID),
.awlen (AWLEN),
.awsize (AWSIZE),
.awburst (AWBURST),
.wdata (WDATA),
.wvalid (WVALID),
.wready (WREADY),
.wid (WID),
.wlast (WLAST),
.wstb (WSTRB),
.bvalid (BVALID),
.bready (BREADY),
.bid (BID),
.bresp (BRESP),
.pre_awaddr (),
.start_burst (),
.dev_ready (1'b1),
.bram_wclk (),
.bram_waddr (),
.bram_wen (),
.bram_wstb (),
.bram_wdata ()
);
axibram_read dut2(
.aclk (ACLK),
.rst (~ARESETN),
.araddr (ARADDR),
.arvalid (ARVALID),
.arready (ARREADY),
.arid (ARID),
.arlen (ARLEN),
.arsize (ARSIZE),
.arburst (ARBURST),
.rdata (RDATA),
.rvalid (RVALID),
.rready (RREADY),
.rid (RID),
.rlast (RLAST),
.rresp (RRESP),
.pre_araddr (),
.start_burst (),
.dev_ready (1'b1),
.bram_rclk (),
.bram_raddr (),
.bram_ren (bram_ren),
.bram_regen (),
.bram_rdata (bram_ren ? 32'hdeadbeef : 0)
);
*/
axi_regs dut(
.ACLK (ACLK),
.ARESETN (ARESETN),
.ARADDR (ARADDR),
.ARVALID (ARVALID),
.ARREADY (ARREADY),
.ARID (ARID),
.ARLOCK (ARLOCK),
.ARCACHE (ARCACHE),
.ARPROT (ARPROT),
.ARLEN (ARLEN),
.ARSIZE (ARSIZE),
.ARBURST (ARBURST),
.ARQOS (ARQOS),
.RDATA (RDATA),
.RVALID (RVALID),
.RREADY (RREADY),
.RID (RID),
.RLAST (RLAST),
.RRESP (RRESP),
.AWADDR (AWADDR),
.AWVALID (AWVALID),
.AWREADY (AWREADY),
.AWID (AWID),
.AWLOCK (AWLOCK),
.AWCACHE (AWCACHE),
.AWPROT (AWPROT),
.AWLEN (AWLEN),
.AWSIZE (AWSIZE),
.AWBURST (AWBURST),
.AWQOS (AWQOS),
.WDATA (WDATA),
.WVALID (WVALID),
.WREADY (WREADY),
.WID (WID),
.WLAST (WLAST),
.WSTRB (WSTRB),
.BVALID (BVALID),
.BREADY (BREADY),
.BID (BID),
.BRESP (BRESP)
);
test_axi_regs test(
.ACLK (ACLK),
.ARESETN (ARESETN),
.ARADDR (ARADDR),
.ARVALID (ARVALID),
.ARREADY (ARREADY),
.ARID (ARID),
.ARLOCK (ARLOCK),
.ARCACHE (ARCACHE),
.ARPROT (ARPROT),
.ARLEN (ARLEN),
.ARSIZE (ARSIZE),
.ARBURST (ARBURST),
.ARQOS (ARQOS),
.RDATA (RDATA),
.RVALID (RVALID),
.RREADY (RREADY),
.RID (RID),
.RLAST (RLAST),
.RRESP (RRESP),
.AWADDR (AWADDR),
.AWVALID (AWVALID),
.AWREADY (AWREADY),
.AWID (AWID),
.AWLOCK (AWLOCK),
.AWCACHE (AWCACHE),
.AWPROT (AWPROT),
.AWLEN (AWLEN),
.AWSIZE (AWSIZE),
.AWBURST (AWBURST),
.AWQOS (AWQOS),
.WDATA (WDATA),
.WVALID (WVALID),
.WREADY (WREADY),
.WID (WID),
.WLAST (WLAST),
.WSTRB (WSTRB),
.BVALID (BVALID),
.BREADY (BREADY),
.BID (BID),
.BRESP (BRESP)
);
endmodule
tb/tb_top.v
View file @ 340db2c6
......@@ -18,12 +18,17 @@
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
// set of global defines
`define SIMULATION
`define CHECKERS_ENABLED
`define OPEN_SOURCE_ONLY
/*
* using x393_testbench01.tf style, contains a lot of copy-pasted code from there
*/
`timescale 1ns/1ps
`include "top.v"
`include "sata_device.v"
//`include "top.v"
//`include "sata_device.v"
module tb #(
`include "includes/x393_parameters.vh" // SuppressThisWarning VEditor - not used
......@@ -31,10 +36,16 @@ module tb #(
)
(
);
`ifdef IVERILOG
`include "IVERILOG_INCLUDE.v"
`else // IVERILOG
parameter lxtname = "x393.lxt";
`endif // IVERILOG
initial #1 $display("HI THERE");
initial
begin
$dumpfile("test.vcd");
$dumpfile(lxtname);
$dumpvars(0,tb);
end
......
tb/test_axi_regs.v deleted 100644 → 0
View file @ 680098f2
/*******************************************************************************
* Module: test_axi_regs
* Date: 2015-07-11
* Author: Alexey
* Description: test generator for axi_regs.v
*
* Copyright (c) 2015 Elphel, Inc.
* test_axi_regs.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* test_axi_regs.v file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
module test_axi_regs(
output reg ACLK,
output reg ARESETN,
// AXI PS Master GP1: Read Address
output reg [31:0] ARADDR,
output reg ARVALID,
input wire ARREADY,
output reg [11:0] ARID,
output reg [1:0] ARLOCK,
output reg [3:0] ARCACHE,
output reg [2:0] ARPROT,
output reg [3:0] ARLEN,
output reg [1:0] ARSIZE,
output reg [1:0] ARBURST,
output reg [3:0] ARQOS,
// AXI PS Master GP1: Read Data
input wire [31:0] RDATA,
input wire RVALID,
output reg RREADY,
input wire [11:0] RID,
input wire RLAST,
input wire [1:0] RRESP,
// AXI PS Master GP1: Write Address
output reg [31:0] AWADDR,
output reg AWVALID,
input wire AWREADY,
output reg [11:0] AWID,
output reg [1:0] AWLOCK,
output reg [3:0] AWCACHE,
output reg [2:0] AWPROT,
output reg [3:0] AWLEN,
output reg [1:0] AWSIZE,
output reg [1:0] AWBURST,
output reg [3:0] AWQOS,
// AXI PS Master GP1: Write Data
output reg [31:0] WDATA,
output reg WVALID,
input wire WREADY,
output reg [11:0] WID,
output reg WLAST,
output reg [3:0] WSTRB,
// AXI PS Master GP1: Write Responce
input wire BVALID,
output reg BREADY,
input wire [11:0] BID,
input wire [1:0] BRESP
);
// finish
initial #5000 $finish;
// clock
initial
ACLK = 0;
always #5
ACLK = ~ACLK;
// reset
initial
begin
#50;
ARESETN <= 1'b1;
#50;
ARESETN <= 1'b0;
#50;
ARESETN <= 1'b1;
end
// Trying to write a word
initial
begin
ARVALID <= 1'b0;
ARADDR <= 1'b0;
ARID <= 1'b0;
ARLOCK <= 1'b0;
ARCACHE <= 1'b0;
ARPROT <= 1'b0;
ARLEN <= 1'b0;
ARSIZE <= 1'b0;
ARBURST <= 1'b0;
RREADY <= 1'b0;
AWVALID <= 1'b0;
AWADDR <= 1'b0;
AWID <= 1'b0;
AWLOCK <= 1'b0;
AWCACHE <= 1'b0;
AWPROT <= 1'b0;
AWLEN <= 1'b0;
AWSIZE <= 1'b0;
AWBURST <= 1'b0;
WVALID <= 1'b0;
WID <= 1'b0;
WSTRB <= 1'b0;
#220;
repeat (10)
@ (posedge ACLK);
AWVALID <= 1'b1;
AWADDR <= 32'h5;
AWID <= 1'b0;
AWLOCK <= 1'b0;
AWCACHE <= 1'b0;
AWPROT <= 1'b0;
AWLEN <= 1'b0;
AWSIZE <= 2'b10;
AWBURST <= 1'b0;
if (AWREADY == 1'b0)
@ (posedge AWREADY);
@ (posedge ACLK);
AWVALID <= 1'b0;
WDATA <= 32'hdeadbeef;
WVALID <= 1'b1;
WSTRB <= 4'b1011;
WID <= 12'h123;
if (WREADY == 1'b0)
@ (posedge WREADY);
@ (posedge ACLK);
WVALID <= 1'b0;
repeat (10)
@ (posedge ACLK);
// Trying to read a word
#170;
repeat (10)
@ (posedge ACLK);
ARADDR <= 32'h5;
ARVALID <= 1'b1;
ARID <= 1'b0;
ARLOCK <= 1'b0;
ARCACHE <= 1'b0;
ARPROT <= 1'b0;
ARLEN <= 1'b0;
ARSIZE <= 1'b0;
ARBURST <= 1'b0;
if (ARREADY == 1'b0)
@ (posedge ARREADY);
@ (posedge ACLK);
ARVALID <= 1'b0;
RREADY <= 1'b1;
if (RVALID == 1'b0)
@ (posedge RVALID);
@ (posedge ACLK);
RREADY <= 1'b0;
end
*/
// Simulation modules
simul_axi_master_rdaddr
#(
.ID_WIDTH(12),
.ADDRESS_WIDTH(32),
.LATENCY(AXI_RDADDR_LATENCY), // minimal delay between inout and output ( 0 - next cycle)
.DEPTH(8), // maximal number of commands in FIFO
.DATA_DELAY(3.5),
.VALID_DELAY(4.0)
) simul_axi_master_rdaddr_i (
.clk(CLK),
.reset(RST),
.arid_in(ARID_IN[11:0]),
.araddr_in(ARADDR_IN[31:0]),
.arlen_in(ARLEN_IN[3:0]),
.arsize_in(ARSIZE_IN[2:0]),
.arburst_in(ARBURST_IN[1:0]),
.arcache_in(4'b0),
.arprot_in(3'b0), // .arprot_in(2'b0),
.arid(arid[11:0]),
.araddr(araddr[31:0]),
.arlen(arlen[3:0]),
.arsize(arsize[2:0]),
.arburst(arburst[1:0]),
.arcache(arcache[3:0]),
.arprot(arprot[2:0]),
.arvalid(arvalid),
.arready(arready),
.set_cmd(AR_SET_CMD), // latch all other input data at posedge of clock
.ready(AR_READY) // command/data FIFO can accept command
);
simul_axi_master_wraddr
#(
.ID_WIDTH(12),
.ADDRESS_WIDTH(32),
.LATENCY(AXI_WRADDR_LATENCY), // minimal delay between inout and output ( 0 - next cycle)
.DEPTH(8), // maximal number of commands in FIFO
.DATA_DELAY(3.5),
.VALID_DELAY(4.0)
) simul_axi_master_wraddr_i (
.clk(CLK),
.reset(RST),
.awid_in(AWID_IN[11:0]),
.awaddr_in(AWADDR_IN[31:0]),
.awlen_in(AWLEN_IN[3:0]),
.awsize_in(AWSIZE_IN[2:0]),
.awburst_in(AWBURST_IN[1:0]),
.awcache_in(4'b0),
.awprot_in(3'b0), //.awprot_in(2'b0),
.awid(awid[11:0]),
.awaddr(awaddr[31:0]),
.awlen(awlen[3:0]),
.awsize(awsize[2:0]),
.awburst(awburst[1:0]),
.awcache(awcache[3:0]),
.awprot(awprot[2:0]),
.awvalid(awvalid),
.awready(awready),
.set_cmd(AW_SET_CMD), // latch all other input data at posedge of clock
.ready(AW_READY) // command/data FIFO can accept command
);
simul_axi_master_wdata
#(
.ID_WIDTH(12),
.DATA_WIDTH(32),
.WSTB_WIDTH(4),
.LATENCY(AXI_WRDATA_LATENCY), // minimal delay between inout and output ( 0 - next cycle)
.DEPTH(8), // maximal number of commands in FIFO
.DATA_DELAY(3.2),
.VALID_DELAY(3.6)
) simul_axi_master_wdata_i (
.clk(CLK),
.reset(RST),
.wid_in(WID_IN[11:0]),
.wdata_in(WDATA_IN[31:0]),
.wstrb_in(WSTRB_IN[3:0]),
.wlast_in(WLAST_IN),
.wid(wid[11:0]),
.wdata(wdata[31:0]),
.wstrb(wstrb[3:0]),
.wlast(wlast),
.wvalid(wvalid),
.wready(wready),
.set_cmd(W_SET_CMD), // latch all other input data at posedge of clock
.ready(W_READY) // command/data FIFO can accept command
);
simul_axi_slow_ready simul_axi_slow_ready_read_i(
.clk(CLK),
.reset(RST), //input reset,
.delay(RD_LAG), //input [3:0] delay,
.valid(rvalid), // input valid,
.ready(rready) //output ready
);
simul_axi_slow_ready simul_axi_slow_ready_write_resp_i(
.clk(CLK),
.reset(RST), //input reset,
.delay(B_LAG), //input [3:0] delay,
.valid(bvalid), // input ADDRESS_NUMBER+2:0 valid,
.ready(bready) //output ready
);
simul_axi_read #(
.ADDRESS_WIDTH(SIMUL_AXI_READ_WIDTH)
) simul_axi_read_i(
.clk(CLK),
.reset(RST),
.last(rlast),
.data_stb(rstb),
.raddr(ARADDR_IN[SIMUL_AXI_READ_WIDTH+1:2]),
.rlen(ARLEN_IN),
.rcmd(AR_SET_CMD),
.addr_out(SIMUL_AXI_ADDR_W[SIMUL_AXI_READ_WIDTH-1:0]),
.burst(), // burst in progress - just debug
.err_out()); // data last does not match predicted or FIFO over/under run - just debug
endmodule
wrapper/GTXE2_GPL.v 0 → 100644
View file @ 340db2c6
This source diff could not be displayed because it is too large. You can view the blob instead.
wrapper/gtxe2_channel_wrapper.v 0 → 100644
View file @ 340db2c6
/*******************************************************************************
* Module: gtxe2_channel_wrapper
* Date: 2015-09-07
* Author: Alexey
* Description: wrapper to switch between closed unisims primitive and open-source one
*
* Copyright (c) 2015 Elphel, Inc.
* GTXE2_GPL.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* GTXE2_GPL.v file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
module gtxe2_channel_wrapper(
// clocking ports, UG476 p.37
input [2:0] CPLLREFCLKSEL,
input GTGREFCLK,
input GTNORTHREFCLK0,
input GTNORTHREFCLK1,
input GTREFCLK0,
input GTREFCLK1,
input GTSOUTHREFCLK0,
input GTSOUTHREFCLK1,
input [1:0] RXSYSCLKSEL,
input [1:0] TXSYSCLKSEL,
output GTREFCLKMONITOR,
// CPLL Ports, UG476 p.48
input CPLLLOCKDETCLK,
input CPLLLOCKEN,
input CPLLPD,
input CPLLRESET,
output CPLLFBCLKLOST,
output CPLLLOCK,
output CPLLREFCLKLOST,
output TSTOUT,
input GTRSVD,
input PCSRSVDIN,
input PCSRSVDIN2,
input PMARSVDIN,
input PMARSVDIN2,
input TSTIN,
// Reset Mode ports, ug476 p.62
input GTRESETSEL,
input RESETOVRD,
// TX Reset ports, ug476 p.65
input CFGRESET,
input GTTXRESET,
input TXPCSRESET,
input TXPMARESET,
output TXRESETDONE,
input TXUSERRDY,
output PCSRSVDOUT,
// RX Reset ports, UG476 p.73
input GTRXRESET,
input RXPMARESET,
input RXCDRRESET,
input RXCDRFREQRESET,
input RXDFELPMRESET,
input EYESCANRESET,
input RXPCSRESET,
input RXBUFRESET,
input RXUSERRDY,
output RXRESETDONE,
input RXOOBRESET,
// Power Down ports, ug476 p.88
input [1:0] RXPD,
input [1:0] TXPD,
input TXPDELECIDLEMODE,
input TXPHDLYPD,
input RXPHDLYPD,
// Loopback ports, ug476 p.91
input [2:0] LOOPBACK,
// Dynamic Reconfiguration Port, ug476 p.92
input [8:0] DRPADDR,
input DRPCLK,
input [15:0] DRPDI,
output [15:0] DRPDO,
input DRPEN,
output DRPRDY,
input DRPWE,
// Digital Monitor Ports, ug476 p.95
input [3:0] CLKRSVD,
output [7:0] DMONITOROUT,
// TX Interface Ports, ug476 p.110
input [7:0] TXCHARDISPMODE,
input [7:0] TXCHARDISPVAL,
input [63:0] TXDATA,
input TXUSRCLK,
input TXUSRCLK2,
// TX 8B/10B encoder ports, ug476 p.118
input [7:0] TX8B10BBYPASS,
input TX8B10BEN,
input [7:0] TXCHARISK,
// TX Gearbox ports, ug476 p.122
output TXGEARBOXREADY,
input [2:0] TXHEADER,
input [6:0] TXSEQUENCE,
input TXSTARTSEQ,
// TX BUffer Ports, ug476 p.134
output [1:0] TXBUFSTATUS,
// TX Buffer Bypass Ports, ug476 p.136
input TXDLYSRESET,
input TXPHALIGN,
input TXPHALIGNEN,
input TXPHINIT,
input TXPHOVRDEN,
input TXPHDLYRESET,
input TXDLYBYPASS,
input TXDLYEN,
input TXDLYOVRDEN,
input TXPHDLYTSTCLK,
input TXDLYHOLD,
input TXDLYUPDOWN,
output TXPHALIGNDONE,
output TXPHINITDONE,
output TXDLYSRESETDONE,
input TXSYNCMODE,
input TXSYNCALLIN,
input TXSYNCIN,
output TXSYNCOUT,
output TXSYNCDONE,
// TX Pattern Generator, ug476 p.147
input [2:0] TXPRBSSEL,
input TXPRBSFORCEERR,
// TX Polarity Control Ports, ug476 p.149
input TXPOLARITY,
// TX Fabric Clock Output Control Ports, ug476 p.152
input [2:0] TXOUTCLKSEL,
input [2:0] TXRATE,
output TXOUTCLKFABRIC,
output TXOUTCLK,
output TXOUTCLKPCS,
output TXRATEDONE,
// TX Phase Interpolator PPM Controller Ports, ug476 p.154
// GTH only
/* input TXPIPPMEN,
input TXPIPPMOVRDEN,
input TXPIPPMSEL,
input TXPIPPMPD,
input [4:0] TXPIPPMSTEPSIZE,*/
// TX Configurable Driver Ports, ug476 p.156
input [2:0] TXBUFDIFFCTRL,
input TXDEEMPH,
input [3:0] TXDIFFCTRL,
input TXELECIDLE,
input TXINHIBIT,
input [6:0] TXMAINCURSOR,
input [2:0] TXMARGIN,
input TXQPIBIASEN,
output TXQPISENN,
output TXQPISENP,
input TXQPISTRONGPDOWN,
input TXQPIWEAKPUP,
input [4:0] TXPOSTCURSOR,
input TXPOSTCURSORINV,
input [4:0] TXPRECURSOR,
input TXPRECURSORINV,
input TXSWING,
input TXDIFFPD,
input TXPISOPD,
// TX Receiver Detection Ports, ug476 p.165
input TXDETECTRX,
output PHYSTATUS,
output [2:0] RXSTATUS,
// TX OOB Signaling Ports, ug476 p.166
output TXCOMFINISH,
input TXCOMINIT,
input TXCOMSAS,
input TXCOMWAKE,
// RX AFE Ports, ug476 p.171
output RXQPISENN,
output RXQPISENP,
input RXQPIEN,
// RX OOB Signaling Ports, ug476 p.178
input [1:0] RXELECIDLEMODE,
output RXELECIDLE,
output RXCOMINITDET,
output RXCOMSASDET,
output RXCOMWAKEDET,
// RX Equalizer Ports, ug476 p.189
input RXLPMEN,
input RXOSHOLD,
input RXOSOVRDEN,
input RXLPMLFHOLD,
input RXLPMLFKLOVRDEN,
input RXLPMHFHOLD,
input RXLPMHFOVRDEN,
input RXDFEAGCHOLD,
input RXDFEAGCOVRDEN,
input RXDFELFHOLD,
input RXDFELFOVRDEN,
input RXDFEUTHOLD,
input RXDFEUTOVRDEN,
input RXDFEVPHOLD,
input RXDFEVPOVRDEN,
input RXDFETAP2HOLD,
input RXDFETAP2OVRDEN,
input RXDFETAP3HOLD,
input RXDFETAP3OVRDEN,
input RXDFETAP4HOLD,
input RXDFETAP4OVRDEN,
input RXDFETAP5HOLD,
input RXDFETAP5OVRDEN,
input RXDFECM1EN,
input RXDFEXYDHOLD,
input RXDFEXYDOVRDEN,
input RXDFEXYDEN,
input [1:0] RXMONITORSEL,
output [6:0] RXMONITOROUT,
// CDR Ports, ug476 p.202
input RXCDRHOLD,
input RXCDROVRDEN,
input RXCDRRESETRSV,
input [2:0] RXRATE,
output RXCDRLOCK,
// RX Fabric Clock Output Control Ports, ug476 p.213
input [2:0] RXOUTCLKSEL,
output RXOUTCLKFABRIC,
output RXOUTCLK,
output RXOUTCLKPCS,
output RXRATEDONE,
input RXDLYBYPASS,
// RX Margin Analysis Ports, ug476 p.220
output EYESCANDATAERROR,
input EYESCANTRIGGER,
input EYESCANMODE,
// RX Polarity Control Ports, ug476 p.224
input RXPOLARITY,
// Pattern Checker Ports, ug476 p.225
input RXPRBSCNTRESET,
input [2:0] RXPRBSSEL,
output RXPRBSERR,
// RX Byte and Word Alignment Ports, ug476 p.233
output RXBYTEISALIGNED,
output RXBYTEREALIGN,
output RXCOMMADET,
input RXCOMMADETEN,
input RXPCOMMAALIGNEN,
input RXMCOMMAALIGNEN,
input RXSLIDE,
// RX 8B/10B Decoder Ports, ug476 p.241
input RX8B10BEN,
output [7:0] RXCHARISCOMMA,
output [7:0] RXCHARISK,
output [7:0] RXDISPERR,
output [7:0] RXNOTINTABLE,
input SETERRSTATUS,
// RX Buffer Bypass Ports, ug476 p.244
input RXPHDLYRESET,
input RXPHALIGN,
input RXPHALIGNEN,
input RXPHOVRDEN,
input RXDLYSRESET,
input RXDLYEN,
input RXDLYOVRDEN,
input RXDDIEN,
output RXPHALIGNDONE,
output RXPHMONITOR,
output RXPHSLIPMONITOR,
output RXDLYSRESETDONE,
// RX Buffer Ports, ug476 p.259
output [2:0] RXBUFSTATUS,
// RX Clock Correction Ports, ug476 p.263
output [1:0] RXCLKCORCNT,
// RX Channel Bonding Ports, ug476 p.274
output RXCHANBONDSEQ,
output RXCHANISALIGNED,
output RXCHANREALIGN,
input [4:0] RXCHBONDI,
output [4:0] RXCHBONDO,
input [2:0] RXCHBONDLEVEL,
input RXCHBONDMASTER,
input RXCHBONDSLAVE,
input RXCHBONDEN,
// RX Gearbox Ports, ug476 p.285
output RXDATAVALID,
input RXGEARBOXSLIP,
output [2:0] RXHEADER,
output RXHEADERVALID,
output RXSTARTOFSEQ,
// FPGA RX Interface Ports, ug476 p.299
output [63:0] RXDATA,
input RXUSRCLK,
input RXUSRCLK2,
// ug476, p.323
output RXVALID,
// for correct clocking scheme in case of multilane structure
input QPLLCLK,
input QPLLREFCLK,
// Diffpairs
input GTXRXP,
input GTXRXN,
output GTXTXN,
output GTXTXP
);
// simulation common attributes, UG476 p.28
parameter SIM_RESET_SPEEDUP = "TRUE";
parameter SIM_CPLLREFCLK_SEL = 3'b001;
parameter SIM_RECEIVER_DETECT_PASS = "TRUE";
parameter SIM_TX_EIDLE_DRIVE_LEVEL = "X";
parameter SIM_VERSION = "1.0";
// Clocking Atributes, UG476 p.38
parameter OUTREFCLK_SEL_INV = 1'b0;
// CPLL Attributes, UG476 p.49
parameter CPLL_CFG = 24'h0;
parameter CPLL_FBDIV = 4;
parameter CPLL_FBDIV_45 = 5;
parameter CPLL_INIT_CFG = 24'h0;
parameter CPLL_LOCK_CFG = 16'h0;
parameter CPLL_REFCLK_DIV = 1;
parameter RXOUT_DIV = 2;
parameter TXOUT_DIV = 2;
parameter SATA_CPLL_CFG = "VCO_3000MHZ";
parameter PMA_RSV3 = 2'b00;
// TX Initialization and Reset Attributes, ug476 p.66
parameter TXPCSRESET_TIME = 5'b00001;
parameter TXPMARESET_TIME = 5'b00001;
// RX Initialization and Reset Attributes, UG476 p.75
parameter RXPMARESET_TIME = 5'h0;
parameter RXCDRPHRESET_TIME = 5'h0;
parameter RXCDRFREQRESET_TIME = 5'h0;
parameter RXDFELPMRESET_TIME = 7'h0;
parameter RXISCANRESET_TIME = 7'h0;
parameter RXPCSRESET_TIME = 5'h0;
parameter RXBUFRESET_TIME = 5'h0;
// Power Down attributes, ug476 p.88
parameter PD_TRANS_TIME_FROM_P2 = 12'h0;
parameter PD_TRANS_TIME_NONE_P2 = 8'h0;
parameter PD_TRANS_TIME_TO_P2 = 8'h0;
parameter TRANS_TIME_RATE = 8'h0;
parameter RX_CLKMUX_PD = 1'b0;
parameter TX_CLKMUX_PD = 1'b0;
// GTX Digital Monitor Attributes, ug476 p.96
parameter DMONITOR_CFG = 24'h008101;
// TX Interface attributes, ug476 p.111
parameter TX_DATA_WIDTH = 20;
parameter TX_INT_DATAWIDTH = 0;
// TX Gearbox Attributes, ug476 p.121
parameter GEARBOX_MODE = 3'h0;
parameter TXGEARBOX_EN = "FALSE";
// TX BUffer Attributes, ug476 p.134
parameter TXBUF_EN = "TRUE";
// TX Bypass buffer, ug476 p.138
parameter TX_XCLK_SEL = "TXOUT";
parameter TXPH_CFG = 16'h0;
parameter TXPH_MONITOR_SEL = 5'h0;
parameter TXPHDLY_CFG = 24'h0;
parameter TXDLY_CFG = 16'h0;
parameter TXDLY_LCFG = 9'h0;
parameter TXDLY_TAP_CFG = 16'h0;
parameter TXSYNC_MULTILANE = 1'b0;
parameter TXSYNC_SKIP_DA = 1'b0;
parameter TXSYNC_OVRD = 1'b1;
parameter LOOPBACK_CFG = 1'b0;
// TX Pattern Generator, ug476 p.147
parameter RXPRBS_ERR_LOOPBACK = 1'b0;
// TX Fabric Clock Output Control Attributes, ug476 p. 153
parameter TXBUF_RESET_ON_RATE_CHANGE = "TRUE";
// TX Phase Interpolator PPM Controller Attributes, ug476 p.155
// GTH only
/*parameter TXPI_SYNCFREQ_PPM = 3'b001;
parameter TXPI_PPM_CFG = 8'd0;
parameter TXPI_INVSTROBE_SEL = 1'b0;
parameter TXPI_GREY_SEL = 1'b0;
parameter TXPI_PPMCLK_SEL = "12345";*/
// TX Configurable Driver Attributes, ug476 p.162
parameter TX_DEEMPH0 = 5'b10100;
parameter TX_DEEMPH1 = 5'b01101;
parameter TX_DRIVE_MODE = "DIRECT";
parameter TX_MAINCURSOR_SEL = 1'b0;
parameter TX_MARGIN_FULL_0 = 7'b0;
parameter TX_MARGIN_FULL_1 = 7'b0;
parameter TX_MARGIN_FULL_2 = 7'b0;
parameter TX_MARGIN_FULL_3 = 7'b0;
parameter TX_MARGIN_FULL_4 = 7'b0;
parameter TX_MARGIN_LOW_0 = 7'b0;
parameter TX_MARGIN_LOW_1 = 7'b0;
parameter TX_MARGIN_LOW_2 = 7'b0;
parameter TX_MARGIN_LOW_3 = 7'b0;
parameter TX_MARGIN_LOW_4 = 7'b0;
parameter TX_PREDRIVER_MODE = 1'b0;
parameter TX_QPI_STATUS_EN = 1'b0;
parameter TX_EIDLE_ASSERT_DELAY = 3'b110;
parameter TX_EIDLE_DEASSERT_DELAY = 3'b100;
parameter TX_LOOPBACK_DRIVE_HIZ = "FALSE";
// TX Receiver Detection Attributes, ug476 p.165
parameter TX_RXDETECT_CFG = 14'h0;
parameter TX_RXDETECT_REF = 3'h0;
// TX OOB Signaling Attributes
parameter SATA_BURST_SEQ_LEN = 4'b0101;
// RX AFE Attributes, ug476 p.171
parameter RX_CM_SEL = 2'b11;
parameter TERM_RCAL_CFG = 5'b0;
parameter TERM_RCAL_OVRD = 1'b0;
parameter RX_CM_TRIM = 3'b010;
// RX OOB Signaling Attributes, ug476 p.179
parameter PCS_RSVD_ATTR = 48'h0100; // oob is up
parameter RXOOB_CFG = 7'b0000110;
parameter SATA_BURST_VAL = 3'b110;
parameter SATA_EIDLE_VAL = 3'b110;
parameter SAS_MIN_COM = 36;
parameter SATA_MIN_INIT = 12;
parameter SATA_MIN_WAKE = 4;
parameter SATA_MAX_BURST = 8;
parameter SATA_MIN_BURST = 4;
parameter SAS_MAX_COM = 64;
parameter SATA_MAX_INIT = 21;
parameter SATA_MAX_WAKE = 7;
// RX Equalizer Attributes, ug476 p.193
parameter RX_OS_CFG = 13'h0080;
parameter RXLPM_LF_CFG = 14'h00f0;
parameter RXLPM_HF_CFG = 14'h00f0;
parameter RX_DFE_LPM_CFG = 16'h0;
parameter RX_DFE_GAIN_CFG = 23'h020FEA;
parameter RX_DFE_H2_CFG = 12'h0;
parameter RX_DFE_H3_CFG = 12'h040;
parameter RX_DFE_H4_CFG = 11'h0e0;
parameter RX_DFE_H5_CFG = 11'h0e0;
parameter PMA_RSV = 32'h00018480;
parameter RX_DFE_LPM_HOLD_DURING_EIDLE = 1'b0;
parameter RX_DFE_XYD_CFG = 13'h0;
parameter PMA_RSV4 = 32'h0;
parameter PMA_RSV2 = 16'h0;
parameter RX_BIAS_CFG = 12'h040;
parameter RX_DEBUG_CFG = 12'h0;
parameter RX_DFE_KL_CFG = 13'h0;
parameter RX_DFE_KL_CFG2 = 32'h0;
parameter RX_DFE_UT_CFG = 17'h11e00;
parameter RX_DFE_VP_CFG = 17'h03f03;
// CDR Attributes, ug476 p.203
parameter RXCDR_CFG = 72'h0;
parameter RXCDR_LOCK_CFG = 6'h0;
parameter RXCDR_HOLD_DURING_EIDLE = 1'b0;
parameter RXCDR_FR_RESET_ON_EIDLE = 1'b0;
parameter RXCDR_PH_RESET_ON_EIDLE = 1'b0;
// RX Fabric Clock Output Control Attributes
parameter RXBUF_RESET_ON_RATE_CHANGE = "TRUE";
// RX Margin Analysis Attributes
parameter ES_VERT_OFFSET = 9'h0;
parameter ES_HORZ_OFFSET = 12'h0;
parameter ES_PRESCALE = 5'h0;
parameter ES_SDATA_MASK = 80'h0;
parameter ES_QUALIFIER = 80'h0;
parameter ES_QUAL_MASK = 80'h0;
parameter ES_EYE_SCAN_EN = 1'b1;
parameter ES_ERRDET_EN = 1'b0;
parameter ES_CONTROL = 6'h0;
parameter es_control_status = 4'b000;
parameter es_rdata = 80'h0;
parameter es_sdata = 80'h0;
parameter es_error_count = 16'h0;
parameter es_sample_count = 16'h0;
parameter RX_DATA_WIDTH = 20;
parameter RX_INT_DATAWIDTH = 0;
parameter ES_PMA_CFG = 10'h0;
// Pattern Checker Attributes, ug476 p.226
parameter RX_PRBS_ERR_CNT = 16'h15c;
// RX Byte and Word Alignment Attributes, ug476 p.235
parameter ALIGN_COMMA_WORD = 1;
parameter ALIGN_COMMA_ENABLE = 10'b1111111111;
parameter ALIGN_COMMA_DOUBLE = "FALSE";
parameter ALIGN_MCOMMA_DET = "TRUE";
parameter ALIGN_MCOMMA_VALUE = 10'b1010000011;
parameter ALIGN_PCOMMA_DET = "TRUE";
parameter ALIGN_PCOMMA_VALUE = 10'b0101111100;
parameter SHOW_REALIGN_COMMA = "TRUE";
parameter RXSLIDE_MODE = "OFF";
parameter RXSLIDE_AUTO_WAIT = 7;
parameter RX_SIG_VALID_DLY = 10;
parameter COMMA_ALIGN_LATENCY = 9'h14e;
// RX 8B/10B Decoder Attributes, ug476 p.242
parameter RX_DISPERR_SEQ_MATCH = "TRUE";
parameter DEC_MCOMMA_DETECT = "TRUE";
parameter DEC_PCOMMA_DETECT = "TRUE";
parameter DEC_VALID_COMMA_ONLY = "FALSE";
parameter UCODEER_CLR = 1'b0;
// RX Buffer Bypass Attributes, ug476 p.247
parameter RXBUF_EN = "TRUE";
parameter RX_XCLK_SEL = "RXREC";
parameter RXPH_CFG = 24'h0;
parameter RXPH_MONITOR_SEL = 5'h0;
parameter RXPHDLY_CFG = 24'h0;
parameter RXDLY_CFG = 16'h0;
parameter RXDLY_LCFG = 9'h0;
parameter RXDLY_TAP_CFG = 16'h0;
parameter RX_DDI_SEL = 6'h0;
parameter TST_RSV = 32'h0;
// RX Buffer Attributes, ug476 p.259
parameter RX_BUFFER_CFG = 6'b0;
parameter RX_DEFER_RESET_BUF_EN = "TRUE";
parameter RXBUF_ADDR_MODE = "FAST";
parameter RXBUF_EIDLE_HI_CNT = 4'b0;
parameter RXBUF_EIDLE_LO_CNT = 4'b0;
parameter RXBUF_RESET_ON_CB_CHANGE = "TRUE";
parameter RXBUF_RESET_ON_COMMAALIGN = "FALSE";
parameter RXBUF_RESET_ON_EIDLE = "FALSE";
parameter RXBUF_THRESH_OVFLW = 0;
parameter RXBUF_THRESH_OVRD = "FALSE";
parameter RXBUF_THRESH_UNDFLW = 0;
// RX Clock Correction Attributes, ug476 p.265
parameter CBCC_DATA_SOURCE_SEL = "DECODED";
parameter CLK_CORRECT_USE = "FALSE";
parameter CLK_COR_SEQ_2_USE = "FALSE";
parameter CLK_COR_KEEP_IDLE = "FALSE";
parameter CLK_COR_MAX_LAT = 9;
parameter CLK_COR_MIN_LAT = 7;
parameter CLK_COR_PRECEDENCE = "TRUE";
parameter CLK_COR_REPEAT_WAIT = 0;
parameter CLK_COR_SEQ_LEN = 1;
parameter CLK_COR_SEQ_1_ENABLE = 4'b1111;
parameter CLK_COR_SEQ_1_1 = 10'b0;
parameter CLK_COR_SEQ_1_2 = 10'b0;
parameter CLK_COR_SEQ_1_3 = 10'b0;
parameter CLK_COR_SEQ_1_4 = 10'b0;
parameter CLK_COR_SEQ_2_ENABLE = 4'b1111;
parameter CLK_COR_SEQ_2_1 = 10'b0;
parameter CLK_COR_SEQ_2_2 = 10'b0;
parameter CLK_COR_SEQ_2_3 = 10'b0;
parameter CLK_COR_SEQ_2_4 = 10'b0;
// RX Channel Bonding Attributes, ug476 p.276
parameter CHAN_BOND_MAX_SKEW = 1;
parameter CHAN_BOND_KEEP_ALIGN = "FALSE";
parameter CHAN_BOND_SEQ_LEN = 1;
parameter CHAN_BOND_SEQ_1_1 = 10'b0;
parameter CHAN_BOND_SEQ_1_2 = 10'b0;
parameter CHAN_BOND_SEQ_1_3 = 10'b0;
parameter CHAN_BOND_SEQ_1_4 = 10'b0;
parameter CHAN_BOND_SEQ_1_ENABLE = 4'b1111;
parameter CHAN_BOND_SEQ_2_1 = 10'b0;
parameter CHAN_BOND_SEQ_2_2 = 10'b0;
parameter CHAN_BOND_SEQ_2_3 = 10'b0;
parameter CHAN_BOND_SEQ_2_4 = 10'b0;
parameter CHAN_BOND_SEQ_2_ENABLE = 4'b1111;
parameter CHAN_BOND_SEQ_2_USE = "FALSE";
parameter FTS_DESKEW_SEQ_ENABLE = 4'b1111;
parameter FTS_LANE_DESKEW_CFG = 4'b1111;
parameter FTS_LANE_DESKEW_EN = "FALSE";
parameter PCS_PCIE_EN = "FALSE";
// RX Gearbox Attributes, ug476 p.287
parameter RXGEARBOX_EN = "FALSE";
// ug476 table p.326 - undocumented parameters
parameter RX_CLK25_DIV = 6;
parameter TX_CLK25_DIV = 6;
`ifdef OPEN_SOURCE_ONLY
GTXE2_CPL gtx_gpl #(
`else // OPEN_SOURCE_ONLY
GTXE2_CHANNEL gtx_unisims #(
`endif // OPEN_SOURCE_ONLY
// simulation common attributes, UG476 p.28
.SIM_RESET_SPEEDUP (SIM_RESET_SPEEDUP),
.SIM_CPLLREFCLK_SEL (SIM_CPLLREFCLK_SEL),
.SIM_RECEIVER_DETECT_PASS (SIM_RECEIVER_DETECT_PASS),
.SIM_TX_EIDLE_DRIVE_LEVEL (SIM_TX_EIDLE_DRIVE_LEVEL),
.SIM_VERSION (SIM_VERSION),
// Clocking Atributes, UG476 p.38
.OUTREFCLK_SEL_INV (OUTREFCLK_SEL_INV),
// CPLL Attributes, UG476 p.49
.CPLL_CFG (CPLL_CFG),
.CPLL_FBDIV (CPLL_FBDIV),
.CPLL_FBDIV_45 (CPLL_FBDIV_45),
.CPLL_INIT_CFG (CPLL_INIT_CFG),
.CPLL_LOCK_CFG (CPLL_LOCK_CFG),
.CPLL_REFCLK_DIV (CPLL_REFCLK_DIV),
.RXOUT_DIV (RXOUT_DIV),
.TXOUT_DIV (TXOUT_DIV),
.SATA_CPLL_CFG (SATA_CPLL_CFG),
.PMA_RSV3 (PMA_RSV3),
// TX Initialization and Reset Attributes, ug476 p.66
.TXPCSRESET_TIME (TXPCSRESET_TIME),
.TXPMARESET_TIME (TXPMARESET_TIME),
// RX Initialization and Reset Attributes, UG476 p.75
.RXPMARESET_TIME (RXPMARESET_TIME),
.RXCDRPHRESET_TIME (RXCDRPHRESET_TIME),
.RXCDRFREQRESET_TIME (RXCDRFREQRESET_TIME),
.RXDFELPMRESET_TIME (RXDFELPMRESET_TIME),
.RXISCANRESET_TIME (RXISCANRESET_TIME),
.RXPCSRESET_TIME (RXPCSRESET_TIME),
.RXBUFRESET_TIME (RXBUFRESET_TIME),
// Power Down attributes, ug476 p.88
.PD_TRANS_TIME_FROM_P2 (PD_TRANS_TIME_FROM_P2),
.PD_TRANS_TIME_NONE_P2 (PD_TRANS_TIME_NONE_P2),
.PD_TRANS_TIME_TO_P2 (PD_TRANS_TIME_TO_P2),
.TRANS_TIME_RATE (TRANS_TIME_RATE),
.RX_CLKMUX_PD (RX_CLKMUX_PD),
.TX_CLKMUX_PD (TX_CLKMUX_PD),
// GTX Digital Monitor Attributes, ug476 p.96
.DMONITOR_CFG (DMONITOR_CFG),
// TX Interface attributes, ug476 p.111
.TX_DATA_WIDTH (TX_DATA_WIDTH),
.TX_INT_DATAWIDTH (TX_INT_DATAWIDTH),
// TX Gearbox Attributes, ug476 p.121
.GEARBOX_MODE (GEARBOX_MODE),
.TXGEARBOX_EN (TXGEARBOX_EN),
// TX BUffer Attributes, ug476 p.134
.TXBUF_EN (TXBUF_EN),
// TX Bypass buffer, ug476 p.138
.TX_XCLK_SEL (TX_XCLK_SEL),
.TXPH_CFG (TXPH_CFG),
.TXPH_MONITOR_SEL (TXPH_MONITOR_SEL),
.TXPHDLY_CFG (TXPHDLY_CFG),
.TXDLY_CFG (TXDLY_CFG),
.TXDLY_LCFG (TXDLY_LCFG),
.TXDLY_TAP_CFG (TXDLY_TAP_CFG),
.TXSYNC_MULTILANE (TXSYNC_MULTILANE),
.TXSYNC_SKIP_DA (TXSYNC_SKIP_DA),
.TXSYNC_OVRD (TXSYNC_OVRD),
.LOOPBACK_CFG (LOOPBACK_CFG),
// TX Pattern Generator, ug476 p.147
.RXPRBS_ERR_LOOPBACK (RXPRBS_ERR_LOOPBACK),
// TX Fabric Clock Output Control Attributes, ug476 p. 153
.TXBUF_RESET_ON_RATE_CHANGE (TXBUF_RESET_ON_RATE_CHANGE),
// TX Phase Interpolator PPM Controller Attributes, ug476 p.155
// GTH only
/* .TXPI_SYNCFREQ_PPM (TXPI_SYNCFREQ_PPM),
.TXPI_PPM_CFG (TXPI_PPM_CFG),
.TXPI_INVSTROBE_SEL (TXPI_INVSTROBE_SEL),
.TXPI_GREY_SEL (TXPI_GREY_SEL),
.TXPI_PPMCLK_SEL (TXPI_PPMCLK_SEL),*/
// TX Configurable Driver Attributes, ug476 p.162
.TX_DEEMPH0 (TX_DEEMPH0),
.TX_DEEMPH1 (TX_DEEMPH1),
.TX_DRIVE_MODE (TX_DRIVE_MODE),
.TX_MAINCURSOR_SEL (TX_MAINCURSOR_SEL),
.TX_MARGIN_FULL_0 (TX_MARGIN_FULL_0),
.TX_MARGIN_FULL_1 (TX_MARGIN_FULL_1),
.TX_MARGIN_FULL_2 (TX_MARGIN_FULL_2),
.TX_MARGIN_FULL_3 (TX_MARGIN_FULL_3),
.TX_MARGIN_FULL_4 (TX_MARGIN_FULL_4),
.TX_MARGIN_LOW_0 (TX_MARGIN_LOW_0),
.TX_MARGIN_LOW_1 (TX_MARGIN_LOW_1),
.TX_MARGIN_LOW_2 (TX_MARGIN_LOW_2),
.TX_MARGIN_LOW_3 (TX_MARGIN_LOW_3),
.TX_MARGIN_LOW_4 (TX_MARGIN_LOW_4),
.TX_PREDRIVER_MODE (TX_PREDRIVER_MODE),
.TX_QPI_STATUS_EN (TX_QPI_STATUS_EN),
.TX_EIDLE_ASSERT_DELAY (TX_EIDLE_ASSERT_DELAY),
.TX_EIDLE_DEASSERT_DELAY (TX_EIDLE_DEASSERT_DELAY),
.TX_LOOPBACK_DRIVE_HIZ (TX_LOOPBACK_DRIVE_HIZ),
// TX Receiver Detection Attributes, ug476 p.165
.TX_RXDETECT_CFG (TX_RXDETECT_CFG),
.TX_RXDETECT_REF (TX_RXDETECT_REF),
// TX OOB Signaling Attributes
.SATA_BURST_SEQ_LEN (SATA_BURST_SEQ_LEN),
// RX AFE Attributes, ug476 p.171
.RX_CM_SEL (RX_CM_SEL),
.TERM_RCAL_CFG (TERM_RCAL_CFG),
.TERM_RCAL_OVRD (TERM_RCAL_OVRD),
.RX_CM_TRIM (RX_CM_TRIM),
// RX OOB Signaling Attributes, ug476 p.179
.PCS_RSVD_ATTR (PCS_RSVD_ATTR),
.RXOOB_CFG (RXOOB_CFG),
.SATA_BURST_VAL (SATA_BURST_VAL),
.SATA_EIDLE_VAL (SATA_EIDLE_VAL),
.SAS_MIN_COM (SAS_MIN_COM),
.SATA_MIN_INIT (SATA_MIN_INIT),
.SATA_MIN_WAKE (SATA_MIN_WAKE),
.SATA_MAX_BURST (SATA_MAX_BURST),
.SATA_MIN_BURST (SATA_MIN_BURST),
.SAS_MAX_COM (SAS_MAX_COM),
.SATA_MAX_INIT (SATA_MAX_INIT),
.SATA_MAX_WAKE (SATA_MAX_WAKE),
// RX Equalizer Attributes, ug476 p.193
.RX_OS_CFG (RX_OS_CFG),
.RXLPM_LF_CFG (RXLPM_LF_CFG),
.RXLPM_HF_CFG (RXLPM_HF_CFG),
.RX_DFE_LPM_CFG (RX_DFE_LPM_CFG),
.RX_DFE_GAIN_CFG (RX_DFE_GAIN_CFG),
.RX_DFE_H2_CFG (RX_DFE_H2_CFG),
.RX_DFE_H3_CFG (RX_DFE_H3_CFG),
.RX_DFE_H4_CFG (RX_DFE_H4_CFG),
.RX_DFE_H5_CFG (RX_DFE_H5_CFG),
.PMA_RSV (PMA_RSV),
.RX_DFE_LPM_HOLD_DURING_EIDLE (RX_DFE_LPM_HOLD_DURING_EIDLE),
.RX_DFE_XYD_CFG (RX_DFE_XYD_CFG),
.PMA_RSV4 (PMA_RSV4),
.PMA_RSV2 (PMA_RSV2),
.RX_BIAS_CFG (RX_BIAS_CFG),
.RX_DEBUG_CFG (RX_DEBUG_CFG),
.RX_DFE_KL_CFG (RX_DFE_KL_CFG),
.RX_DFE_KL_CFG2 (RX_DFE_KL_CFG2),
.RX_DFE_UT_CFG (RX_DFE_UT_CFG),
.RX_DFE_VP_CFG (RX_DFE_VP_CFG),
// CDR Attributes, ug476 p.203
.RXCDR_CFG (RXCDR_CFG),
.RXCDR_LOCK_CFG (RXCDR_LOCK_CFG),
.RXCDR_HOLD_DURING_EIDLE (RXCDR_HOLD_DURING_EIDLE),
.RXCDR_FR_RESET_ON_EIDLE (RXCDR_FR_RESET_ON_EIDLE),
.RXCDR_PH_RESET_ON_EIDLE (RXCDR_PH_RESET_ON_EIDLE),
// RX Fabric Clock Output Control Attributes
.RXBUF_RESET_ON_RATE_CHANGE (RXBUF_RESET_ON_RATE_CHANGE),
// RX Margin Analysis Attributes
.ES_VERT_OFFSET (ES_VERT_OFFSET),
.ES_HORZ_OFFSET (ES_HORZ_OFFSET),
.ES_PRESCALE (ES_PRESCALE),
.ES_SDATA_MASK (ES_SDATA_MASK),
.ES_QUALIFIER (ES_QUALIFIER),
.ES_QUAL_MASK (ES_QUAL_MASK),
.ES_EYE_SCAN_EN (ES_EYE_SCAN_EN),
.ES_ERRDET_EN (ES_ERRDET_EN),
.ES_CONTROL (ES_CONTROL),
/* .es_control_status (es_control_status),
.es_rdata (es_rdata),
.es_sdata (es_sdata),
.es_error_count (es_error_count),
.es_sample_count (es_sample_count),*/
.RX_DATA_WIDTH (RX_DATA_WIDTH),
.RX_INT_DATAWIDTH (RX_INT_DATAWIDTH),
.ES_PMA_CFG (ES_PMA_CFG),
// Pattern Checker Attributes, ug476 p.226
.RX_PRBS_ERR_CNT (RX_PRBS_ERR_CNT),
// RX Byte and Word Alignment Attributes, ug476 p.235
.ALIGN_COMMA_WORD (ALIGN_COMMA_WORD),
.ALIGN_COMMA_ENABLE (ALIGN_COMMA_ENABLE),
.ALIGN_COMMA_DOUBLE (ALIGN_COMMA_DOUBLE),
.ALIGN_MCOMMA_DET (ALIGN_MCOMMA_DET),
.ALIGN_MCOMMA_VALUE (ALIGN_MCOMMA_VALUE),
.ALIGN_PCOMMA_DET (ALIGN_PCOMMA_DET),
.ALIGN_PCOMMA_VALUE (ALIGN_PCOMMA_VALUE),
.SHOW_REALIGN_COMMA (SHOW_REALIGN_COMMA),
.RXSLIDE_MODE (RXSLIDE_MODE),
.RXSLIDE_AUTO_WAIT (RXSLIDE_AUTO_WAIT),
.RX_SIG_VALID_DLY (RX_SIG_VALID_DLY),
.COMMA_ALIGN_LATENCY (COMMA_ALIGN_LATENCY),
// RX 8B/10B Decoder Attributes, ug476 p.242
.RX_DISPERR_SEQ_MATCH (RX_DISPERR_SEQ_MATCH),
.DEC_MCOMMA_DETECT (DEC_MCOMMA_DETECT),
.DEC_PCOMMA_DETECT (DEC_PCOMMA_DETECT),
.DEC_VALID_COMMA_ONLY (DEC_VALID_COMMA_ONLY),
.UCODEER_CLR (UCODEER_CLR),
// RX Buffer Bypass Attributes, ug476 p.247
.RXBUF_EN (RXBUF_EN),
.RX_XCLK_SEL (RX_XCLK_SEL),
.RXPH_CFG (RXPH_CFG),
.RXPH_MONITOR_SEL (RXPH_MONITOR_SEL),
.RXPHDLY_CFG (RXPHDLY_CFG),
.RXDLY_CFG (RXDLY_CFG),
.RXDLY_LCFG (RXDLY_LCFG),
.RXDLY_TAP_CFG (RXDLY_TAP_CFG),
.RX_DDI_SEL (RX_DDI_SEL),
.TST_RSV (TST_RSV),
// RX Buffer Attributes, ug476 p.259
.RX_BUFFER_CFG (RX_BUFFER_CFG),
.RX_DEFER_RESET_BUF_EN (RX_DEFER_RESET_BUF_EN),
.RXBUF_ADDR_MODE (RXBUF_ADDR_MODE),
.RXBUF_EIDLE_HI_CNT (RXBUF_EIDLE_HI_CNT),
.RXBUF_EIDLE_LO_CNT (RXBUF_EIDLE_LO_CNT),
.RXBUF_RESET_ON_CB_CHANGE (RXBUF_RESET_ON_CB_CHANGE),
.RXBUF_RESET_ON_COMMAALIGN (RXBUF_RESET_ON_COMMAALIGN),
.RXBUF_RESET_ON_EIDLE (RXBUF_RESET_ON_EIDLE),
.RXBUF_THRESH_OVFLW (RXBUF_THRESH_OVFLW),
.RXBUF_THRESH_OVRD (RXBUF_THRESH_OVRD),
.RXBUF_THRESH_UNDFLW (RXBUF_THRESH_UNDFLW),
// RX Clock Correction Attributes, ug476 p.265
.CBCC_DATA_SOURCE_SEL (CBCC_DATA_SOURCE_SEL),
.CLK_CORRECT_USE (CLK_CORRECT_USE),
.CLK_COR_SEQ_2_USE (CLK_COR_SEQ_2_USE),
.CLK_COR_KEEP_IDLE (CLK_COR_KEEP_IDLE),
.CLK_COR_MAX_LAT (CLK_COR_MAX_LAT),
.CLK_COR_MIN_LAT (CLK_COR_MIN_LAT),
.CLK_COR_PRECEDENCE (CLK_COR_PRECEDENCE),
.CLK_COR_REPEAT_WAIT (CLK_COR_REPEAT_WAIT),
.CLK_COR_SEQ_LEN (CLK_COR_SEQ_LEN),
.CLK_COR_SEQ_1_ENABLE (CLK_COR_SEQ_1_ENABLE),
.CLK_COR_SEQ_1_1 (CLK_COR_SEQ_1_1),
.CLK_COR_SEQ_1_2 (CLK_COR_SEQ_1_2),
.CLK_COR_SEQ_1_3 (CLK_COR_SEQ_1_3),
.CLK_COR_SEQ_1_4 (CLK_COR_SEQ_1_4),
.CLK_COR_SEQ_2_ENABLE (CLK_COR_SEQ_2_ENABLE),
.CLK_COR_SEQ_2_1 (CLK_COR_SEQ_2_1),
.CLK_COR_SEQ_2_2 (CLK_COR_SEQ_2_2),
.CLK_COR_SEQ_2_3 (CLK_COR_SEQ_2_3),
.CLK_COR_SEQ_2_4 (CLK_COR_SEQ_2_4),
// RX Channel Bonding Attributes, ug476 p.276
.CHAN_BOND_MAX_SKEW (CHAN_BOND_MAX_SKEW),
.CHAN_BOND_KEEP_ALIGN (CHAN_BOND_KEEP_ALIGN),
.CHAN_BOND_SEQ_LEN (CHAN_BOND_SEQ_LEN),
.CHAN_BOND_SEQ_1_1 (CHAN_BOND_SEQ_1_1),
.CHAN_BOND_SEQ_1_2 (CHAN_BOND_SEQ_1_2),
.CHAN_BOND_SEQ_1_3 (CHAN_BOND_SEQ_1_3),
.CHAN_BOND_SEQ_1_4 (CHAN_BOND_SEQ_1_4),
.CHAN_BOND_SEQ_1_ENABLE (CHAN_BOND_SEQ_1_ENABLE),
.CHAN_BOND_SEQ_2_1 (CHAN_BOND_SEQ_2_1),
.CHAN_BOND_SEQ_2_2 (CHAN_BOND_SEQ_2_2),
.CHAN_BOND_SEQ_2_3 (CHAN_BOND_SEQ_2_3),
.CHAN_BOND_SEQ_2_4 (CHAN_BOND_SEQ_2_4),
.CHAN_BOND_SEQ_2_ENABLE (CHAN_BOND_SEQ_2_ENABLE),
.CHAN_BOND_SEQ_2_USE (CHAN_BOND_SEQ_2_USE),
.FTS_DESKEW_SEQ_ENABLE (FTS_DESKEW_SEQ_ENABLE),
.FTS_LANE_DESKEW_CFG (FTS_LANE_DESKEW_CFG),
.FTS_LANE_DESKEW_EN (FTS_LANE_DESKEW_EN),
.PCS_PCIE_EN (PCS_PCIE_EN),
// RX Gearbox Attributes, ug476 p.287
.RXGEARBOX_EN (RXGEARBOX_EN),
// ug476 table p.326 - undocumented parameters
.RX_CLK25_DIV (RX_CLK25_DIV),
.TX_CLK25_DIV (TX_CLK25_DIV)
)
(
// clocking ports, UG476 p.37
.CPLLREFCLKSEL (CPLLREFCLKSEL),
.GTGREFCLK (GTGREFCLK),
.GTNORTHREFCLK0 (GTNORTHREFCLK0),
.GTNORTHREFCLK1 (GTNORTHREFCLK1),
.GTREFCLK0 (GTREFCLK0),
.GTREFCLK1 (GTREFCLK1),
.GTSOUTHREFCLK0 (GTSOUTHREFCLK0),
.GTSOUTHREFCLK1 (GTSOUTHREFCLK1),
.RXSYSCLKSEL (RXSYSCLKSEL),
.TXSYSCLKSEL (TXSYSCLKSEL),
.GTREFCLKMONITOR (GTREFCLKMONITOR),
// CPLL Ports, UG476 p.48
.CPLLLOCKDETCLK (CPLLLOCKDETCLK),
.CPLLLOCKEN (CPLLLOCKEN),
.CPLLPD (CPLLPD),
.CPLLRESET (CPLLRESET),
.CPLLFBCLKLOST (CPLLFBCLKLOST),
.CPLLLOCK (CPLLLOCK),
.CPLLREFCLKLOST (CPLLREFCLKLOST),
.TSTOUT (TSTOUT),
.GTRSVD (GTRSVD),
.PCSRSVDIN (PCSRSVDIN),
.PCSRSVDIN2 (PCSRSVDIN2),
.PMARSVDIN (PMARSVDIN),
.PMARSVDIN2 (PMARSVDIN2),
.TSTIN (TSTIN),
// Reset Mode ports, ug476 p.62
.GTRESETSEL (GTRESETSEL),
.RESETOVRD (RESETOVRD),
// TX Reset ports, ug476 p.65
.CFGRESET (CFGRESET),
.GTTXRESET (GTTXRESET),
.TXPCSRESET (TXPCSRESET),
.TXPMARESET (TXPMARESET),
.TXRESETDONE (TXRESETDONE),
.TXUSERRDY (TXUSERRDY),
.PCSRSVDOUT (PCSRSVDOUT),
// RX Reset ports, UG476 p.73
.GTRXRESET (GTRXRESET),
.RXPMARESET (RXPMARESET),
.RXCDRRESET (RXCDRRESET),
.RXCDRFREQRESET (RXCDRFREQRESET),
.RXDFELPMRESET (RXDFELPMRESET),
.EYESCANRESET (EYESCANRESET),
.RXPCSRESET (RXPCSRESET),
.RXBUFRESET (RXBUFRESET),
.RXUSERRDY (RXUSERRDY),
.RXRESETDONE (RXRESETDONE),
.RXOOBRESET (RXOOBRESET),
// Power Down ports, ug476 p.88
.RXPD (RXPD),
.TXPD (TXPD),
.TXPDELECIDLEMODE (TXPDELECIDLEMODE),
.TXPHDLYPD (TXPHDLYPD),
.RXPHDLYPD (RXPHDLYPD),
// Loopback ports, ug476 p.91
.LOOPBACK (LOOPBACK),
// Dynamic Reconfiguration Port, ug476 p.92
.DRPADDR (DRPADDR),
.DRPCLK (DRPCLK),
.DRPDI (DRPDI),
.DRPDO (DRPDO),
.DRPEN (DRPEN),
.DRPRDY (DRPRDY),
.DRPWE (DRPWE),
// Digital Monitor Ports, ug476 p.95
.CLKRSVD (CLKRSVD),
.DMONITOROUT (DMONITOROUT),
// TX Interface Ports, ug476 p.110
.TXCHARDISPMODE (TXCHARDISPMODE),
.TXCHARDISPVAL (TXCHARDISPVAL),
.TXDATA (TXDATA),
.TXUSRCLK (TXUSRCLK),
.TXUSRCLK2 (TXUSRCLK2),
// TX 8B/10B encoder ports, ug476 p.118
.TX8B10BBYPASS (TX8B10BBYPASS),
.TX8B10BEN (TX8B10BEN),
.TXCHARISK (TXCHARISK),
// TX Gearbox ports, ug476 p.122
.TXGEARBOXREADY (TXGEARBOXREADY),
.TXHEADER (TXHEADER),
.TXSEQUENCE (TXSEQUENCE),
.TXSTARTSEQ (TXSTARTSEQ),
// TX BUffer Ports, ug476 p.134
.TXBUFSTATUS (TXBUFSTATUS),
// TX Buffer Bypass Ports, ug476 p.136
.TXDLYSRESET (TXDLYSRESET),
.TXPHALIGN (TXPHALIGN),
.TXPHALIGNEN (TXPHALIGNEN),
.TXPHINIT (TXPHINIT),
.TXPHOVRDEN (TXPHOVRDEN),
.TXPHDLYRESET (TXPHDLYRESET),
.TXDLYBYPASS (TXDLYBYPASS),
.TXDLYEN (TXDLYEN),
.TXDLYOVRDEN (TXDLYOVRDEN),
.TXPHDLYTSTCLK (TXPHDLYTSTCLK),
.TXDLYHOLD (TXDLYHOLD),
.TXDLYUPDOWN (TXDLYUPDOWN),
.TXPHALIGNDONE (TXPHALIGNDONE),
.TXPHINITDONE (TXPHINITDONE),
.TXDLYSRESETDONE (TXDLYSRESETDONE),
.TXSYNCMODE (TXSYNCMODE),
.TXSYNCALLIN (TXSYNCALLIN),
.TXSYNCIN (TXSYNCIN),
.TXSYNCOUT (TXSYNCOUT),
.TXSYNCDONE (TXSYNCDONE),
// TX Pattern Generator, ug476 p.147
.TXPRBSSEL (TXPRBSSEL),
.TXPRBSFORCEERR (TXPRBSFORCEERR),
// TX Polarity Control Ports, ug476 p.149
.TXPOLARITY (TXPOLARITY),
// TX Fabric Clock Output Control Ports, ug476 p.152
.TXOUTCLKSEL (TXOUTCLKSEL),
.TXRATE (TXRATE),
.TXOUTCLKFABRIC (TXOUTCLKFABRIC),
.TXOUTCLK (TXOUTCLK),
.TXOUTCLKPCS (TXOUTCLKPCS),
.TXRATEDONE (TXRATEDONE),
// TX Phase Interpolator PPM Controller Ports, ug476 p.154
// GTH only
/* input TXPIPPMEN,
.TXPIPPMOVRDEN (TXPIPPMOVRDEN),
.TXPIPPMSEL (TXPIPPMSEL),
.TXPIPPMPD (TXPIPPMPD),
.TXPIPPMSTEPSIZE (TXPIPPMSTEPSIZE),*/
// TX Configurable Driver Ports, ug476 p.156
.TXBUFDIFFCTRL (TXBUFDIFFCTRL),
.TXDEEMPH (TXDEEMPH),
.TXDIFFCTRL (TXDIFFCTRL),
.TXELECIDLE (TXELECIDLE),
.TXINHIBIT (TXINHIBIT),
.TXMAINCURSOR (TXMAINCURSOR),
.TXMARGIN (TXMARGIN),
.TXQPIBIASEN (TXQPIBIASEN),
.TXQPISENN (TXQPISENN),
.TXQPISENP (TXQPISENP),
.TXQPISTRONGPDOWN (TXQPISTRONGPDOWN),
.TXQPIWEAKPUP (TXQPIWEAKPUP),
.TXPOSTCURSOR (TXPOSTCURSOR),
.TXPOSTCURSORINV (TXPOSTCURSORINV),
.TXPRECURSOR (TXPRECURSOR),
.TXPRECURSORINV (TXPRECURSORINV),
.TXSWING (TXSWING),
.TXDIFFPD (TXDIFFPD),
.TXPISOPD (TXPISOPD),
// TX Receiver Detection Ports, ug476 p.165
.TXDETECTRX (TXDETECTRX),
.PHYSTATUS (PHYSTATUS),
.RXSTATUS (RXSTATUS),
// TX OOB Signaling Ports, ug476 p.166
.TXCOMFINISH (TXCOMFINISH),
.TXCOMINIT (TXCOMINIT),
.TXCOMSAS (TXCOMSAS),
.TXCOMWAKE (TXCOMWAKE),
// RX AFE Ports, ug476 p.171
.RXQPISENN (RXQPISENN),
.RXQPISENP (RXQPISENP),
.RXQPIEN (RXQPIEN),
// RX OOB Signaling Ports, ug476 p.178
.RXELECIDLEMODE (RXELECIDLEMODE),
.RXELECIDLE (RXELECIDLE),
.RXCOMINITDET (RXCOMINITDET),
.RXCOMSASDET (RXCOMSASDET),
.RXCOMWAKEDET (RXCOMWAKEDET),
// RX Equalizer Ports, ug476 p.189
.RXLPMEN (RXLPMEN),
.RXOSHOLD (RXOSHOLD),
.RXOSOVRDEN (RXOSOVRDEN),
.RXLPMLFHOLD (RXLPMLFHOLD),
.RXLPMLFKLOVRDEN (RXLPMLFKLOVRDEN),
.RXLPMHFHOLD (RXLPMHFHOLD),
.RXLPMHFOVRDEN (RXLPMHFOVRDEN),
.RXDFEAGCHOLD (RXDFEAGCHOLD),
.RXDFEAGCOVRDEN (RXDFEAGCOVRDEN),
.RXDFELFHOLD (RXDFELFHOLD),
.RXDFELFOVRDEN (RXDFELFOVRDEN),
.RXDFEUTHOLD (RXDFEUTHOLD),
.RXDFEUTOVRDEN (RXDFEUTOVRDEN),
.RXDFEVPHOLD (RXDFEVPHOLD),
.RXDFEVPOVRDEN (RXDFEVPOVRDEN),
.RXDFETAP2HOLD (RXDFETAP2HOLD),
.RXDFETAP2OVRDEN (RXDFETAP2OVRDEN),
.RXDFETAP3HOLD (RXDFETAP3HOLD),
.RXDFETAP3OVRDEN (RXDFETAP3OVRDEN),
.RXDFETAP4HOLD (RXDFETAP4HOLD),
.RXDFETAP4OVRDEN (RXDFETAP4OVRDEN),
.RXDFETAP5HOLD (RXDFETAP5HOLD),
.RXDFETAP5OVRDEN (RXDFETAP5OVRDEN),
.RXDFECM1EN (RXDFECM1EN),
.RXDFEXYDHOLD (RXDFEXYDHOLD),
.RXDFEXYDOVRDEN (RXDFEXYDOVRDEN),
.RXDFEXYDEN (RXDFEXYDEN),
.RXMONITORSEL (RXMONITORSEL),
.RXMONITOROUT (RXMONITOROUT),
// CDR Ports, ug476 p.202
.RXCDRHOLD (RXCDRHOLD),
.RXCDROVRDEN (RXCDROVRDEN),
.RXCDRRESETRSV (RXCDRRESETRSV),
.RXRATE (RXRATE),
.RXCDRLOCK (RXCDRLOCK),
// RX Fabric Clock Output Control Ports, ug476 p.213
.RXOUTCLKSEL (RXOUTCLKSEL),
.RXOUTCLKFABRIC (RXOUTCLKFABRIC),
.RXOUTCLK (RXOUTCLK),
.RXOUTCLKPCS (RXOUTCLKPCS),
.RXRATEDONE (RXRATEDONE),
.RXDLYBYPASS (RXDLYBYPASS),
// RX Margin Analysis Ports, ug476 p.220
.EYESCANDATAERROR (EYESCANDATAERROR),
.EYESCANTRIGGER (EYESCANTRIGGER),
.EYESCANMODE (EYESCANMODE),
// RX Polarity Control Ports, ug476 p.224
.RXPOLARITY (RXPOLARITY),
// Pattern Checker Ports, ug476 p.225
.RXPRBSCNTRESET (RXPRBSCNTRESET),
.RXPRBSSEL (RXPRBSSEL),
.RXPRBSERR (RXPRBSERR),
// RX Byte and Word Alignment Ports, ug476 p.233
.RXBYTEISALIGNED (RXBYTEISALIGNED),
.RXBYTEREALIGN (RXBYTEREALIGN),
.RXCOMMADET (RXCOMMADET),
.RXCOMMADETEN (RXCOMMADETEN),
.RXPCOMMAALIGNEN (RXPCOMMAALIGNEN),
.RXMCOMMAALIGNEN (RXMCOMMAALIGNEN),
.RXSLIDE (RXSLIDE),
// RX 8B/10B Decoder Ports, ug476 p.24
.RX8B10BEN (RX8B10BEN),
.RXCHARISCOMMA (RXCHARISCOMMA),
.RXCHARISK (RXCHARISK),
.RXDISPERR (RXDISPERR),
.RXNOTINTABLE (RXNOTINTABLE),
.SETERRSTATUS (SETERRSTATUS),
// RX Buffer Bypass Ports, ug476 p.244
.RXPHDLYRESET (RXPHDLYRESET),
.RXPHALIGN (RXPHALIGN),
.RXPHALIGNEN (RXPHALIGNEN),
.RXPHOVRDEN (RXPHOVRDEN),
.RXDLYSRESET (RXDLYSRESET),
.RXDLYEN (RXDLYEN),
.RXDLYOVRDEN (RXDLYOVRDEN),
.RXDDIEN (RXDDIEN),
.RXPHALIGNDONE (RXPHALIGNDONE),
.RXPHMONITOR (RXPHMONITOR),
.RXPHSLIPMONITOR (RXPHSLIPMONITOR),
.RXDLYSRESETDONE (RXDLYSRESETDONE),
// RX Buffer Ports, ug476 p.259
.RXBUFSTATUS (RXBUFSTATUS),
// RX Clock Correction Ports, ug476 p.263
.RXCLKCORCNT (RXCLKCORCNT),
// RX Channel Bonding Ports, ug476 p.274
.RXCHANBONDSEQ (RXCHANBONDSEQ),
.RXCHANISALIGNED (RXCHANISALIGNED),
.RXCHANREALIGN (RXCHANREALIGN),
.RXCHBONDI (RXCHBONDI),
.RXCHBONDO (RXCHBONDO),
.RXCHBONDLEVEL (RXCHBONDLEVEL),
.RXCHBONDMASTER (RXCHBONDMASTER),
.RXCHBONDSLAVE (RXCHBONDSLAVE),
.RXCHBONDEN (RXCHBONDEN),
// RX Gearbox Ports, ug476 p.285
.RXDATAVALID (RXDATAVALID),
.RXGEARBOXSLIP (RXGEARBOXSLIP),
.RXHEADER (RXHEADER),
.RXHEADERVALID (RXHEADERVALID),
.RXSTARTOFSEQ (RXSTARTOFSEQ),
// FPGA RX Interface Ports, ug476 p.299
.RXDATA (RXDATA),
.RXUSRCLK (RXUSRCLK),
.RXUSRCLK2 (RXUSRCLK2),
// ug476, p.323
.RXVALID (RXVALID),
// for correct clocking scheme in case of multilane structure
.QPLLCLK (QPLLCLK),
.QPLLREFCLK (QPLLREFCLK),
// Diffpairs
.GTXRXP (GTXRXP),
.GTXRXN (GTXRXN),
.GTXTXN (GTXTXN),
.GTXTXP (GTXTXP)
);
endmodule
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