Commit 271e974e authored by Andrey Filippov's avatar Andrey Filippov
Browse files

Fixed link FSM error mishandling sender hold

parent fcb4bd93

.project

+17 −17
Original line number Diff line number Diff line
@@ -52,87 +52,87 @@ 
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			<name>vivado_logs/VivadoBitstream.log</name>

			<type>1</type>

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ahci/ahci_fis_receive.v

+21 −4
Original line number Diff line number Diff line
@@ -63,6 +63,7 @@ module ahci_fis_receive#( 
    input                         update_err_sts,// update PxTFD.STS and PxTFD.ERR from the last received regs d2h

    input                         update_pio,    // update PxTFD.STS and PxTFD.ERR from pio_* (entry PIO:Update)

    input                         update_prdbc,  // update PRDBC in registers

    input                         clear_prdbc,   // save resources - clear prdbc for every command - discard what is written there

    input                         clear_bsy_drq, // clear PxTFD.STS.BSY and PxTFD.STS.DRQ, update

    input                         clear_bsy_set_drq, // clear PxTFD.STS.BSY and sets PxTFD.STS.DRQ, update

    input                         set_bsy,       // set PxTFD.STS.BSY, update
@@ -76,7 +77,12 @@ module ahci_fis_receive#( 
    

    input                         pcmd_fre,      // control bit enables saving FIS to memory (will be ignored for signature)

    

    // TODO: Add writing PRDBC here?

    // TODO: Add writing PRDBC here? Yes, the following. B ut data may be discarded as only 0 is supposed to be written

//    input      [ADDRESS_BITS-1:0] soft_write_addr,  // register address written by software

//    input                  [31:0] soft_write_data,  // register data written (after applying wstb and type (RO, RW, RWC, RW1)

//    input                         soft_write_en,     // write enable for data write

    

    

    output reg                    pPioXfer,      // state variable

    output                  [7:0] tfd_sts,       // Current PxTFD status field (updated after regFIS and SDB - certain fields)

                                                 // tfd_sts[7] - BSY, tfd_sts[3] - DRQ, tfd_sts[0] - ERR
@@ -126,9 +132,10 @@ CLB_OFFS = 0x800 # In the second half of the register space (0x800..0xbff - 1KB) 
FB_OFFS =  0xc00 # Needs 0x100 bytes 

#HBA_PORT0 = 0x100 Not needed, always HBA_OFFS + 0x100



*/



`include "includes/ahci_localparams.vh" // @SuppressThisWarning VEditor : Unused localparams



*/

localparam CLB_OFFS32 =        'h200; //  # In the second half of the register space (0x800..0xbff - 1KB)

localparam HBA_OFFS32 =         0;

localparam HBA_PORT0_OFFS32  = 'h40;
@@ -387,7 +394,17 @@ localparam DATA_TYPE_ERR = 3; 
        else if ((decr_dwcw || decr_dwcr) && !xfer_cntr_zero_r) xfer_cntr_r[31:2] <= {xfer_cntr_r[31:2]} - 

                                                                                     {18'b0, decr_dwcr? data_in_dwords: decr_DXC_dw[11:0]};

        

        if (hba_rst || reg_sdb[0] || reg_ps[4] || reg_ds[5])  prdbc_r[31:2] <= 0;

        // no - it should only be updated when written by software

        //CLB_OFFS32 + 1; // location of PRDBC

/*

    input      [ADDRESS_BITS-1:0] soft_write_addr,  // register address written by software

    input                  [31:0] soft_write_data,  // register data written (after applying wstb and type (RO, RW, RWC, RW1)

    input                         soft_write_en,     // write enable for data write

*/        

//        if (hba_rst || reg_sdb[0] || reg_ps[4] || reg_ds[5])  prdbc_r[31:2] <= 0;

//        if (soft_write_en && (soft_write_addr == (CLB_OFFS32 + 1))) prdbc_r[31:2] <= soft_write_data[31:2];



        if (clear_prdbc || hba_rst)             prdbc_r[31:2] <= 0;

        else if (decr_dwcw || decr_dwcr)        prdbc_r[31:2] <= {prdbc_r[31:2]} + {18'b0, decr_dwcr? data_in_dwords: decr_DXC_dw[11:0]};

        

        xfer_cntr_zero_r <=                     xfer_cntr_r[31:2] == 0;

ahci/ahci_fsm.v

+4 −3
Original line number Diff line number Diff line
@@ -291,7 +291,7 @@ module ahci_fsm 
    wire                           fsm_pre_act_w = fsm_actions && fsm_next; // use it as CS for generated actions (registered)

    

    reg                      [1:0] async_pend_r; // waiting to process cominit_got

    reg                            async_from_st; // chnge to multi-bit if there will be more sources for async transitions

    reg                            async_from_st; // change to multi-bit if there will be more sources for async transitions

//    wire                           asynq_rq = (cominit_got && unsolicited_cominit_en) || pcmd_st_cleared;

    wire                           asynq_rq = (cominit_got && unsolicited_en) || pcmd_st_cleared;

                                   // OK to wait for some time fsm_act_busy is supposed to never hang up
@@ -396,7 +396,8 @@ module ahci_fsm 
        else if (fsm_pre_act_w) fsm_act_busy <= fsm_wait_act_w;

        else if (fsm_act_done)  fsm_act_busy <= 0;

        

        if (pcmd_st_cleared) async_from_st <= 1;

        if      (hba_rst)         async_from_st <= 0;

        else if (pcmd_st_cleared) async_from_st <= 1;

        else if (asynq_rq)        async_from_st <= 0;

        

        if (hba_rst) async_pend_r <= 0;

ahci/ahci_sata_layers.v

+24 −4
Original line number Diff line number Diff line
@@ -212,6 +212,9 @@ module ahci_sata_layers #( 
    

    wire debug_detected_alignp; // oob detects ALIGNp, but not the link layer

    wire                    [31:0] debug_phy0;

    

    wire [31:0]                    datascope0_di;

    

//    assign debug_sata = {link_established, phy_ready, debug_phy[29:16],debug_link[15:0]}; // 

//    assign debug_sata = debug_link[31:0]; // 

///    assign debug_sata = debug_phy;
@@ -261,6 +264,7 @@ module ahci_sata_layers #( 
        if (d2h_fifo_wr) debug_last_d2h_type_in<= d2h_type_in;

        if (d2h_fifo_rd) debug_last_d2h_type<=    d2h_type;

    end

    /*

    assign debug_phy = {h2d_type_out[1:0],h2d_type[1:0],

                        ll_h2d_last,d2h_valid,  d2h_type[1:0],

                        debug_last_d2h_type_in, d2h_type_in[1:0],
@@ -272,6 +276,22 @@ module ahci_sata_layers #( 
                        d2h_waddr[1:0],

                        d2h_raddr[1:0],

                        debug_phy0[ 7:0]};

*/

/*                        

    assign debug_phy = {h2d_type_out[1:0],h2d_type[1:0],

                        ll_h2d_last,d2h_valid,  d2h_type[1:0],

//                        debug_last_d2h_type_in, d2h_type_in[1:0],

//                        debug_last_d2h_type[1:0],

//                        d2h_fill[1:0],

//                        1'b0,

//                        d2h_fifo_wr,

//                        d2h_fifo_re_regen[1:0],

//                        d2h_waddr[1:0],

//                        d2h_raddr[1:0],

                        debug_phy0[23:0]};

*/

assign debug_phy = debug_phy0; 



//                        debug_phy0[15:0]};

//                        debug_phy0[19:0]};
@@ -289,7 +309,7 @@ module ahci_sata_layers #( 
//        .comwake_got     (serr_DW),            // output wire 

    

    

    

    assign datascope_di   = {5'b0,debug_link[5],datascope0_di[25:0]};// aligns_pair tx

    link #(

        .DATA_BYTE_WIDTH(4)

    ) link (
@@ -412,10 +432,10 @@ module ahci_sata_layers #( 
        .datascope_clk     (datascope_clk),     // output

        .datascope_waddr   (datascope_waddr),   // output[9:0] 

        .datascope_we      (datascope_we),      // output

        .datascope_di      (datascope_di),      // output[31:0] 

//        .datascope_trig    (ll_incom_invalidate ), // ll_frame_ackn),     // input datascope external trigger

        .datascope_di      (datascope0_di),      // output[31:0] 

        .datascope_trig    (ll_incom_invalidate ), // ll_frame_ackn),     // input datascope external trigger

//        .datascope_trig    (debug_link[4:0] == 'h0a), // state_send_eof // input datascope external trigger

        .datascope_trig    (debug_link[4:0] == 'h02), // state_rcvr_goodcrc // input datascope external trigger

///        .datascope_trig    (debug_link[4:0] == 'h02), // state_rcvr_goodcrc // input datascope external trigger

        //debug_link

`endif

ahci/ahci_top.v

+42 −1
Original line number Diff line number Diff line
@@ -687,6 +687,28 @@ wire[1:0] debug_fis_end_r; // output[1:0] 
wire[1:0] debug_get_fis_busy_r; // output[1:0]

 



localparam DATA_TYPE_DMA =      0;

localparam DATA_TYPE_FIS_HEAD = 1;

localparam DATA_TYPE_OK =       2;

localparam DATA_TYPE_ERR =      3;



reg [12:0] debug_d2h_length;

reg [12:0] debug_d2h_length_prev;

reg        was_good_bad;

reg        was_good_bad_prev;



always @(posedge mclk) if (d2h_ready && d2h_valid) begin

    if      (d2h_type == DATA_TYPE_FIS_HEAD) debug_d2h_length_prev <= debug_d2h_length;



    if      (d2h_type == DATA_TYPE_FIS_HEAD) debug_d2h_length <= 0;

    else if (d2h_type == DATA_TYPE_DMA)      debug_d2h_length <= debug_d2h_length  + 1;



    if      (d2h_type == DATA_TYPE_FIS_HEAD) was_good_bad_prev <= was_good_bad;



    if      ((d2h_type == DATA_TYPE_OK) || (d2h_type == DATA_TYPE_ERR)) was_good_bad <= (d2h_type == DATA_TYPE_OK);

    

end



    axi_ahci_regs #(

        .ADDRESS_BITS          (ADDRESS_BITS),

        .HBA_RESET_BITS        (HBA_RESET_BITS),
@@ -745,12 +767,29 @@ wire[1:0] debug_get_fis_busy_r; // output[1:0] 
        .afi_cache_set    (set_axi_cache_mode), // output

        .was_hba_rst      (was_hba_rst),     // output 

        .was_port_rst     (was_port_rst),    // output 

/*        

        .debug_in0        ({ debug_data_in_ready,       // output

                             debug_fis_end_w,           // output

                             xfer_cntr_zero,

                             debug_fis_end_r[0],        // debug_fis_end_r[1:0],      // output[1:0] 

                             debug_get_fis_busy_r[1:0], // output[1:0] 

                             debug_dma[25:0]}),       // input[31:0]

 */                            

        .debug_in0        ({ 2'b0,

                             was_good_bad_prev,

                             debug_d2h_length_prev[12:0],

                             2'b0,

                             was_good_bad,

                             debug_d2h_length[12:0]

                             }),

                             

/*

reg [12:0] debug_d2h_length;

reg [12:0] debug_d2h_length_prev;

reg        was_good_bad;

reg        was_good_bad_prev;



*/                             

//        .debug_in1        ({xclk_period[7:0], // lower 8 bits of 12-bit value. Same frequency would be 0x800 (msb opposite to 3 next bits)

//                            debug_dma1[23:0]}),      // debug_in_link),   // input[31:0]

        .debug_in1        ({debug_in_link[15:8],
@@ -1003,6 +1042,8 @@ wire[1:0] debug_get_fis_busy_r; // output[1:0] 
        .update_pio        (frcv_update_pio),        // input  update PxTFD.STS and PxTFD.ERR from pio_* (entry PIO:Update)

        

        .update_prdbc      (frcv_update_prdbc),      // input

        .clear_prdbc       (fsnd_fetch_cmd),         // input save resources - clear prdbc for every commnad

        

        .clear_bsy_drq     (frcv_clear_bsy_drq),     // input

        .clear_bsy_set_drq (frcv_clear_bsy_set_drq), // input