more debugging

ahci/ahci_ctrl_stat.v

@@ -151,7 +151,7 @@ module  ahci_ctrl_stat #(
     wire                          swr_HBA_PORT__PxSCTL = soft_write_en && (soft_write_addr == HBA_PORT__PxSCTL__SPD__ADDR);
 //    wire                          swr_HBA_PORT__PxSSTS = soft_write_en && (soft_write_addr == HBA_PORT__PxSSTS__SPD__ADDR);
     wire                          swr_HBA_PORT__PxSERR = soft_write_en && (soft_write_addr == HBA_PORT__PxSERR__DIAG__X__ADDR);
-    wire                          swr_HBA_PORT__PxCI =   soft_write_en && (soft_write_addr == HBA_PORT__PxCI__CI__DFLT);
+    wire                          swr_HBA_PORT__PxCI =   soft_write_en && (soft_write_addr == HBA_PORT__PxCI__CI__ADDR);
 
     reg                           hba_rst_r = 1;
     reg                           rst_por;

ahci/ahci_dma.v

@@ -321,7 +321,7 @@ module  ahci_dma (
     
     
         if (cmd_start_hclk)  ct_maddr[31:4] <= {ctba_r[31:7],3'b0};
-        else if (ct_done)    ct_maddr[31:4] <= ct_maddr[31:4] + 16;
+        else if (ct_done)    ct_maddr[31:4] <= ct_maddr[31:4] + 8; // 16;
         else if (wcount_set) ct_maddr[31:4] <= ct_maddr[31:4] + 1;
         
         // overall sequencing makes sure that there will be no new requests until older served

ahci/ahci_fis_receive.v

@@ -77,7 +77,7 @@ module  ahci_fis_receive#(
     // TODO: Add writing PRDBC here?
     output reg                    pPioXfer,      // state variable
     output                  [7:0] tfd_sts,       // Current PxTFD status field (updated after regFIS and SDB - certain fields)
-                                                 // tfd_sts[7] - BSY, tfd_sts[4] - DRQ, tfd_sts[0] - ERR
+                                                 // tfd_sts[7] - BSY, tfd_sts[3] - DRQ, tfd_sts[0] - ERR
     output                  [7:0] tfd_err,       // Current PxTFD error field (updated after regFIS and SDB)
     output reg                    fis_i,         // value of "I" field in received regsD2H or SDB FIS or DMA Setup FIS
     output reg                    sdb_n,         // value of "N" field in received SDB FIS 
@@ -307,7 +307,8 @@ localparam DATA_TYPE_ERR =      3;
         
         get_fis_done <=  get_fis_busy_r && (too_long_err || fis_end_w);
         
-        if      (hba_rst || get_fis)          fis_first_vld <= 0;
+//        if      (hba_rst || get_fis)          fis_first_vld <= 0;
+        if      (hba_rst || fis_end_w)          fis_first_vld <= 0; // is_FIS_HEAD stays on longer than just get_fis
         else if (is_FIS_HEAD)                 fis_first_vld <= 1;
         
         if      (hba_rst || get_fis)          fis_ok <= 0;

ahci/ahci_fis_transmit.v

@@ -129,7 +129,8 @@ module  ahci_fis_transmit #(
     reg [READ_REG_LATENCY:0] reg_re_r;
     wire                     reg_re_w; // combined conditions to read register memory
 ///    wire                     reg_stb =     reg_re_r[READ_REG_LATENCY];
-    wire                     pre_reg_stb = reg_re_r[READ_REG_LATENCY-1];
+///    wire                     reg_stb =     reg_re_r[READ_REG_LATENCY-1];
+    wire                     pre_reg_stb = reg_re_r[READ_REG_LATENCY-1] && !reg_re_r[READ_REG_LATENCY]; // only first, to make running 1
     reg                [3:0] fetch_chead_r; 
     reg                [3:0] fetch_chead_stb_r;
     wire                     chead_done_w = fetch_chead_stb_r[2]; // done fetching command header
@@ -177,7 +178,8 @@ module  ahci_fis_transmit #(
     assign ch_p =     ch_p_r;
     assign ch_w =     ch_w_r;
     assign ch_a =     ch_a_r;
-    assign ch_cfl =   cfis_acmd_left_r;
+//    assign ch_cfl =   cfis_acmd_left_r;
+    assign ch_cfl =   ch_cmd_len_r;
     assign reg_re_w = fetch_cmd || chead_bsy_re;
     assign dma_ctba_ld = fetch_chead_stb_r[2];
     assign dma_start =   fetch_chead_stb_r[3]; // next cycle after dma_ctba_ld 
@@ -210,12 +212,10 @@ module  ahci_fis_transmit #(
         // Read 3 DWORDs from the command header
         
         if (hba_rst)                       fetch_chead_r <= 0; // running 1 
-        else if (fetch_cmd)                fetch_chead_r <= 1;
-        else                               fetch_chead_r <= fetch_chead_r << 1;
+        else                               fetch_chead_r <= {fetch_chead_r[2:0], fetch_cmd};
         
         if      (hba_rst)                  fetch_chead_stb_r <= 0;
-        else if (pre_reg_stb && chead_bsy) fetch_chead_stb_r <= 1;
-        else                               fetch_chead_stb_r <= fetch_chead_stb_r << 1;
+        else                               fetch_chead_stb_r <= {fetch_chead_stb_r[2:0], pre_reg_stb && chead_bsy};        
 
         if      (hba_rst)                  chead_bsy <= 0;
         else if (fetch_cmd)                chead_bsy <= 1;
@@ -226,8 +226,7 @@ module  ahci_fis_transmit #(
         else if (fetch_chead_r[1])         chead_bsy_re <= 0; // read 3 dwords
         
         if      (hba_rst)                  reg_re_r <= 0; // [0] -> reg_re output
-        else if (reg_re_w)                 reg_re_r <= 1;
-        else                               reg_re_r <= reg_re_r << 1;
+        else                               reg_re_r <= {reg_re[1:0], reg_re_w};
         
         if      (fetch_cmd)                reg_addr <= CLB_OFFS32;   // there will be more conditions
         else if (reg_re_r[0])              reg_addr <= reg_addr + 1;

ahci/ahci_fsm.v

@@ -194,7 +194,7 @@ module  ahci_fsm
     input                         pxcmd_fre,     // control bit enables saving FIS to memory
     input                         pPioXfer,      // state variable
     input                   [7:0] tfd_sts,       // Current PxTFD status field (updated after regFIS and SDB - certain fields)
-                                                 // tfd_sts[7] - BSY, tfd_sts[4] - DRQ, tfd_sts[0] - ERR
+                                                 // tfd_sts[7] - BSY, tfd_sts[3] - DRQ, tfd_sts[0] - ERR
 ///    input                   [7:0] tfd_err,       // Current PxTFD error field (updated after regFIS and SDB)
     input                         fis_i,         // value of "I" field in received regsD2H or SDB FIS
 ///    input                         sdb_n,         // value of "N" field in received SDB FIS 
@@ -241,7 +241,7 @@ module  ahci_fsm
 `include "includes/ahci_localparams.vh" // @SuppressThisWarning VEditor : Unused localparams
 `include "includes/fis_types.vh"        // @SuppressThisWarning VEditor : Some  localparams unused
     wire                           tfd_bsy =     tfd_sts[7];
-    wire                           tfd_drq =     tfd_sts[4];
+    wire                           tfd_drq =     tfd_sts[3];
     wire                           tfd_sts_err = tfd_sts[0];
     
     reg                     [ 9:0] pgm_waddr;

ahci/ahci_sata_layers.v

@@ -170,7 +170,7 @@ module  ahci_sata_layers #(
     assign d2h_valid = d2h_nempty;
     assign d2h_many =  |d2h_fill[FIFO_ADDR_WIDTH:3]; // 
     
-    assign h2d_ready = h2d_fill[FIFO_ADDR_WIDTH] && !(&h2d_fill[FIFO_ADDR_WIDTH:3]);
+    assign h2d_ready = !h2d_fill[FIFO_ADDR_WIDTH] && !(&h2d_fill[FIFO_ADDR_WIDTH:3]);
     assign ll_d2h_almost_full   = d2h_fill[FIFO_ADDR_WIDTH] || &d2h_fill[FIFO_ADDR_WIDTH-1:6]; // 63 dwords (maybe use :5?) - time to tell device to stop 
     
     assign ll_frame_req_w = !ll_frame_busy && h2d_pending && (((h2d_type == H2D_TYPE_FIS_LAST) && h2d_fifo_wr ) || (|h2d_fill[FIFO_ADDR_WIDTH : BITS_TO_START_XMIT]));

ahci/ahci_top.v

@@ -307,7 +307,7 @@ module  ahci_top#(
     
     // fsm <- state variables that are maintained inside 'ahc_fis_receive'
     wire              [7:0] tfd_sts;       // Current PxTFD status field (updated after regFIS and SDB - certain fields)
-                                           // tfd_sts[7] - BSY, tfd_sts[4] - DRQ, tfd_sts[0] - ERR
+                                           // tfd_sts[7] - BSY, tfd_sts[3] - DRQ, tfd_sts[0] - ERR
 //    wire              [7:0] tfd_err;       // Current PxTFD error field (updated after regFIS and SDB)
     wire                    fis_i;         // value of "I" field in received regsD2H or SDB FIS
 ///    wire                    sdb_n;         // value of "N" field in received SDB FIS 

ahci/sata_ahci_top.v

@@ -221,12 +221,12 @@
     wire         [3:0] sctl_ipm;          // Interface power management transitions allowed
     wire         [3:0] sctl_spd;          // Interface maximal speed
     
-    reg          [2:0] hrst_r;
-    wire               hrst = hrst_r[2];
+    reg          [2:0] nhrst_r;
+    wire               hrst = !nhrst_r[2];
     
     always @ (posedge hclk or posedge arst) begin
-        if (arst) hrst_r <= 0;
-        else      hrst_r <= (hrst_r << 1) | 1;
+        if (arst) nhrst_r <= 0;
+        else      nhrst_r <= (nhrst_r << 1) | 1;
     end
 
     

generated/action_decoder.v

 /*******************************************************************************
  * Module: action_decoder
- * Date:2016-01-24  
+ * Date:2016-01-25  
  * Author: auto-generated file, see ahci_fsm_sequence.py
  * Description: Decode sequencer code to 1-hot actions
  *******************************************************************************/

generated/condition_mux.v

 /*******************************************************************************
  * Module: condition_mux
- * Date:2016-01-24  
+ * Date:2016-01-25  
  * Author: auto-generated file, see ahci_fsm_sequence.py
  * Description: Select condition
  *******************************************************************************/