more debugging

ahci/ahci_ctrl_stat.v

@@ -151,7 +151,7 @@ module  ahci_ctrl_stat #(
     wire                          swr_HBA_PORT__PxSCTL = soft_write_en && (soft_write_addr == HBA_PORT__PxSCTL__SPD__ADDR);
 //    wire                          swr_HBA_PORT__PxSSTS = soft_write_en && (soft_write_addr == HBA_PORT__PxSSTS__SPD__ADDR);
     wire                          swr_HBA_PORT__PxSERR = soft_write_en && (soft_write_addr == HBA_PORT__PxSERR__DIAG__X__ADDR);
-    wire                          swr_HBA_PORT__PxCI =   soft_write_en && (soft_write_addr == HBA_PORT__PxCI__CI__DFLT);
+    wire                          swr_HBA_PORT__PxCI =   soft_write_en && (soft_write_addr == HBA_PORT__PxCI__CI__ADDR);
 
     reg                           hba_rst_r = 1;
     reg                           rst_por;

ahci/ahci_dma.v

@@ -321,7 +321,7 @@ module  ahci_dma (
     
     
         if (cmd_start_hclk)  ct_maddr[31:4] <= {ctba_r[31:7],3'b0};
-        else if (ct_done)    ct_maddr[31:4] <= ct_maddr[31:4] + 16;
+        else if (ct_done)    ct_maddr[31:4] <= ct_maddr[31:4] + 8; // 16;
         else if (wcount_set) ct_maddr[31:4] <= ct_maddr[31:4] + 1;
         
         // overall sequencing makes sure that there will be no new requests until older served

ahci/ahci_fis_receive.v

@@ -77,7 +77,7 @@ module  ahci_fis_receive#(
     // TODO: Add writing PRDBC here?
     output reg                    pPioXfer,      // state variable
     output                  [7:0] tfd_sts,       // Current PxTFD status field (updated after regFIS and SDB - certain fields)
-                                                 // tfd_sts[7] - BSY, tfd_sts[4] - DRQ, tfd_sts[0] - ERR
+                                                 // tfd_sts[7] - BSY, tfd_sts[3] - DRQ, tfd_sts[0] - ERR
     output                  [7:0] tfd_err,       // Current PxTFD error field (updated after regFIS and SDB)
     output reg                    fis_i,         // value of "I" field in received regsD2H or SDB FIS or DMA Setup FIS
     output reg                    sdb_n,         // value of "N" field in received SDB FIS 
@@ -307,7 +307,8 @@ localparam DATA_TYPE_ERR =      3;
         
         get_fis_done <=  get_fis_busy_r && (too_long_err || fis_end_w);
         
-        if      (hba_rst || get_fis)          fis_first_vld <= 0;
+//        if      (hba_rst || get_fis)          fis_first_vld <= 0;
+        if      (hba_rst || fis_end_w)          fis_first_vld <= 0; // is_FIS_HEAD stays on longer than just get_fis
         else if (is_FIS_HEAD)                 fis_first_vld <= 1;
         
         if      (hba_rst || get_fis)          fis_ok <= 0;

ahci/ahci_fis_transmit.v

@@ -129,7 +129,8 @@ module  ahci_fis_transmit #(
     reg [READ_REG_LATENCY:0] reg_re_r;
     wire                     reg_re_w; // combined conditions to read register memory
 ///    wire                     reg_stb =     reg_re_r[READ_REG_LATENCY];
-    wire                     pre_reg_stb = reg_re_r[READ_REG_LATENCY-1];
+///    wire                     reg_stb =     reg_re_r[READ_REG_LATENCY-1];
+    wire                     pre_reg_stb = reg_re_r[READ_REG_LATENCY-1] && !reg_re_r[READ_REG_LATENCY]; // only first, to make running 1
     reg                [3:0] fetch_chead_r; 
     reg                [3:0] fetch_chead_stb_r;
     wire                     chead_done_w = fetch_chead_stb_r[2]; // done fetching command header
@@ -177,7 +178,8 @@ module  ahci_fis_transmit #(
     assign ch_p =     ch_p_r;
     assign ch_w =     ch_w_r;
     assign ch_a =     ch_a_r;
-    assign ch_cfl =   cfis_acmd_left_r;
+//    assign ch_cfl =   cfis_acmd_left_r;
+    assign ch_cfl =   ch_cmd_len_r;
     assign reg_re_w = fetch_cmd || chead_bsy_re;
     assign dma_ctba_ld = fetch_chead_stb_r[2];
     assign dma_start =   fetch_chead_stb_r[3]; // next cycle after dma_ctba_ld 
@@ -210,12 +212,10 @@ module  ahci_fis_transmit #(
         // Read 3 DWORDs from the command header
         
         if (hba_rst)                       fetch_chead_r <= 0; // running 1 
-        else if (fetch_cmd)                fetch_chead_r <= 1;
-        else                               fetch_chead_r <= fetch_chead_r << 1;
+        else                               fetch_chead_r <= {fetch_chead_r[2:0], fetch_cmd};
         
         if      (hba_rst)                  fetch_chead_stb_r <= 0;
-        else if (pre_reg_stb && chead_bsy) fetch_chead_stb_r <= 1;
-        else                               fetch_chead_stb_r <= fetch_chead_stb_r << 1;
+        else                               fetch_chead_stb_r <= {fetch_chead_stb_r[2:0], pre_reg_stb && chead_bsy};        
 
         if      (hba_rst)                  chead_bsy <= 0;
         else if (fetch_cmd)                chead_bsy <= 1;
@@ -226,8 +226,7 @@ module  ahci_fis_transmit #(
         else if (fetch_chead_r[1])         chead_bsy_re <= 0; // read 3 dwords
         
         if      (hba_rst)                  reg_re_r <= 0; // [0] -> reg_re output
-        else if (reg_re_w)                 reg_re_r <= 1;
-        else                               reg_re_r <= reg_re_r << 1;
+        else                               reg_re_r <= {reg_re[1:0], reg_re_w};
         
         if      (fetch_cmd)                reg_addr <= CLB_OFFS32;   // there will be more conditions
         else if (reg_re_r[0])              reg_addr <= reg_addr + 1;

ahci/ahci_fsm.v

@@ -194,7 +194,7 @@ module  ahci_fsm
     input                         pxcmd_fre,     // control bit enables saving FIS to memory
     input                         pPioXfer,      // state variable
     input                   [7:0] tfd_sts,       // Current PxTFD status field (updated after regFIS and SDB - certain fields)
-                                                 // tfd_sts[7] - BSY, tfd_sts[4] - DRQ, tfd_sts[0] - ERR
+                                                 // tfd_sts[7] - BSY, tfd_sts[3] - DRQ, tfd_sts[0] - ERR
 ///    input                   [7:0] tfd_err,       // Current PxTFD error field (updated after regFIS and SDB)
     input                         fis_i,         // value of "I" field in received regsD2H or SDB FIS
 ///    input                         sdb_n,         // value of "N" field in received SDB FIS 
@@ -241,7 +241,7 @@ module  ahci_fsm
 `include "includes/ahci_localparams.vh" // @SuppressThisWarning VEditor : Unused localparams
 `include "includes/fis_types.vh"        // @SuppressThisWarning VEditor : Some  localparams unused
     wire                           tfd_bsy =     tfd_sts[7];
-    wire                           tfd_drq =     tfd_sts[4];
+    wire                           tfd_drq =     tfd_sts[3];
     wire                           tfd_sts_err = tfd_sts[0];
     
     reg                     [ 9:0] pgm_waddr;

ahci/ahci_sata_layers.v

@@ -170,7 +170,7 @@ module  ahci_sata_layers #(
     assign d2h_valid = d2h_nempty;
     assign d2h_many =  |d2h_fill[FIFO_ADDR_WIDTH:3]; // 
     
-    assign h2d_ready = h2d_fill[FIFO_ADDR_WIDTH] && !(&h2d_fill[FIFO_ADDR_WIDTH:3]);
+    assign h2d_ready = !h2d_fill[FIFO_ADDR_WIDTH] && !(&h2d_fill[FIFO_ADDR_WIDTH:3]);
     assign ll_d2h_almost_full   = d2h_fill[FIFO_ADDR_WIDTH] || &d2h_fill[FIFO_ADDR_WIDTH-1:6]; // 63 dwords (maybe use :5?) - time to tell device to stop 
     
     assign ll_frame_req_w = !ll_frame_busy && h2d_pending && (((h2d_type == H2D_TYPE_FIS_LAST) && h2d_fifo_wr ) || (|h2d_fill[FIFO_ADDR_WIDTH : BITS_TO_START_XMIT]));

ahci/ahci_top.v

@@ -307,7 +307,7 @@ module  ahci_top#(
     
     // fsm <- state variables that are maintained inside 'ahc_fis_receive'
     wire              [7:0] tfd_sts;       // Current PxTFD status field (updated after regFIS and SDB - certain fields)
-                                           // tfd_sts[7] - BSY, tfd_sts[4] - DRQ, tfd_sts[0] - ERR
+                                           // tfd_sts[7] - BSY, tfd_sts[3] - DRQ, tfd_sts[0] - ERR
 //    wire              [7:0] tfd_err;       // Current PxTFD error field (updated after regFIS and SDB)
     wire                    fis_i;         // value of "I" field in received regsD2H or SDB FIS
 ///    wire                    sdb_n;         // value of "N" field in received SDB FIS 

ahci/sata_ahci_top.v

@@ -221,12 +221,12 @@
     wire         [3:0] sctl_ipm;          // Interface power management transitions allowed
     wire         [3:0] sctl_spd;          // Interface maximal speed
     
-    reg          [2:0] hrst_r;
-    wire               hrst = hrst_r[2];
+    reg          [2:0] nhrst_r;
+    wire               hrst = !nhrst_r[2];
     
     always @ (posedge hclk or posedge arst) begin
-        if (arst) hrst_r <= 0;
-        else      hrst_r <= (hrst_r << 1) | 1;
+        if (arst) nhrst_r <= 0;
+        else      nhrst_r <= (nhrst_r << 1) | 1;
     end
 
     

generated/action_decoder.v

 /*******************************************************************************
  * Module: action_decoder
- * Date:2016-01-24  
+ * Date:2016-01-25  
  * Author: auto-generated file, see ahci_fsm_sequence.py
  * Description: Decode sequencer code to 1-hot actions
  *******************************************************************************/

generated/condition_mux.v

 /*******************************************************************************
  * Module: condition_mux
- * Date:2016-01-24  
+ * Date:2016-01-25  
  * Author: auto-generated file, see ahci_fsm_sequence.py
  * Description: Select condition
  *******************************************************************************/

tb/tb_ahci.tf

@@ -343,6 +343,7 @@ sata_device dev(
 
 // axi_hp simulation signals
   wire HCLK;
+  wire HRST;
   wire [31:0] afi_sim_rd_address;    // output[31:0] 
   wire [ 5:0] afi_sim_rid;           // output[5:0]  SuppressThisWarning VEditor - not used - just view
 //  reg         afi_sim_rd_valid;      // input
@@ -355,26 +356,29 @@ sata_device dev(
   wire  [ 1:0] afi_sim_rd_resp;       // input[1:0] 
 //  reg  [ 1:0] afi_sim_rd_resp;       // input[1:0] 
 
-  wire [31:0] afi_sim_wr_address;    // output[31:0] SuppressThisWarning VEditor - not used - just view
+  wire [31:0] afi_sim_wr_address;    // output[31:0]
   wire [ 5:0] afi_sim_wid;           // output[5:0]  SuppressThisWarning VEditor - not used - just view
   wire        afi_sim_wr_valid;      // output
   wire        afi_sim_wr_ready;      // input
 //  reg         afi_sim_wr_ready;      // input
-  wire [63:0] afi_sim_wr_data;       // output[63:0] SuppressThisWarning VEditor - not used - just view
-  wire [ 7:0] afi_sim_wr_stb;        // output[7:0]  SuppressThisWarning VEditor - not used - just view
+  wire [63:0] afi_sim_wr_data;       // output[63:0]
+  wire [ 7:0] afi_sim_wr_stb;        // output[7:0]
   wire [ 3:0] afi_sim_bresp_latency; // input[3:0] 
 //  reg  [ 3:0] afi_sim_bresp_latency; // input[3:0] 
   wire [ 2:0] afi_sim_wr_cap;        // output[2:0]  SuppressThisWarning VEditor - not used - just view
   wire [ 3:0] afi_sim_wr_qos;        // output[3:0]  SuppressThisWarning VEditor - not used - just view
 
   assign HCLK = dut.ps7_i.SAXIHP3ACLK; // shortcut name
+  assign HRST = dut.sata_top.hrst;  // shortcut name
+/*
+//  assign HCLK = dut.ps7_i.SAXIHP3ACLK; // shortcut name
 // afi loopback
   assign #1 afi_sim_rd_data=  afi_sim_rd_ready?{2'h0,afi_sim_rd_address[31:3],1'h1,  2'h0,afi_sim_rd_address[31:3],1'h0}:64'bx;
   assign #1 afi_sim_rd_valid = afi_sim_rd_ready;
   assign #1 afi_sim_rd_resp = afi_sim_rd_ready?2'b0:2'bx;
   assign #1 afi_sim_wr_ready = afi_sim_wr_valid;
   assign #1 afi_sim_bresp_latency=4'h5; 
-
+*/
 // axi_hp register access
   // PS memory mapped registers to read/write over a separate simulation bus running at HCLK, no waits
   reg  [31:0] PS_REG_ADDR;
@@ -411,7 +415,7 @@ sata_device dev(
 simul_axi_hp_rd #(
         .HP_PORT(3)
     ) simul_axi_hp_rd_i (
-        .rst            (RST),                            // input
+        .rst            (HRST), // RST),                            // input
         .aclk           (dut.ps7_i.SAXIHP3ACLK),          // input
         .aresetn        (),                               // output
         .araddr         (dut.ps7_i.SAXIHP3ARADDR[31:0]),  // input[31:0] 
@@ -452,7 +456,7 @@ simul_axi_hp_rd #(
 simul_axi_hp_wr #(
         .HP_PORT(3)
     ) simul_axi_hp_wr_i (
-        .rst            (RST), // input
+        .rst            (HRST), // RST), // input
         .aclk           (dut.ps7_i.SAXIHP3ACLK),          // input
         .aresetn        (),                               // output
         .awaddr         (dut.ps7_i.SAXIHP3AWADDR),        // input[31:0] 
@@ -617,6 +621,7 @@ always #(CLKIN_PERIOD/2) CLK = ~CLK;
 
 // Simulation 
 `include "includes/ahci_localparams.vh" // SuppressThisWarning VEditor - many unused defines
+`include "includes/fis_types.vh"       // SuppressThisWarning VEditor - some unused defines
 localparam MAXIGP1 = 32'h80000000; // Start of the MAXIGP1 address range (use ahci_localparams.vh offsets)
 
     task maxigp1_write_single; // address in bytes, not words
@@ -647,9 +652,10 @@ localparam MAXIGP1 = 32'h80000000; // Start of the MAXIGP1 address range (use ah
 
     task maxigp1_print;
         input [31:0] address;
+        input [319:0] msg;
         begin
             read_and_wait (address + MAXIGP1);
-            $display ("%x -> %x @ %t",address + MAXIGP1, registered_rdata,$time);
+            $display ("%x -> %x (%s)@ %t",address + MAXIGP1, registered_rdata,msg,$time);
         end
     endtask
 
@@ -659,6 +665,69 @@ localparam HBA_PORT0_OFFS32  = 'h40;
 localparam PXSIG_OFFS32 = HBA_OFFS32 + HBA_PORT0_OFFS32 + 'h9; 
 localparam PXTFD_OFFS32 = HBA_OFFS32 + HBA_PORT0_OFFS32 + 'h8;
 
+localparam SYS_MEM_START = 32'h3fffc000; // 16384 bytes (4096 DWORDs of teh system memory for R/W over AXI_HP) 
+localparam SYS_MEM_SIZE =  16384; // bytes - size of system memory 
+// realtive to the system memory area
+localparam COMMAND_TABLE = 32'h3f00; // 256 bytes for a command table in the system memory
+localparam IDENTIFY_BUF =  32'h3d00; // 512 bytes for a command table in the system memory
+localparam PRD_OFFSET = 'h80;        // start of PRD table - 128-th byte in command table
+localparam ATA_IDFY = 'hec; // Identify command
+
+    reg  [31:0] sysmem[0:4095]; 
+
+    // connect system memory ty AXI_NP RD and WR channels
+//  assign HCLK = dut.ps7_i.SAXIHP3ACLK; // shortcut name
+// afi loopback
+    assign #1 afi_sim_rd_valid = afi_sim_rd_ready;
+    assign #1 afi_sim_rd_resp = afi_sim_rd_ready?2'b0:2'bx;
+    assign #1 afi_sim_wr_ready = afi_sim_wr_valid;
+    assign #1 afi_sim_bresp_latency=4'h5; 
+//  assign #1 afi_sim_rd_data=  afi_sim_rd_ready?{2'h0,afi_sim_rd_address[31:3],1'h1,  2'h0,afi_sim_rd_address[31:3],1'h0}:64'bx;
+    wire MEM_SEL = (afi_sim_rd_address[31:3] >= (SYS_MEM_START >> 3)) && (afi_sim_rd_address[31:3] < ((SYS_MEM_START + SYS_MEM_SIZE) >> 3));
+    wire [31:2] sysmem_dworda_rd = {(afi_sim_rd_address[31:3] - (SYS_MEM_START >> 3)),1'b0};
+    assign #1 afi_sim_rd_data=  afi_sim_rd_ready?(MEM_SEL? {sysmem[sysmem_dworda_rd[31:2]+1], sysmem[sysmem_dworda_rd[31:2]]} :64'bx):64'bz;
+    wire [31:2] sysmem_dworda_wr = {(afi_sim_wr_address[31:3] - (SYS_MEM_START >> 3)),1'b0};
+    wire [31:0] sysmem_di_low =  ({{8{afi_sim_wr_stb[3]}},{8{afi_sim_wr_stb[2]}},{8{afi_sim_wr_stb[1]}},{8{afi_sim_wr_stb[0]}}} &
+                                (sysmem[sysmem_dworda_wr[31:2]] ^ afi_sim_wr_data[31:0])) ^ sysmem[sysmem_dworda_wr[31:2]];
+    
+    wire [31:0] sysmem_di_high = ({{8{afi_sim_wr_stb[7]}},{8{afi_sim_wr_stb[6]}},{8{afi_sim_wr_stb[5]}},{8{afi_sim_wr_stb[4]}}} &
+                                (sysmem[sysmem_dworda_wr[31:2]+1] ^ afi_sim_wr_data[63:32])) ^ sysmem[sysmem_dworda_wr[31:2]+1];
+    always @ (posedge HCLK) begin
+        if (|afi_sim_wr_stb[3:0]) sysmem[sysmem_dworda_wr[31:2]    ] <= sysmem_di_low;
+        if (|afi_sim_wr_stb[7:4]) sysmem[sysmem_dworda_wr[31:2] + 1] <= sysmem_di_high;
+    end
+    
+    
+    task setup_pio_read_identify_command;
+        input integer prd_int; // [0] - first prd interrupt, ... [31] - 31-st
+        integer i;
+        begin
+            // clear system memory for command
+            for (i = 0; i < 63; i = i+1)  sysmem[(COMMAND_TABLE >> 2) + i] = 0;
+            // fill ATA command 
+            sysmem[(COMMAND_TABLE >> 2) + 0] = FIS_H2DR |         // FIS type - H2D register (0x27)
+                                               ('h80 << 8) |      // set C = 1
+                                               (ATA_IDFY << 16) | // Command = 0xEC (IDFY)
+                                              ( 0 << 24);        // features = 0 ?
+            // All other 4 DWORDs are 0 for this command
+            // Set PRDT (single item) TODO: later check multiple small ones
+            sysmem[((COMMAND_TABLE + PRD_OFFSET) >> 2) + 0] = SYS_MEM_START + IDENTIFY_BUF;
+            sysmem[((COMMAND_TABLE + PRD_OFFSET) >> 2) + 3] = (prd_int[0] << 31) | 511; // 512 bytes in this PRDT
+            // Setup command header
+            maxigp1_writep       ((CLB_OFFS32 + 0) << 2,     (5 <<  0) | // 'CFL' - number of DWORDs in thes CFIS
+                                                         (0 <<  5) | // 'A' Not ATAPI
+                                                         (0 <<  6) | // 'W' Not write to device
+                                                         (1 <<  7) | // 'P' Prefetchable = 1
+                                                         (0 <<  8) | // 'R' Not a Reset
+                                                         (0 <<  9) | // 'B' Not a BIST
+                                                         (0 << 10) | // 'C' Do not clear BSY/CI after transmitting this command
+                                                         (1 << 16)); // 'PRDTL' - number of PRDT entries (just one)
+            maxigp1_writep       ((CLB_OFFS32 +2 ) << 2, (SYS_MEM_START + COMMAND_TABLE) & 32'hffffffc0); // 'CTBA' - Command table base address
+            // Set Command Issued
+            maxigp1_writep       (HBA_PORT__PxCI__CI__ADDR << 2, 1); // 'PxCI' - Set 'Command issue' for slot 0 (the only one)
+            // relax and enjoy
+        end
+    endtask
 initial begin //Host
     wait (!RST);
 //reg [639:0] TESTBENCH_TITLE = "RESET"; // to show human-readable state in the GTKWave
@@ -676,27 +745,27 @@ initial begin //Host
     maxigp1_writep       ((CLB_OFFS32+1) << 2, 'h87654321); // 
 
 
-    maxigp1_print        (PXSIG_OFFS32 << 2); // OK to read wrong - it is RO with default 'hffffffff
-    maxigp1_print        (PXTFD_OFFS32 << 2); // OK to read wrong - it is RO with default 0
-    maxigp1_print        (CLB_OFFS32     << 2); // 
-    maxigp1_print        ((CLB_OFFS32+1) << 2); // 
+    maxigp1_print        (PXSIG_OFFS32 << 2,"PXSIG_OFFS32"); // OK to read wrong - it is RO with default 'hffffffff
+    maxigp1_print        (PXTFD_OFFS32 << 2,"PXTFD_OFFS32"); // OK to read wrong - it is RO with default 0
+    maxigp1_print        (CLB_OFFS32     << 2,"CLB_OFFS32"); // 
+    maxigp1_print        ((CLB_OFFS32+1) << 2,"CLB_OFFS32+1"); // 
 
 
 
     
-    maxigp1_print        (PCI_Header__CAP__CAP__ADDR << 2);
-    maxigp1_print        (GHC__PI__PI__ADDR << 2);
-    maxigp1_print        (HBA_PORT__PxCMD__ICC__ADDR << 2);
-    maxigp1_print        (GHC__GHC__IE__ADDR << 2);
+    maxigp1_print        (PCI_Header__CAP__CAP__ADDR << 2,"PCI_Header__CAP__CAP__ADDR");
+    maxigp1_print        (GHC__PI__PI__ADDR << 2,"GHC__PI__PI__ADDR");
+    maxigp1_print        (HBA_PORT__PxCMD__ICC__ADDR << 2,"HBA_PORT__PxCMD__ICC__ADDR");
+    maxigp1_print        (GHC__GHC__IE__ADDR << 2,"GHC__GHC__IE__ADDR");
     maxigp1_writep       (GHC__GHC__IE__ADDR << 2, GHC__GHC__IE__MASK); // enable interrupts (global)
-    maxigp1_print        (HBA_PORT__PxIE__CPDE__ADDR << 2);
+    maxigp1_print        (HBA_PORT__PxIE__CPDE__ADDR << 2,"HBA_PORT__PxIE__CPDE__ADDR");
 //    maxigp1_writep       (HBA_PORT__PxIE__CPDE__ADDR << 2, ~0); // allow all interrupts
     maxigp1_writep       (HBA_PORT__PxIE__CPDE__ADDR << 2, HBA_PORT__PxIE__DHRE__MASK); // =='h1: allow DHRS only interrupts (D2HR received (signature)
-    maxigp1_print        (GHC__GHC__IE__ADDR << 2);
-    maxigp1_print        (HBA_PORT__PxIE__CPDE__ADDR << 2);
+    maxigp1_print        (GHC__GHC__IE__ADDR << 2,"GHC__GHC__IE__ADDR");
+    maxigp1_print        (HBA_PORT__PxIE__CPDE__ADDR << 2,"HBA_PORT__PxIE__CPDE__ADDR");
     
-    maxigp1_print        (PXSIG_OFFS32 << 2);
-    maxigp1_print        (PXTFD_OFFS32 << 2);
+    maxigp1_print        (PXSIG_OFFS32 << 2,"PXSIG_OFFS32");
+    maxigp1_print        (PXTFD_OFFS32 << 2,"PXTFD_OFFS32");
     
     
     TESTBENCH_TITLE = "Waiting D2H IRQ";
@@ -704,9 +773,28 @@ initial begin //Host
     wait (IRQ);
     TESTBENCH_TITLE = "Got D2H IRQ";
     $display("[Testbench]:       %s @%t", TESTBENCH_TITLE, $time);
-    maxigp1_print        (PXSIG_OFFS32 << 2);
-    maxigp1_print        (PXTFD_OFFS32 << 2);
-    
+    maxigp1_print        (GHC__IS__IPS__ADDR << 2,"GHC__IS__IPS__ADDR"); // Should be 1 (port 0)
+    maxigp1_writep       (GHC__IS__IPS__ADDR << 2, 1); // clear that interrupt
+    maxigp1_print        (GHC__IS__IPS__ADDR << 2,"GHC__IS__IPS__ADDR"); // Now it should be 0
+    
+    maxigp1_print        (HBA_PORT__PxIS__DHRS__ADDR << 2,"HBA_PORT__PxIS__DHRS__ADDR"); // It should be 400041 - DHR inerrupt (and others)
+    maxigp1_writep       (HBA_PORT__PxIS__DHRS__ADDR << 2, HBA_PORT__PxIS__DHRS__MASK); // clear that interrupt
+    maxigp1_print        (HBA_PORT__PxIS__DHRS__ADDR << 2,"HBA_PORT__PxIS__DHRS__ADDR"); // Now it should be 0400040 (DHR cleared)
+//HBA_PORT__PxIS__DHRS__ADDR    
+
+    maxigp1_print        (PXSIG_OFFS32 << 2,"PXSIG_OFFS32");
+    maxigp1_print        (PXTFD_OFFS32 << 2,"PXTFD_OFFS32");
+    maxigp1_print        (HBA_PORT__PxSERR__DIAG__X__ADDR,"HBA_PORT__PxSERR__DIAG__X__ADDR");
+    maxigp1_print        (HBA_PORT__PxCMD__FRE__ADDR << 2,"HBA_PORT__PxCMD__FRE__ADDR");
+    maxigp1_writep       (HBA_PORT__PxCMD__FRE__ADDR << 2, HBA_PORT__PxCMD__FRE__MASK); // Enable FR, some RO bits already set 
+    maxigp1_print        (HBA_PORT__PxCMD__FRE__ADDR << 2,"HBA_PORT__PxCMD__FRE__ADDR");
+    maxigp1_writep       (HBA_PORT__PxCMD__FRE__ADDR << 2, HBA_PORT__PxCMD__FRE__MASK |HBA_PORT__PxCMD__ST__MASK); // Enable FR and ST 
+    maxigp1_print        (HBA_PORT__PxCMD__FRE__ADDR << 2,"HBA_PORT__PxCMD__FRE__ADDR");
+    
+    maxigp1_print        (HBA_PORT__PxSSTS__DET__ADDR << 2,"HBA_PORT__PxSSTS__DET__ADDR");
+    
+    setup_pio_read_identify_command(1); // prdt interrupt for entry 0
+    maxigp1_print        (HBA_PORT__PxCI__CI__ADDR << 2,"HBA_PORT__PxCI__CI__ADDR");
 //    $finish;
 //HBA_PORT__PxIE__DHRE__MASK = 'h1;
 end

tb_ahci_01.sav

 [*]
 [*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
-[*] Mon Jan 25 02:04:39 2016
+[*] Tue Jan 26 02:29:04 2016
 [*]
-[dumpfile] "/home/andrey/git/x393_sata/simulation/tb_ahci-20160124173705418.fst"
-[dumpfile_mtime] "Mon Jan 25 00:37:59 2016"
-[dumpfile_size] 6252216
+[dumpfile] "/home/andrey/git/x393_sata/simulation/tb_ahci-20160125190408414.fst"
+[dumpfile_mtime] "Tue Jan 26 02:05:07 2016"
+[dumpfile_size] 6202198
 [savefile] "/home/andrey/git/x393_sata/tb_ahci_01.sav"
-[timestart] 213500
-[size] 1823 1173
+[timestart] 0
+[size] 1823 1180
 [pos] 1951 0
-*-15.936193 418000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+*-23.114683 19004242 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [treeopen] tb_ahci.
 [treeopen] tb_ahci.dev.
 [treeopen] tb_ahci.dev.phy.
@@ -21,13 +21,16 @@
 [treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.
 [treeopen] tb_ahci.dut.sata_top.ahci_top_i.
 [treeopen] tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.
+[treeopen] tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.
 [treeopen] tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.
+[treeopen] tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.
 [treeopen] tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.
 [treeopen] tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.
 [treeopen] tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.ahci_regs_i.
 [treeopen] tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.axibram_read_i.
 [treeopen] tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.axibram_write_i.
-[sst_width] 275
+[treeopen] tb_ahci.simul_axi_hp_rd_i.
+[sst_width] 420
 [signals_width] 254
 [sst_expanded] 1
 [sst_vpaned_height] 625
@@ -82,7 +85,6 @@ tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.bram_addr[9:0]
 tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.bram_wdata[31:0]
 tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.bram_wdata_r[31:0]
 tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.ahci_regs_di[31:0]
-@23
 tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.wmask[31:0]
 @28
 tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.ahci_regs_i.en_a
@@ -246,6 +248,7 @@ tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.ahci_regs_i.en_b
 @22
 tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.ahci_regs_i.we_b[3:0]
 tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.ahci_regs_i.we_b4[3:0]
+tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.ahci_regs_i.data_in32_b[31:0]
 @1000200
 -ahci_regs_i
 @c00200
@@ -429,7 +432,7 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.tfd_err[7:0]
 -ahci_fis_receive
 @1401200
 -ahci_top
-@c00200
+@800200
 -ahci_ctrl_stat
 @22
 tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.regs_addr[9:0]
@@ -475,43 +478,6 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.regs_we
 tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.update_HBA_PORT__PxSERR
 tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.update_HBA_PORT__PxSSTS
 @c00022
-tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
-@28
-(0)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
-(1)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
-(2)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
-(3)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
-(4)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
-(5)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
-(6)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
-(7)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
-(8)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
-(9)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
-(10)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
-(11)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
-(12)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
-(13)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
-(14)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
-(15)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
-(16)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
-(17)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
-(18)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
-(19)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
-(20)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
-(21)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
-(22)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
-(23)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
-(24)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
-(25)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
-(26)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
-(27)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
-(28)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
-(29)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
-(30)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
-(31)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
-@1401200
--group_end
-@c00022
 tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.serr[31:0]
 @28
 (0)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.serr[31:0]
@@ -551,7 +517,7 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.serr[31:0]
 @28
 tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.pxci0_clear
 tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.pxci_changed
-@c00022
+@800022
 tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.regs_changed[5:0]
 @28
 (0)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.regs_changed[5:0]
@@ -560,9 +526,9 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.regs_changed[5:0]
 (3)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.regs_changed[5:0]
 (4)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.regs_changed[5:0]
 (5)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.regs_changed[5:0]
-@1401200
+@1001200
 -group_end
-@c00022
+@800022
 tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.update_first[5:0]
 @28
 (0)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.update_first[5:0]
@@ -571,10 +537,49 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.update_first[5:0]
 (3)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.update_first[5:0]
 (4)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.update_first[5:0]
 (5)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.update_first[5:0]
-@1401200
+@1001200
 -group_end
 @200
 -
+@22
+tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSSTS_r[11:0]
+@c00022
+tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
+@28
+(0)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
+(1)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
+(2)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
+(3)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
+(4)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
+(5)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
+(6)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
+(7)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
+(8)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
+(9)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
+(10)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
+(11)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
+(12)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
+(13)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
+(14)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
+(15)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
+(16)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
+(17)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
+(18)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
+(19)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
+(20)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
+(21)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
+(22)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
+(23)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
+(24)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
+(25)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
+(26)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
+(27)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
+(28)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
+(29)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
+(30)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
+(31)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
+@1401200
+-group_end
 @c00022
 tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIE_r[31:0]
 @28
@@ -612,7 +617,7 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIE_r[31:0]
 (31)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIE_r[31:0]
 @1401200
 -group_end
-@800022
+@c00022
 tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]
 @28
 (0)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]
@@ -647,8 +652,13 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]
 (29)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]
 (30)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]
 (31)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]
-@1001200
+@1401200
 -group_end
+@28
+tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.pxci0_clear
+tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.swr_HBA_PORT__PxCI
+tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.pxci0
+tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.pxci_changed
 @c00022
 tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.sirq[31:0]
 @28
@@ -725,6 +735,7 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.ssts_spd_gen2
 tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.ssts_spd_gen3
 @1401200
 -ssts
+@1000200
 -ahci_ctrl_stat
 @c00200
 -axi_ahci_regs
@@ -739,7 +750,7 @@ tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.any_access
 tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.set_port_rst
 @1401200
 -axi_ahci_regs
-@c00200
+@800200
 -ahci_fsm
 @c00022
 tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pgm_addr[9:0]
@@ -788,9 +799,25 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.fsm_jump[2:0]
 tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.fsm_pre_act_w
 @1001200
 -group_end
+@28
+tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pcmd_st
+tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.tfd_bsy
+tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.tfd_drq
+@22
+tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.tfd_sts[7:0]
+@28
+tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.fis_first_vld
+@c00200
+-other
+@28
+tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.get_fis
+tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.is_FIS_HEAD
+tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.fis_end_w
 @200
 -
-@800200
+@1401200
+-other
+@c00200
 -actions
 @28
 tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pfsm_started
@@ -805,8 +832,124 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.sirq_PC
 tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.get_rfis
 tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.update_sig
 tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.update_err_sts
-@1000200
+@1401200
 -actions
+@c00200
+-conditions
+@22
+tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.condition_mux_i.sel[7:0]
+@c00022
+tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.condition_mux_i.cond_r[5:0]
+@28
+(0)tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.condition_mux_i.cond_r[5:0]
+(1)tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.condition_mux_i.cond_r[5:0]
+(2)tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.condition_mux_i.cond_r[5:0]
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+@200
+-
+@1000200
+-raddr_fifo
+@28
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+@28
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+@28
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+@22
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+@22
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+@28
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+@200
+-
+@28
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+-simul_axi_hp_rd
+-top
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+-
+@1000200
+-ahci_dma
 @c00200
 -link
 @28