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Commit 17e832f8 authored by Andrey Filippov's avatar Andrey Filippov
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Working on AHCI FSM code generator

parent 4bf4f348
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Showing with 945 additions and 210 deletions
ahci/ahci_ctrl_stat.v
View file @ 17e832f8
......@@ -124,7 +124,7 @@ module ahci_ctrl_stat #(
input ssts_det_ndnp, // no device detected, phy communication not established
input ssts_det_dnp, // device detected, but phy communication not established
input ssts_det_dp, // device detected, phy communication established
input ssts_det_offline, // device offline
input ssts_det_offline, // device offline or BIST
output [3:0] ssts_det, // current value of PxSSTS.DET
// SCR2:SControl (written by software only)
......
ahci/ahci_dma.v
View file @ 17e832f8
......@@ -65,11 +65,11 @@ module ahci_dma (
// After the first 0x80 bytes of the Command Table are read out, this module will read/process PRDs,
// not forwarding them to the output
output prd_done, // prd done (regardless of the interrupt) - data transfer of one PRD is finished (any direction)
output prd_irq, // prd interrupt, if enabled
output prd_done, // @mclk prd done (regardless of the interrupt) - data transfer of one PRD is finished (any direction)
input prd_irq_clear, // reset pending prd_irq
output reg prd_irq_pend, // prd interrupt pending. This is just a condition for irq - actual will be generated after FIS OK
output reg cmd_busy, // all commands
output cmd_done,
output cmd_done, // @ mclk
// Data System memory -> HBA interface @ mclk
output [31:0] sys_out, // 32-bit data from the system memory to HBA (dma data)
......@@ -81,6 +81,8 @@ module ahci_dma (
output sys_nfull, // internal FIFO has room for more data (will decide - how big reserved space to keep)
input sys_we,
output extra_din, // all DRDs are transferred to memory, but FIFO has some data. Valid when transfer is stopped
// axi_hp signals write channel
// write address
output [31:0] afi_awaddr,
......@@ -228,8 +230,10 @@ module ahci_dma (
reg [3:0] dev_rd_id;
reg [5:0] afi_id; // common for 3 channels
assign prd_done = done_dev_wr || done_dev_rd;
assign prd_irq = data_irq && prd_done;
wire fifo_nempty_mclk;
reg en_extra_din_r;
// assign prd_done = done_dev_wr || done_dev_rd;
assign cmd_done_hclk = ((ct_busy_r==2'b10) && (prdtl_mclk == 0)) || done_flush || done_dev_rd;
assign ct_done = (ct_busy_r == 2'b10);
assign first_prd_fetch = ct_over_prd_enabled == 2'b01;
......@@ -269,7 +273,7 @@ module ahci_dma (
assign afi_arburst = 2'h1;
assign afi_arqos = 4'h0;
assign afi_rdissuecap1en = 1'b0;
assign extra_din = en_extra_din_r && fifo_nempty_mclk;
always @ (posedge mclk) begin
if (ct_re) ct_data <= ct_data_ram[ct_addr];
if (ctba_ld) ctba_r <= ctba[31:7];
......@@ -292,6 +296,13 @@ module ahci_dma (
prd_start_r <= prd_start;
if (mrst || prd_irq_clear ||cmd_start || cmd_abort) prd_irq_pend <= 0;
else if (data_irq && prd_done) prd_irq_pend <= 1;
if (mrst || cmd_start || cmd_abort) en_extra_din_r <= 0;
else if (cmd_done) en_extra_din_r <= 1;
end
......@@ -472,6 +483,7 @@ module ahci_dma (
.dout_wstb (afi_wstb4), // output[3:0] reg
.done (done_dev_rd), // output reg
.busy (), // output
.fifo_nempty_mclk (fifo_nempty_mclk), // output reg
.din (sys_in), // input[31:0]
.din_rdy (sys_nfull), // output
.din_avail (sys_we) // input
......@@ -535,5 +547,19 @@ module ahci_dma (
.busy() // output
);
pulse_cross_clock #(
.EXTRA_DLY(0)
) prd_done_mclk_i (
.rst (hrst), // input
.src_clk (hclk), // input
.dst_clk (mclk), // input
.in_pulse (done_dev_wr || done_dev_rd), // input
.out_pulse (prd_done), // output
.busy() // output
);
endmodule
ahci/ahci_dma_wr_fifo.v
View file @ 17e832f8
......@@ -59,7 +59,7 @@ module ahci_dma_wr_fifo#(
// last_prd was not set
output busy,
// output done_flush, // finished last PRD (indicated by last_prd @ start), data left module
output reg fifo_nempty_mclk, // to detect extra data from FIS, has some latency - only valid after read is stopped
// mclk domain
input [31:0] din,
output din_rdy, // can accept data from HBA (multiple dwords, so reasonable latency is OK)
......@@ -268,6 +268,8 @@ module ahci_dma_wr_fifo#(
if (fifo_wr && !waddr[0]) fifo0_ram[waddr[ADDRESS_BITS:1]] <= din;
if (fifo_wr && waddr[0]) fifo1_ram[waddr[ADDRESS_BITS:1]] <= din;
fifo_nempty_mclk <= (fifo_full [raddr[ADDRESS_BITS:1]] ^ raddr[ADDRESS_BITS]); // only valid after read is stopped
end
......
ahci/ahci_fis_receive.v
View file @ 17e832f8
This diff is collapsed.
ahci/ahci_fis_transmit.v
View file @ 17e832f8
......@@ -75,7 +75,7 @@ module ahci_fis_transmit #(
input dma_ct_busy, // dma module is busy reading command table from the system memory
// issue dma_prd_start same time as dma_start if prefetch enabled, otherwise with cfis_xmit
output reg dma_prd_start, // at or after cmd_start - enable reading PRD/data (if any) ch_prdtl should be valid, twice - OK
output reg dma_cmd_abort, // try to abort a command TODO: Implement
output reg dma_cmd_abort, // try to abort a command
// reading out command table data from DMA module
output reg [ 4:0] ct_addr, // DWORD address
......
ahci/ahci_fsm.v
View file @ 17e832f8
......@@ -148,11 +148,16 @@ module ahci_fsm
// inputs from the DMA engine
input dma_prd_done, // output (finished next prd)
input dma_prd_irq, // output (finished next prd and prd irq is enabled)
output dma_prd_irq_clear, // reset pending prd_irq
input dma_prd_irq_pend, // prd interrupt pending. This is just a condition for irq - actual will be generated after FIS OK
input dma_cmd_busy, // output reg (DMA engine is processing PRDs)
input dma_cmd_done, // output (last PRD is over)
// Communication with ahci_fis_receive (some are unused
// Communication with ahci_fis_receive (some are unused)
// Debug features
input fis_first_invalid, // Some data available from FIFO, but not FIS head
output fis_first_flush, // Skip FIFO data until empty or FIS head
input fis_first_vld, // fis_first contains valid FIS header, reset by 'get_*'
input [7:0] fis_type, // FIS type (low byte in the first FIS DWORD), valid with 'fis_first_vld'
input [7:0] bist_bits, // bits that define built-in self test
......@@ -170,6 +175,7 @@ module ahci_fsm
input fis_ok, // FIS done, checksum OK reset by starting a new get FIS
input fis_err, // FIS done, checksum ERROR reset by starting a new get FIS
input fis_ferr, // FIS done, fatal error - FIS too long
input fis_extra, // more data got from FIS than DMA can accept. Does not deny fis_ok. May have latency
output set_update_sig, // when set, enables get_sig (and resets itself)
input pUpdateSig, // state variable
......@@ -204,6 +210,7 @@ module ahci_fsm
input pio_i, // value of "I" field in received PIO Setup FIS
input pio_d, // value of "D" field in received PIO Setup FIS
input [7:0] pio_es, // value of PIO E_Status
input sactive0, // bit 0 of sActive DWORD received in SDB FIS
// Using even word count (will be rounded up), partial DWORD (last) will be handled by PRD length if needed
input [31:2] xfer_cntr, // transfer counter in words for both DMA (31 bit) and PIO (lower 15 bits), updated after decr_dwc
input xfer_cntr_zero,// valid next cycle
......
ahci/ahci_top.v
View file @ 17e832f8
......@@ -212,7 +212,8 @@ module ahci_top#(
wire [ 1:0] dma_ct_re; // input
wire [31:0] dma_ct_data; // output[31:0] reg
wire dma_prd_done; // output (finished next prd)
wire dma_prd_irq; // output (finished next prd and prd irq is enabled)
wire dma_prd_irq_clear; // reset pending prd_irq
wire dma_prd_irq_pend; // prd interrupt pending. This is just a condition for irq - actual will be generated after FIS OK
wire dma_cmd_busy; // output reg (DMA engine is processing PRDs)
wire dma_cmd_done; // output (last PRD is over)
wire [31:0] dma_dout; // output[31:0]
......@@ -220,10 +221,17 @@ module ahci_top#(
wire dma_re; // input
wire dma_in_ready; // output
wire dma_we; // input
wire dma_extra_din; // all DRDs are transferred to memory, but FIFO has some data. Valid when transfer is stopped
// ---------------------------------------
// fsm <-> ahc_fis_receive
// fsm ->
wire frcv_first_vld;
// To debug/recover -
wire frcv_first_invalid; // Some data available from FIFO, but not FIS head
wire frcv_first_flush; // Skip FIFO data until empty or FIS head
wire frcv_get_dsfis;
wire frcv_get_psfis;
wire frcv_get_rfis;
......@@ -252,6 +260,7 @@ module ahci_top#(
wire frcv_ok; // FIS done, checksum OK reset by starting a new get FIS
wire frcv_err; // FIS done, checksum ERROR reset by starting a new get FIS
wire frcv_ferr; // FIS done, fatal error - FIS too long
wire frcv_extra; // DMA all transferred, but some data is still in left. . Does not deny frcv_ok
wire frcv_set_update_sig; // when set, enables get_sig (and resets itself)
wire frcv_pUpdateSig; // state variable
......@@ -270,8 +279,8 @@ module ahci_top#(
wire pio_i; // value of "I" field in received PIO Setup FIS
wire pio_d; // value of "D" field in received PIO Setup FIS
wire [7:0] pio_es; // value of PIO E_Status
wire pPioXfer;
wire sactive0; // bit 0 of sActive DWORD received in SDB FIS
// Using even word count (will be rounded up), partial DWORD (last) will be handled by PRD length if needed
wire [31:0] xfer_cntr;
......@@ -503,10 +512,15 @@ module ahci_top#(
.pxci0 (pxci0), // input
.dma_prd_done (dma_prd_done), // input
.dma_prd_irq (dma_prd_irq), // input
.dma_prd_irq_clear (dma_prd_irq_clear), // output
.dma_prd_irq_pend (dma_prd_irq_pend), // input
.dma_cmd_busy (dma_cmd_busy), // input
.dma_cmd_done (dma_cmd_done), // input
.fis_first_invalid (frcv_first_invalid),// input
.fis_first_flush (frcv_first_flush), // output
.fis_first_vld (frcv_first_vld), // input
.fis_type (d2h_data[7:0]), // input[7:0] FIS type (low byte in the first FIS DWORD), valid with 'fis_first_vld'
.bist_bits (d2h_data[23:16]), // bits that define built-in self test
......@@ -523,6 +537,7 @@ module ahci_top#(
.fis_ok (frcv_ok), // input
.fis_err (frcv_err), // input
.fis_ferr (frcv_ferr), // input
.fis_extra (frcv_extra || dma_extra_din), // input // more data got from FIS than DMA can accept. Does not deny fis_ok. May have latency
.set_update_sig (frcv_set_update_sig),// output
.pUpdateSig (frcv_pUpdateSig), // input
......@@ -552,6 +567,7 @@ module ahci_top#(
.dma_d (dma_d), // input
.pio_i (pio_i), // input
.pio_d (pio_d), // input
.sactive0 (sactive0), // input
.pio_es (pio_es), // input[7:0]
.xfer_cntr (xfer_cntr[31:2]), // input[31:2]
.xfer_cntr_zero (xfer_cntr_zero), // input
......@@ -746,7 +762,10 @@ module ahci_top#(
.ct_re (dma_ct_re[0]), // input
.ct_data (dma_ct_data), // output[31:0] reg
.prd_done (dma_prd_done), // output
.prd_irq (dma_prd_irq), // output
.prd_irq_clear (dma_prd_irq_clear),// input
.prd_irq_pend (dma_prd_irq_pend), // output reg
.cmd_busy (dma_cmd_busy), // output reg
.cmd_done (dma_cmd_done), // output
.sys_out (dma_dout), // output[31:0]
......@@ -755,7 +774,7 @@ module ahci_top#(
.sys_in (d2h_data), // input[31:0]
.sys_nfull (dma_in_ready), // output
.sys_we (dma_we), // input
.extra_din (dma_extra_din), // output reg
.afi_awaddr (afi_awaddr), // output[31:0]
.afi_awvalid (afi_awvalid), // output
.afi_awready (afi_awready), // input
......@@ -809,6 +828,8 @@ module ahci_top#(
.mclk (mclk), // input
.fis_first_vld (frcv_first_vld), // output reg
.fis_first_invalid (frcv_first_invalid), // output
.fis_first_flush (frcv_first_flush), // input
.get_dsfis (frcv_get_dsfis), // input
.get_psfis (frcv_get_psfis), // input
......@@ -824,6 +845,9 @@ module ahci_top#(
.fis_err (frcv_err), // output reg
.fis_ferr (frcv_ferr), // output
.dma_prds_done (dma_cmd_done), // input
.fis_extra (frcv_extra), // output
.set_update_sig (frcv_set_update_sig), // input
.pUpdateSig (frcv_pUpdateSig), // output
.sig_available (frcv_sig_available), // output reg
......@@ -855,6 +879,7 @@ module ahci_top#(
.pio_i (pio_i), // output reg
.pio_d (pio_d), // output reg
.pio_es (pio_es), // output[7:0] reg
.sactive0 (sactive0), // output reg
.xfer_cntr (xfer_cntr[31:2]), // output[31:2]
.xfer_cntr_zero (xfer_cntr_zero), // output reg
.data_in_dwords (data_in_dwords), // output[11:0]
......
generated/action_decoder.v 0 → 100644
View file @ 17e832f8
/*******************************************************************************
* Module: action_decoder
* Date:2016-01-18
* Author: auto-generated file, see ahci_fsm_sequence.py
* Description: Decode sequencer code to 1-hot actions
*******************************************************************************/
`timescale 1ns/1ps
module action_decoder (
input clk,
input enable,
input [10:0] data,
output reg PXSERR_DIAG_X,
output reg SIRQ_DHR,
output reg SIRQ_DP,
output reg SIRQ_DS,
output reg SIRQ_IF,
output reg SIRQ_PS,
output reg SIRQ_SDB,
output reg SIRQ_TFE,
output reg SIRQ_UF,
output reg PFSM_STARTED,
output reg PCMD_CR_CLEAR,
output reg PCMD_CR_SET,
output reg PXCI0_CLEAR,
output reg PXSSTS_DET_1,
output reg SSTS_DET_OFFLINE,
output reg SET_UPDATE_SIG,
output reg UPDATE_SIG,
output reg UPDATE_ERR_STS,
output reg UPDATE_PIO,
output reg UPDATE_PRDBC,
output reg CLEAR_BSY_DRQ,
output reg CLEAR_BSY_SET_DRQ,
output reg SET_BSY,
output reg SET_STS_7F,
output reg SET_STS_80,
output reg XFER_CNTR_CLEAR,
output reg DECR_DWC,
output reg FIS_FIRST_FLUSH,
output reg CLEAR_CMD_TO_ISSUE,
output reg DMA_ABORT,
output reg DMA_PRD_IRQ_CLEAR,
output reg XMIT_COMRESET,
output reg SEND_SYNC_ESC,
output reg SET_OFFLINE,
output reg R_OK,
output reg R_ERR,
output reg FETCH_CMD,
output reg ATAPI_XMIT,
output reg CFIS_XMIT,
output reg DX_XMIT,
output reg GET_DATA_FIS,
output reg GET_DSFIS,
output reg GET_IGNORE,
output reg GET_PSFIS,
output reg GET_RFIS,
output reg GET_SDBFIS,
output reg GET_UFIS);
always @(posedge clk) begin
PXSERR_DIAG_X <= enable && data[ 2] && data[ 0];
SIRQ_DHR <= enable && data[ 3] && data[ 0];
SIRQ_DP <= enable && data[ 4] && data[ 0];
SIRQ_DS <= enable && data[ 5] && data[ 0];
SIRQ_IF <= enable && data[ 6] && data[ 0];
SIRQ_PS <= enable && data[ 7] && data[ 0];
SIRQ_SDB <= enable && data[ 8] && data[ 0];
SIRQ_TFE <= enable && data[ 9] && data[ 0];
SIRQ_UF <= enable && data[10] && data[ 0];
PFSM_STARTED <= enable && data[ 2] && data[ 1];
PCMD_CR_CLEAR <= enable && data[ 3] && data[ 1];
PCMD_CR_SET <= enable && data[ 4] && data[ 1];
PXCI0_CLEAR <= enable && data[ 5] && data[ 1];
PXSSTS_DET_1 <= enable && data[ 6] && data[ 1];
SSTS_DET_OFFLINE <= enable && data[ 7] && data[ 1];
SET_UPDATE_SIG <= enable && data[ 8] && data[ 1];
UPDATE_SIG <= enable && data[ 9] && data[ 1];
UPDATE_ERR_STS <= enable && data[10] && data[ 1];
UPDATE_PIO <= enable && data[ 3] && data[ 2];
UPDATE_PRDBC <= enable && data[ 4] && data[ 2];
CLEAR_BSY_DRQ <= enable && data[ 5] && data[ 2];
CLEAR_BSY_SET_DRQ <= enable && data[ 6] && data[ 2];
SET_BSY <= enable && data[ 7] && data[ 2];
SET_STS_7F <= enable && data[ 8] && data[ 2];
SET_STS_80 <= enable && data[ 9] && data[ 2];
XFER_CNTR_CLEAR <= enable && data[10] && data[ 2];
DECR_DWC <= enable && data[ 4] && data[ 3];
FIS_FIRST_FLUSH <= enable && data[ 5] && data[ 3];
CLEAR_CMD_TO_ISSUE <= enable && data[ 6] && data[ 3];
DMA_ABORT <= enable && data[ 7] && data[ 3];
DMA_PRD_IRQ_CLEAR <= enable && data[ 8] && data[ 3];
XMIT_COMRESET <= enable && data[ 9] && data[ 3];
SEND_SYNC_ESC <= enable && data[10] && data[ 3];
SET_OFFLINE <= enable && data[ 5] && data[ 4];
R_OK <= enable && data[ 6] && data[ 4];
R_ERR <= enable && data[ 7] && data[ 4];
FETCH_CMD <= enable && data[ 8] && data[ 4];
ATAPI_XMIT <= enable && data[ 9] && data[ 4];
CFIS_XMIT <= enable && data[10] && data[ 4];
DX_XMIT <= enable && data[ 6] && data[ 5];
GET_DATA_FIS <= enable && data[ 7] && data[ 5];
GET_DSFIS <= enable && data[ 8] && data[ 5];
GET_IGNORE <= enable && data[ 9] && data[ 5];
GET_PSFIS <= enable && data[10] && data[ 5];
GET_RFIS <= enable && data[ 7] && data[ 6];
GET_SDBFIS <= enable && data[ 8] && data[ 6];
GET_UFIS <= enable && data[ 9] && data[ 6];
end
endmodule
generated/condition_mux.v 0 → 100644
View file @ 17e832f8
/*******************************************************************************
* Module: condition_mux
* Date:2016-01-18
* Author: auto-generated file, see ahci_fsm_sequence.py
* Description: Select condition
*******************************************************************************/
`timescale 1ns/1ps
module condition_mux (
input clk,
input [ 7:0] sel,
output condition,
input ST_NB_ND,
input PXCI0_NOT_CMDTOISSUE,
input PCTI_CTBAR_XCZ,
input PCTI_XCZ,
input NST_D2HR,
input NPD_NCA,
input CHW_DMAA,
input SCTL_DET_CHANGED_TO_4,
input SCTL_DET_CHANGED_TO_1,
input PXSSTS_DET_NE_3,
input PXSSTS_DET_EQ_1,
input NPCMD_FRE,
input FIS_OK,
input FIS_ERR,
input FIS_FERR,
input FIS_EXTRA,
input FIS_FIRST_INVALID,
input FR_D2HR,
input FIS_DATA,
input FIS_ANY,
input NB_ND_D2HR_PIO,
input D2HR,
input SDB,
input DMA_ACT,
input DMA_SETUP,
input BIST_ACT_FE,
input BIST_ACT,
input PIO_SETUP,
input NB_ND,
input TFD_STS_ERR,
input FIS_I,
input PIO_I,
input NPD,
input PIOX,
input XFER0,
input PIOX_XFER0,
input CTBAA_CTBAP,
input CTBAP,
input CTBA_B,
input CTBA_C,
input TX_ERR,
input SYNCESC_ERR,
input DMA_PRD_IRQ_PEND,
input X_RDY_COLLISION);
wire [43:0] masked;
reg [ 5:0] cond_r;
assign condition = |cond_r;
assign masked[ 0] = ST_NB_ND && sel[ 2] && sel[ 1] && sel[ 0];
assign masked[ 1] = PXCI0_NOT_CMDTOISSUE && sel[ 3] && sel[ 1] && sel[ 0];
assign masked[ 2] = PCTI_CTBAR_XCZ && sel[ 4] && sel[ 1] && sel[ 0];
assign masked[ 3] = PCTI_XCZ && sel[ 5] && sel[ 1] && sel[ 0];
assign masked[ 4] = NST_D2HR && sel[ 6] && sel[ 1] && sel[ 0];
assign masked[ 5] = NPD_NCA && sel[ 7] && sel[ 1] && sel[ 0];
assign masked[ 6] = CHW_DMAA && sel[ 3] && sel[ 2] && sel[ 0];
assign masked[ 7] = SCTL_DET_CHANGED_TO_4 && sel[ 4] && sel[ 2] && sel[ 0];
assign masked[ 8] = SCTL_DET_CHANGED_TO_1 && sel[ 5] && sel[ 2] && sel[ 0];
assign masked[ 9] = PXSSTS_DET_NE_3 && sel[ 6] && sel[ 2] && sel[ 0];
assign masked[10] = PXSSTS_DET_EQ_1 && sel[ 7] && sel[ 2] && sel[ 0];
assign masked[11] = NPCMD_FRE && sel[ 4] && sel[ 3] && sel[ 0];
assign masked[12] = FIS_OK && sel[ 5] && sel[ 3] && sel[ 0];
assign masked[13] = FIS_ERR && sel[ 6] && sel[ 3] && sel[ 0];
assign masked[14] = FIS_FERR && sel[ 7] && sel[ 3] && sel[ 0];
assign masked[15] = FIS_EXTRA && sel[ 5] && sel[ 4] && sel[ 0];
assign masked[16] = FIS_FIRST_INVALID && sel[ 6] && sel[ 4] && sel[ 0];
assign masked[17] = FR_D2HR && sel[ 7] && sel[ 4] && sel[ 0];
assign masked[18] = FIS_DATA && sel[ 6] && sel[ 5] && sel[ 0];
assign masked[19] = FIS_ANY && sel[ 7] && sel[ 5] && sel[ 0];
assign masked[20] = NB_ND_D2HR_PIO && sel[ 7] && sel[ 6] && sel[ 0];
assign masked[21] = D2HR && sel[ 3] && sel[ 2] && sel[ 1];
assign masked[22] = SDB && sel[ 4] && sel[ 2] && sel[ 1];
assign masked[23] = DMA_ACT && sel[ 5] && sel[ 2] && sel[ 1];
assign masked[24] = DMA_SETUP && sel[ 6] && sel[ 2] && sel[ 1];
assign masked[25] = BIST_ACT_FE && sel[ 7] && sel[ 2] && sel[ 1];
assign masked[26] = BIST_ACT && sel[ 4] && sel[ 3] && sel[ 1];
assign masked[27] = PIO_SETUP && sel[ 5] && sel[ 3] && sel[ 1];
assign masked[28] = NB_ND && sel[ 6] && sel[ 3] && sel[ 1];
assign masked[29] = TFD_STS_ERR && sel[ 7] && sel[ 3] && sel[ 1];
assign masked[30] = FIS_I && sel[ 5] && sel[ 4] && sel[ 1];
assign masked[31] = PIO_I && sel[ 6] && sel[ 4] && sel[ 1];
assign masked[32] = NPD && sel[ 7] && sel[ 4] && sel[ 1];
assign masked[33] = PIOX && sel[ 6] && sel[ 5] && sel[ 1];
assign masked[34] = XFER0 && sel[ 7] && sel[ 5] && sel[ 1];
assign masked[35] = PIOX_XFER0 && sel[ 7] && sel[ 6] && sel[ 1];
assign masked[36] = CTBAA_CTBAP && sel[ 4] && sel[ 3] && sel[ 2];
assign masked[37] = CTBAP && sel[ 5] && sel[ 3] && sel[ 2];
assign masked[38] = CTBA_B && sel[ 6] && sel[ 3] && sel[ 2];
assign masked[39] = CTBA_C && sel[ 7] && sel[ 3] && sel[ 2];
assign masked[40] = TX_ERR && sel[ 5] && sel[ 4] && sel[ 2];
assign masked[41] = SYNCESC_ERR && sel[ 6] && sel[ 4] && sel[ 2];
assign masked[42] = DMA_PRD_IRQ_PEND && sel[ 7] && sel[ 4] && sel[ 2];
assign masked[43] = X_RDY_COLLISION && sel[ 6] && sel[ 5] && sel[ 2];
always @(posedge clk) begin
cond_r[ 0] <= |masked[ 7: 0];
cond_r[ 1] <= |masked[15: 8];
cond_r[ 2] <= |masked[23:16];
cond_r[ 3] <= |masked[31:24];
cond_r[ 4] <= |masked[39:32];
cond_r[ 5] <= |masked[43:40];
end
endmodule
helpers/ahci_fsm_sequence.py
View file @ 17e832f8
This diff is collapsed.
host/link.v
View file @ 17e832f8
......@@ -722,7 +722,7 @@ begin
HOST_LINK_TITLE = "From device - received data";
HOST_LINK_DATA = data_out;
$display("[Host] LINK: %s = %h @%t", HOST_LINK_TITLE, HOST_LINK_DATA, $time);
`endif
//`endif
end
......
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