Commit 1344fec0 authored by Alexey Grebenkin's avatar Alexey Grebenkin

copypaste typos fix in dma_control.v

parent 3b5ef7db
...@@ -188,26 +188,26 @@ wire to_we; ...@@ -188,26 +188,26 @@ wire to_we;
assign to_wr_next_addr = to_wr_addr + 1'b1; assign to_wr_next_addr = to_wr_addr + 1'b1;
assign to_rd_next_addr = to_rd_addr + 1'b1; assign to_rd_next_addr = to_rd_addr + 1'b1;
// hclk domain counters // sclk domain counters
always @ (posedge hclk) always @ (posedge sclk)
begin begin
to_wr_addr <= rst ? 10'h0 : to_we ? to_wr_next_addr : to_wr_addr; to_wr_addr <= rst ? 10'h0 : to_we ? to_wr_next_addr : to_wr_addr;
to_wr_addr_gr <= rst ? 10'h0 : to_we ? to_wr_next_addr ^ {1'b0, to_wr_next_addr[9:1]} : to_wr_addr_gr; to_wr_addr_gr <= rst ? 10'h0 : to_we ? to_wr_next_addr ^ {1'b0, to_wr_next_addr[9:1]} : to_wr_addr_gr;
end end
// sclk domain counters // hclk domain counters
always @ (posedge sclk) always @ (posedge hclk)
begin begin
to_rd_addr <= rst ? 9'h0 : to_re ? to_rd_next_addr : to_rd_addr; to_rd_addr <= rst ? 9'h0 : to_re ? to_rd_next_addr : to_rd_addr;
to_rd_addr_gr <= rst ? 9'h0 : to_re ? to_rd_next_addr ^ {1'b0, to_rd_next_addr[8:1]} : to_rd_addr_gr; to_rd_addr_gr <= rst ? 9'h0 : to_re ? to_rd_next_addr ^ {1'b0, to_rd_next_addr[8:1]} : to_rd_addr_gr;
end end
// write address -> sclk (rd) domain to compare // write address -> hclk (rd) domain to compare
always @ (posedge sclk) always @ (posedge hclk)
begin begin
to_wr_addr_gr_r <= rst ? 10'h0 : to_wr_addr; to_wr_addr_gr_r <= rst ? 10'h0 : to_wr_addr;
to_wr_addr_gr_rr <= rst ? 10'h0 : to_wr_addr_rr; to_wr_addr_gr_rr <= rst ? 10'h0 : to_wr_addr_rr;
end end
// read address -> hclk (wr) domain to compare // read address -> sclk (wr) domain to compare
always @ (posedge hclk) always @ (posedge sclk)
begin begin
to_rd_addr_gr_r <= rst ? 9'h0 : to_rd_addr; to_rd_addr_gr_r <= rst ? 9'h0 : to_rd_addr;
to_rd_addr_gr_rr <= rst ? 9'h0 : to_rd_addr_rr; to_rd_addr_gr_rr <= rst ? 9'h0 : to_rd_addr_rr;
...@@ -228,13 +228,13 @@ begin: to_rd_antigray ...@@ -228,13 +228,13 @@ begin: to_rd_antigray
end end
endgenerate endgenerate
// so we've got the following: // so we've got the following:
// hclk domain: to_wr_addr - current write address // sclk domain: to_wr_addr - current write address
// to_rd_addr_r - read address some hclk ticks ago // to_rd_addr_r - read address some sclk ticks ago
// => we can say if the fifo have the possibility to be full // => we can say if the fifo have the possibility to be full
// since actual to_rd_addr could only be incremented // since actual to_rd_addr could only be incremented
// //
// sclk domain: to_rd_addr - current read address // hclk domain: to_rd_addr - current read address
// to_wr_addr_r - write address some sclk ticks ago // to_wr_addr_r - write address some hclk ticks ago
// => we can say if the fifo have the possibility to be empty // => we can say if the fifo have the possibility to be empty
// since actual to_wr_addr could only be incremented // since actual to_wr_addr could only be incremented
assign to_full = {to_wr_addr, 1'b0} == to_rd_addr_r + 1'b1; assign to_full = {to_wr_addr, 1'b0} == to_rd_addr_r + 1'b1;
......
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