Skip to content

X
x393_sata
Commit 0e68732d authored by Andrey Filippov's avatar Andrey Filippov
Browse files
Options

more debugging

parent 507b1bd3
Show whitespace changes
Inline Side-by-side
Showing with 327 additions and 112 deletions
.project
View file @ 0e68732d
......@@ -52,87 +52,87 @@
<link>
<name>vivado_logs/VivadoBitstream.log</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoBitstream-20160209233437529.log</location>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoBitstream-20160211193930680.log</location>
</link>
<link>
<name>vivado_logs/VivadoOpt.log</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOpt-20160209233437529.log</location>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOpt-20160211193930680.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPhys.log</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPhys-20160209233437529.log</location>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPhys-20160211193930680.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPower.log</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPower-20160209233437529.log</location>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPower-20160211193930680.log</location>
</link>
<link>
<name>vivado_logs/VivadoPlace.log</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoPlace-20160209233437529.log</location>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoPlace-20160211193930680.log</location>
</link>
<link>
<name>vivado_logs/VivadoRoute.log</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoRoute-20160209233437529.log</location>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoRoute-20160211193930680.log</location>
</link>
<link>
<name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoSynthesis-20160209233314772.log</location>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoSynthesis-20160211193930680.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportImplemented-20160209233437529.log</location>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportImplemented-20160211193930680.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160209233314772.log</location>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160211193930680.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimingReportImplemented.log</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportImplemented-20160209233437529.log</location>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportImplemented-20160211193930680.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimingReportSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportSynthesis-20160209233314772.log</location>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportSynthesis-20160211193930680.log</location>
</link>
<link>
<name>vivado_state/x393_sata-opt-phys.dcp</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-phys-20160209233437529.dcp</location>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-phys-20160211193930680.dcp</location>
</link>
<link>
<name>vivado_state/x393_sata-opt-power.dcp</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-power-20160209233437529.dcp</location>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-power-20160211193930680.dcp</location>
</link>
<link>
<name>vivado_state/x393_sata-opt.dcp</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-20160209233437529.dcp</location>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-20160211193930680.dcp</location>
</link>
<link>
<name>vivado_state/x393_sata-place.dcp</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-place-20160209233437529.dcp</location>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-place-20160211193930680.dcp</location>
</link>
<link>
<name>vivado_state/x393_sata-route.dcp</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-route-20160209233437529.dcp</location>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-route-20160211193930680.dcp</location>
</link>
<link>
<name>vivado_state/x393_sata-synth.dcp</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-synth-20160209233314772.dcp</location>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-synth-20160211193930680.dcp</location>
</link>
</linkedResources>
</projectDescription>
ahci/ahci_sata_layers.v
View file @ 0e68732d
......@@ -225,8 +225,8 @@ module ahci_sata_layers #(
/// assign serr_DS = phy_ready && (cominit_got); // RWC: Link sequence error
/// assign serr_DC = phy_ready && (serr_DW); // RWC: CRC error in Link layer
assign serr_DT = phy_ready && (0); // RWC: Transport state transition error
assign serr_DS = phy_ready && (0); // RWC: Link sequence error
assign serr_DC = phy_ready && (0); // RWC: CRC error in Link layer
// assign serr_DS = phy_ready && (0); // RWC: Link sequence error
// assign serr_DC = phy_ready && (0); // RWC: CRC error in Link layer
// assign serr_DB = phy_ready && (0); // RWC: 10B to 8B decode error
assign serr_DI = phy_ready && (rxelsfull); // RWC: PHY Internal Error // just debugging
assign serr_EP = phy_ready && (rxelsempty); // RWC: Protocol Error - a violation of SATA protocol detected // just debugging
......@@ -277,7 +277,8 @@ module ahci_sata_layers #(
.sync_escape_req (syncesc_send), // input wire // TL demands to brutally cancel current transaction
.sync_escape_ack (syncesc_send_done), // output wire // acknowlegement of a successful reception?
.incom_stop_req (pcmd_st_cleared), // input wire // TL demands to stop current receiving session
.link_established (link_established),
.link_established (link_established), // output wire
.link_bad_crc (serr_DC), // output wire // Bad CRC at EOF
// inputs from phy
.phy_ready (phy_ready), // input wire // phy is ready - link is established
// data-primitives stream from phy
......@@ -348,6 +349,8 @@ module ahci_sata_layers #(
.cplllock_debug (),
.usrpll_locked_debug(),
.re_aligned (serr_DS), // output reg
`ifdef USE_DRP
.drp_rst (drp_rst), // input
......
host/elastic1632.v
View file @ 0e68732d
......@@ -23,7 +23,7 @@
module elastic1632#(
parameter DEPTH_LOG2 = 4, // => 16 total rows x16 is for free in Xilinx, but keep it asymmetrical to reduce
// latency
parameter OFFSET = 5 // distance between read and write pointers, = wr_ptr - rd_ptr
parameter OFFSET = 7 // 5 // distance between read and write pointers, = wr_ptr - rd_ptr
)(
input wclk,
input rclk,
......@@ -48,6 +48,7 @@ module elastic1632#(
localparam ALIGN_PRIM = 32'h7B4A4ABC;
localparam FIFO_DEPTH = 1 << DEPTH_LOG2;
localparam CORR_OFFSET = OFFSET - 0;
reg [15:0] data_in_r;
reg [1:0] charisk_in_r;
reg [1:0] notintable_in_r;
......@@ -57,7 +58,9 @@ reg msb_in_r; // input contains MSB
reg inc_waddr;
reg [DEPTH_LOG2:0] waddr;
wire [DEPTH_LOG2-1:0] waddr_minus = waddr[DEPTH_LOG2-1:0] - 1;
reg [DEPTH_LOG2:0] raddr;
//reg [DEPTH_LOG2:0] raddr;
wire [DEPTH_LOG2:0] raddr_w;
reg [DEPTH_LOG2:0] raddr_r;
reg [44:0] fifo_ram [0: FIFO_DEPTH -1];
reg [0:0] prealign_ram[0: FIFO_DEPTH -1];
reg [FIFO_DEPTH-1:0] fill;
......@@ -67,13 +70,15 @@ reg [2:0] aligned_rclk;
reg [1:0] dav_rclk;
wire skip_rclk;
wire add_rclk;
wire [44:0] rdata = fifo_ram[raddr[DEPTH_LOG2-1:0]];
wire align_out = rdata[44];
wire pre_align_out = prealign_ram[raddr[DEPTH_LOG2-1:0]];
//wire [44:0] rdata = fifo_ram[raddr[DEPTH_LOG2-1:0]];
reg [44:0] rdata_r;
//wire align_out = rdata[44];
wire align_out = rdata_r[44];
//wire pre_align_out = prealign_ram[raddr[DEPTH_LOG2-1:0]];
reg pre_align_out_r;
reg align_out_r;
reg [2:0] correct_r;
wire correct = align_out && (!align_out_r || (pre_align_out && !correct_r[2]));
wire correct = align_out && (!align_out_r || (pre_align_out_r && !correct_r[2]));
reg [1:0] full_0; // full at waddr = waddr
reg [1:0] full_1; // full at waddr = raddr+1
......@@ -85,7 +90,7 @@ wire is_alignp_w = ({data_in, data_in_r} == ALIGN_PRIM) &&
({notintable_in, notintable_in_r} == 0) &&
({disperror_in, disperror_in_r} == 0);
wire [DEPTH_LOG2:0] dbg_diff = waddr-raddr;
wire [DEPTH_LOG2:0] dbg_diff = waddr-raddr_r;
wire dbg_dav1 = dav_rclk[1];
wire dbg_full0 = full_0[1];
wire dbg_full1 = full_1[1];
......@@ -132,27 +137,44 @@ always @(posedge wclk) begin
end
// FIFO read clock domain - system synchronous, 75MHz for SATA2
localparam [DEPTH_LOG2:0] SIZED0 = 0;
localparam [DEPTH_LOG2:0] SIZED1 = 1;
localparam [DEPTH_LOG2:0] SIZED2 = 2;
// assign raddr_w = aligned_rclk[1]? ( raddr_r + (add_rclk? 0 : (skip_rclk ? 2 : 1))) : 0;
assign raddr_w = aligned_rclk[1]? ( raddr_r + (add_rclk? SIZED0 : (skip_rclk ? SIZED2 : SIZED1))) : SIZED0;
always @(posedge rclk) begin
raddr_r <= raddr_w;
rdata_r <= fifo_ram[raddr_w[DEPTH_LOG2-1:0]];
pre_align_out_r <= prealign_ram[raddr_w[DEPTH_LOG2-1:0]];
if (!aligned32_in_r) aligned_rclk <= 0;
else aligned_rclk <= {aligned_rclk[1:0],fill[OFFSET-2] | aligned_rclk[0]};
if (!aligned32_in_r) dav_rclk <= 0;
else dav_rclk <= {dav_rclk[0],fill_out[raddr[DEPTH_LOG2-1:0]] ^ raddr[DEPTH_LOG2]};
// else dav_rclk <= {dav_rclk[0],fill_out[raddr[DEPTH_LOG2-1:0]] ^ raddr[DEPTH_LOG2]};
else dav_rclk <= {dav_rclk[0],fill_out[raddr_r[DEPTH_LOG2-1:0]] ^ raddr_r[DEPTH_LOG2]};
if (!aligned32_in_r) full_0 <= 1;
else full_0 <= {full_0[0], fill[raddr[DEPTH_LOG2-1:0]] ^ raddr[DEPTH_LOG2]};
// else full_0 <= {full_0[0], fill[raddr[DEPTH_LOG2-1:0]] ^ raddr[DEPTH_LOG2]};
else full_0 <= {full_0[0], fill[raddr_r[DEPTH_LOG2-1:0]] ^ raddr_r[DEPTH_LOG2]};
if (!aligned32_in_r) full_1 <= 1;
else full_1 <= {full_1[0], fill_1[raddr[DEPTH_LOG2-1:0]] ^ raddr[DEPTH_LOG2]};
// else full_1 <= {full_1[0], fill_1[raddr[DEPTH_LOG2-1:0]] ^ raddr[DEPTH_LOG2]};
else full_1 <= {full_1[0], fill_1[raddr_r[DEPTH_LOG2-1:0]] ^ raddr_r[DEPTH_LOG2]};
if (!aligned_rclk[1]) raddr <=0;
else if (!add_rclk) raddr <= raddr + (skip_rclk ? 2 : 1);
// if (!aligned_rclk[1]) raddr <=0;
// else if (!add_rclk) raddr <= raddr + (skip_rclk ? 2 : 1);
disperror_out <= rdata[43:40];
notintable_out <= rdata[39:36];
charisk_out <= rdata[35:32];
data_out <= rdata[31: 0];
disperror_out <= rdata_r[43:40];
notintable_out <= rdata_r[39:36];
charisk_out <= rdata_r[35:32];
data_out <= rdata_r[31: 0];
align_out_r <= align_out;
......@@ -164,7 +186,7 @@ end
assign skip_rclk = correct && dav_rclk[1];
assign add_rclk = correct && !dav_rclk[1];
assign isaligned_out = aligned_rclk[2];
assign full = full_1[1] && !full_0[1];
assign empty = !full_1[1] && full_0[1];
assign full = aligned_rclk && full_1[1] && !full_0[1];
assign empty = aligned_rclk && !full_1[1] && full_0[1];
endmodule
host/gtx_wrap.v
View file @ 0e68732d
......@@ -44,7 +44,10 @@ module gtx_wrap #(
parameter RXCDRPHRESET_TIME = 5'h1,
parameter RXCDRFREQRESET_TIME = 5'h1,
parameter RXDFELPMRESET_TIME = 7'hf,
parameter RXISCANRESET_TIME = 5'h1
parameter RXISCANRESET_TIME = 5'h1,
parameter ELASTIC_DEPTH = 4, //5,
parameter ELASTIC_OFFSET = 7 // 5 //10
)
(
output reg debug = 0,
......@@ -683,8 +686,8 @@ wire rxcominitdet_gtx;
`else // OLD_ELASTIC
elastic1632 #(
.DEPTH_LOG2(4),
.OFFSET(5)
.DEPTH_LOG2 (ELASTIC_DEPTH), // 16 //4),
.OFFSET (ELASTIC_OFFSET) // 10 //5)
) elastic1632_i (
.wclk (xclk), // input 150MHz, recovered
.rclk (rxusrclk2), // input 75 MHz, system
......@@ -742,8 +745,51 @@ wire xclk_gtx;
BUFG bufg_txoutclk (.O(txoutclk),.I(txoutclk_gtx));
//BUFR bufr_xclk (.O(xclk),.I(xclk_mr),.CE(1'b1),.CLR(1'b0));
//BUFMR bufmr_xclk (.O(xclk_mr),.I(xclk_gtx));
`ifdef USE_DRP
wire xclk_gtx_g;
`ifdef STRAIGHT_XCLK
BUFH BUFH_i (
.O(), // output
.I() // input
);
/* Instance template for module clock_inverter */
clock_inverter clock_inverter_i (
.rst (),
.clk_in (), // input
.invert (), // input
.clk_out() // output
);
BUFG bug_xclk (.O(xclk),.I(xclk_gtx));
`else
BUFH bufr_xclk (.O (xclk_gtx_g),
.I (xclk_gtx));
clock_inverter bug_xclk (
.rst (rxreset),
.clk_in (xclk_gtx_g), // input
.invert (other_control[15]), // input other_control[15] inverts xclk phase
.clk_out (xclk)); // output
`endif
BUFG bug_xclk (.O(xclk),.I(~xclk_gtx));
`else
// VDT bug - incorrectly processes defines when calculating closure
BUFH BUFH_i (
.O(), // output
.I() // input
);
/* Instance template for module clock_inverter */
clock_inverter clock_inverter_i (
.rst (),
.clk_in (), // input
.invert (), // input
.clk_out() // output
);
BUFG bug_xclk (.O(xclk),.I(xclk_gtx));
`endif
gtxe2_channel_wrapper #(
.SIM_RECEIVER_DETECT_PASS ("TRUE"),
......
host/link.v
View file @ 0e68732d
......@@ -79,8 +79,9 @@ module link #(
output wire sync_escape_ack, // acknowlegement of a successful reception
input wire incom_stop_req, // TL demands to stop current recieving session
output link_established, // received 3 back-to-back non-align primitives.
output reg link_bad_crc, // got bad crc at EOF
// inputs from phy
input wire phy_ready, // phy is ready - link is established: Not yet - need 3 non-align primitives
input wire phy_ready, // phy is ready - link is established
input wire [DATA_BYTE_WIDTH*8 - 1:0] phy_data_in, // data-primitives stream from phy
input wire [DATA_BYTE_WIDTH - 1:0] phy_isk_in, // charisk
input wire [DATA_BYTE_WIDTH - 1:0] phy_err_in, // disperr | notintable
......@@ -320,6 +321,9 @@ end
///assign alignes_pair = link_established_r && (alignes_pair_0 | alignes_pair_1);
assign alignes_pair = phy_ready && (alignes_pair_0 | alignes_pair_1);
always @ (posedge clk) begin
link_bad_crc <= state_rcvr_eof & crc_bad;
end
// Whole transitions table, literally from doc pages 311-328
assign set_sync_esc = sync_escape_req;
......
host/oob_ctrl.v
View file @ 0e68732d
......@@ -66,7 +66,8 @@ module oob_ctrl #(
input wire rxbyteisaligned,// input wire // obvious
output wire phy_ready, // output wire // shows if channel is ready
input set_offline, // input wire // electrically idle // From
input comreset_send // input wire // Not possible yet? // From
input comreset_send, // input wire // Not possible yet? // From
output reg re_aligned // re-aligned after alignment loss
,output debug_detected_alignp
);
......@@ -99,7 +100,7 @@ reg link_state;
// 1 - connection is being established OR already established, 0 - is not
reg oob_state;
// Force offline from AHCI
// Andrey: Force offline from AHCI
reg force_offline_r; // AHCI conrol need setting offline/sending comreset
always @ (posedge clk) begin
if (rst || comreset_send) force_offline_r <= 0;
......@@ -107,7 +108,19 @@ always @ (posedge clk) begin
end
assign phy_ready = link_state & gtx_ready & rxbyteisaligned;
// Andrey: Make phy ready not go inactive during re-aligning
///assign phy_ready = link_state & gtx_ready & rxbyteisaligned;
reg phy_ready_r;
reg was_aligned_r;
always @ (posedge clk) begin
if (!(link_state & gtx_ready)) phy_ready_r <= 0;
else if (rxbyteisaligned) phy_ready_r <= 1;
was_aligned_r <= rxbyteisaligned;
re_aligned <= phy_ready_r && rxbyteisaligned && !was_aligned_r;
end
assign phy_ready = phy_ready_r;
always @ (posedge clk)
link_state <= (link_state | link_up) & ~link_down & ~rst & ~force_offline_r;
......
host/sata_phy.v
View file @ 0e68732d
......@@ -82,6 +82,8 @@ module sata_phy #(
output cplllock_debug,
output usrpll_locked_debug,
output re_aligned, // re-aligned after alignment loss
`ifdef USE_DRP
input drp_rst,
input drp_clk,
......@@ -152,53 +154,39 @@ wire dummy;
oob_ctrl oob_ctrl(
// sata clk = usrclk2
.clk (clk),
// reset oob
.rst (rst),
// gtx is ready = all resets are done
.gtx_ready (gtx_ready),
.clk (clk), // input wire // sata clk = usrclk2
.rst (rst), // input wire // reset oob
.gtx_ready (gtx_ready), // input wire // gtx is ready = all resets are done
.debug ({dummy,debug_cnt[10:0]}),
// oob responses
.rxcominitdet_in (rxcominitdet),
.rxcomwakedet_in (rxcomwakedet),
.rxelecidle_in (rxelecidle),
.rxcominitdet_in (rxcominitdet), // input wire
.rxcomwakedet_in (rxcomwakedet), // input wire
.rxelecidle_in (rxelecidle), // input wire
// oob issues
.txcominit (txcominit),
.txcomwake (txcomwake),
.txelecidle (txelecidle),
.txpcsreset_req (txpcsreset_req),
.recal_tx_done (recal_tx_done),
.rxreset_req (rxreset_req),
.rxreset_ack (rxreset_ack),
.txcominit (txcominit), // output wire
.txcomwake (txcomwake), // output wire
.txelecidle (txelecidle), // output wire
.txpcsreset_req (txpcsreset_req), // output wire
.recal_tx_done (recal_tx_done), // input wire
.rxreset_req (rxreset_req), // output wire
.rxreset_ack (rxreset_ack), // input wire
.clk_phase_align_req (clk_phase_align_req), // output wire
.clk_phase_align_ack (clk_phase_align_ack), // input wire
// input data stream (if any data during OOB setting => ignored)
.txdata_in (txdata_in),
.txcharisk_in (txcharisk_in),
// output data stream to gtx
.txdata_out (txdata),
.txcharisk_out (txcharisk),
// input data from gtx
.rxdata_in (rxdata[31:0]),
.rxcharisk_in (rxcharisk[3:0]),
// bypassed data from gtx
.rxdata_out (rxdata_out),
.rxcharisk_out (rxcharisk_out),
// receiving data is aligned
.rxbyteisaligned (rxbyteisaligned),
// shows if channel is ready
.phy_ready (phy_ready),
.txdata_in (txdata_in), // input[31:0] wire // input data stream (if any data during OOB setting => ignored)
.txcharisk_in (txcharisk_in), // input[3:0] wire // same
.txdata_out (txdata), // output[31:0] wire // output data stream to gtx
.txcharisk_out (txcharisk), // output[3:0] wire // same
.rxdata_in (rxdata[31:0]), // input[31:0] wire // input data from gtx
.rxcharisk_in (rxcharisk[3:0]), // input[3:0] wire // same
.rxdata_out (rxdata_out), // output[31:0] wire // bypassed data from gtx
.rxcharisk_out (rxcharisk_out), // output[3:0]wire // same
.rxbyteisaligned (rxbyteisaligned), // input wire // receiving data is aligned
.phy_ready (phy_ready), // output wire // shows if channel is ready
// To/from AHCI
.set_offline (set_offline), // input
.comreset_send (comreset_send) // input
,.debug_detected_alignp(debug_detected_alignp)
.comreset_send (comreset_send), // input
.re_aligned (re_aligned) // output reg
,.debug_detected_alignp(debug_detected_alignp) // output
);
wire cplllockdetclk; // TODO
......@@ -293,10 +281,11 @@ always @ (posedge clk or posedge sata_areset) begin
else sata_reset_done_r <= {sata_reset_done_r[1:0], 1'b1};
end
reg cplllock_r;
always @ (posedge gtrefclk) begin
rxreset_f <= ~cplllock | cpllreset | rxreset_oob & gtx_configured;
txreset_f <= ~cplllock | cpllreset;
cplllock_r <= cplllock;
rxreset_f <= ~cplllock_r | ~cplllock | cpllreset | rxreset_oob & gtx_configured;
txreset_f <= ~cplllock_r | ~cplllock | cpllreset;
/// rxreset_f <= ~cplllock | cpllreset | ~usrpll_locked | ~sata_reset_done | rxreset_oob & gtx_configured;
/// txreset_f <= ~cplllock | cpllreset | ~usrpll_locked;
......
py393sata/x393sata.py
View file @ 0e68732d
......@@ -744,20 +744,50 @@ sata = x393sata.x393sata()
sata.bitstream()
#sata.drp_write (0x20b,0x401) # bypass, clock align
### sata.drp (0x20b,0x81) # bypass, clock align
sata.drp (0x20b,0x81) # bypass, clock align
#sata.drp (0x20b,0x400) # bypass, clock align
### sata.drp (0x59,0x8) # Use RXREC
sata.drp (0x59,0x8) # Use RXREC
#sata.drp (0x59,0x48)
sata.reg_status()
sata.reg_status()
_=mem.mem_dump (0x80000ff0, 4,4)
sata.reg_status(),sata.reset_ie()
sata.dd_read_dma(0x5ff, 1)
_=mem.mem_dump (0x80000ff0, 4,4)
_=mem.mem_dump (0x80001000, 0x100,4)
sata.reg_status(),sata.reset_ie()
for block in range (1,255):
sata.dd_read_dma(block, 1)
_=mem.mem_dump (0x80000ff0, 4,4)
_=mem.mem_dump (0x80001000, 0x100,4)
sata.reg_status(),sata.reset_ie()
mem.write_mem(0x80000118,0x10)
06b: 00104 # CFIS:Xmit: do SET_BSY
06c: 30060 # do CFIS_XMIT, WAIT DONE
06d: 19039 # if X_RDY_COLLISION goto P:Idle
06e: 150f8 # if SYNCESC_ERR goto ERR:SyncEscapeRecv
06f: 0a471 # if FIS_OK goto CFIS:Success
070: 00102 # always goto ERR:Non-Fatal
sata.setup_pio_read_identify_command()
sata.reg_status()
_=mem.mem_dump (0x80000ff0, 4,4)
_=mem.mem_dump (0x80001000, 0x100,4)
sata.reg_status(),sata.reset_ie()
sata.reset_ie(), sata.reg_status()
_=mem.mem_dump (0x80000ff0, 4,4)
......
system_defines.vh
View file @ 0e68732d
......@@ -3,6 +3,7 @@
`define SYSTEM_DEFINES
`define USE_DRP
`define ALIGN_CLOCKS
`define STRAIGHT_XCLK
`define USE_DATASCOPE
`define PRELOAD_BRAMS
`define AHCI_SATA 1
......
tb/tb_ahci.tf
View file @ 0e68732d
......@@ -1116,6 +1116,9 @@ initial begin //Host
read_sipo_meas ('h00001, 256, early_count, late_count);
drp_write ('h20b, 'h8401); // bypass, clock align and invert xclk
maxigp1_print (GHC__IS__IPS__ADDR << 2,"GHC__IS__IPS__ADDR"); // Should be 1 (port 0)
maxigp1_writep (GHC__IS__IPS__ADDR << 2, 1); // clear that interrupt
maxigp1_print (GHC__IS__IPS__ADDR << 2,"GHC__IS__IPS__ADDR"); // Now it should be 0
......
tb_ahci_01.sav
View file @ 0e68732d
[*]
[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
[*] Wed Feb 10 06:33:11 2016
[*] Fri Feb 12 00:55:27 2016
[*]
[dumpfile] "/home/andrey/git/x393_sata/simulation/tb_ahci-20160209233045645.fst"
[dumpfile_mtime] "Wed Feb 10 06:32:11 2016"
[dumpfile_size] 10480323
[dumpfile] "/home/andrey/git/x393_sata/simulation/tb_ahci-20160211173556344.fst"
[dumpfile_mtime] "Fri Feb 12 00:37:07 2016"
[dumpfile_size] 6893125
[savefile] "/home/andrey/git/x393_sata/tb_ahci_01.sav"
[timestart] 0
[timestart] 852330
[size] 1823 1180
[pos] 0 0
*-23.654860 890000 29549854 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
*-12.814444 869500 29549854 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] tb_ahci.
[treeopen] tb_ahci.axi_read_addr.
[treeopen] tb_ahci.dev.linkMonitorFIS.
......@@ -23,6 +23,7 @@
[treeopen] tb_ahci.dut.
[treeopen] tb_ahci.dut.axi_hp_clk_i.
[treeopen] tb_ahci.dut.sata_top.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.fifo_h2d_control_i.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.link.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.link.crc.
......@@ -59,7 +60,7 @@
[treeopen] tb_ahci.simul_axi_hp_wr_i.waddr_i.
[treeopen] tb_ahci.simul_axi_hp_wr_i.wdata_i.
[treeopen] tb_ahci.simul_axi_read_i.
[sst_width] 306
[sst_width] 417
[signals_width] 409
[sst_expanded] 1
[sst_vpaned_height] 573
......@@ -3448,7 +3449,6 @@ tb_ahci.elastic1632_slow_i.add_rclk
tb_ahci.elastic1632_slow_i.skip_rclk
@8022
tb_ahci.elastic1632_slow_i.waddr[4:0]
tb_ahci.elastic1632_slow_i.raddr[4:0]
tb_ahci.elastic1632_slow_i.dbg_diff[4:0]
@1401200
-elastic_slow
......@@ -3461,8 +3461,14 @@ tb_ahci.elastic1632_fast_i.is_alignp_w
@22
tb_ahci.elastic1632_fast_i.data_in[15:0]
tb_ahci.elastic1632_fast_i.charisk_in[1:0]
@c00022
tb_ahci.elastic1632_fast_i.charisk_in_r[1:0]
@28
(0)tb_ahci.elastic1632_fast_i.charisk_in_r[1:0]
(1)tb_ahci.elastic1632_fast_i.charisk_in_r[1:0]
@1401200
-group_end
@28
tb_ahci.elastic1632_fast_i.isaligned_in
@22
tb_ahci.elastic1632_fast_i.data_out[31:0]
......@@ -3500,7 +3506,6 @@ tb_ahci.elastic1632_fast_i.correct_r[2:0]
-group_end
@8022
tb_ahci.elastic1632_fast_i.waddr[4:0]
tb_ahci.elastic1632_fast_i.raddr[4:0]
tb_ahci.elastic1632_fast_i.dbg_diff[4:0]
@1401200
-elastic_fast
......@@ -3551,10 +3556,14 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.dbg_clk_align_cntr[15:0]
-oob
@1401200
-oob_ctrl
@800200
@c00200
-sipo_meas
@22
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.channel.rx.RXDATA[63:0]
tb_ahci.read_sipo_meas.duration[15:0]
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.channel.clocking.RXOUTCLK
@22
tb_ahci.read_sipo_meas.mask[31:0]
@28
tb_ahci.read_sipo_meas.running
......@@ -3595,6 +3604,10 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.sipo_to_xclk_measure_i.drp_
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.sipo_to_xclk_measure_i.drp_timer_wr
@22
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.sipo_to_xclk_measure_i.dmask[31:0]
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.RXOUTCLK
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.sipo_to_xclk_measure_i.xclk
@22
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.sipo_to_xclk_measure_i.sipo_di[19:0]
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.sipo_to_xclk_measure_i.sipo_n[19:0]
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.sipo_to_xclk_measure_i.sipo_np[19:0]
......@@ -3629,13 +3642,12 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.sipo_to_xclk_measure_i.othe
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.txreset
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.rxreset
@1000200
@1401200
-sipo_meas
@800200
-gtx
@29
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.drp_we
@28
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.drp_we
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.drp_en
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.drp_en
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.drp_we
......@@ -3659,6 +3671,14 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.rxphaligndone2_r
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.rxphaligndone
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.rxdlysreset
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.rxdlysresetdone
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.xclk_gtx_g
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.xclk_gtx
@22
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.other_control[15:0]
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.xclk
@29
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.rxreset
@800200
-ttxdata_resynchro
@28
......
wrapper/clock_inverter.v 0 → 100644
View file @ 0e68732d
/*******************************************************************************
* Module: clock_inverter
* Date:2016-02-11
* Author: andrey
* Description: Glitch-free clock controlled inverter
*
* Copyright (c) 2016 Elphel, Inc .
* clock_inverter.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* clock_inverter.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module clock_inverter(
input rst, // just for simulation
input clk_in,
input invert,
output clk_out
);
`ifdef SUPPORTED_BUFGCTRL_INVERION
BUFGCTRL #(
.INIT_OUT (0),
.IS_CE0_INVERTED (1'b0),
.IS_CE1_INVERTED (1'b0),
.IS_I0_INVERTED (1'b1),
.IS_I1_INVERTED (1'b0),
.IS_IGNORE0_INVERTED (1'b0),
.IS_IGNORE1_INVERTED (1'b0),
.IS_S0_INVERTED (1'b1),
.IS_S1_INVERTED (1'b0),
.PRESELECT_I0 ("TRUE"),
.PRESELECT_I1 ("FALSE")
) BUFGCTRL_i (
.O (clk_out), // output
.CE0 (1'b1), // input
.CE1 (1'b1), // input
.I0 (clk_in), // input
.I1 (clk_in), // input
.IGNORE0 (1'b0), // input
.IGNORE1 (1'b0), // input
.S0 (invert), // input
.S1 (invert) // input
);
`else
reg invert_r;
reg pos_r;
reg neg_r;
// poor man's ddr
always @ (posedge clk_in) begin
invert_r <= invert;
pos_r <= !rst && !pos_r;
end
always @ (negedge clk_in) begin
neg_r <= pos_r;
end
BUFGCTRL #(
.INIT_OUT (0),
.PRESELECT_I0 ("TRUE"),
.PRESELECT_I1 ("FALSE")
) BUFGCTRL_i (
.O (clk_out), // output
.CE0 (1'b1), // input
.CE1 (1'b1), // input
.I0 (pos_r ^ neg_r), // input
.I1 (pos_r == neg_r), // input
.IGNORE0 (1'b0), // input
.IGNORE1 (1'b0), // input
.S0 (!invert_r), // input
.S1 ( invert_r) // input
);
`endif
endmodule
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment