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x393_sata
Commit 05c77d23 authored by Alexey Grebenkin's avatar Alexey Grebenkin
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Complete host commit, pre-testing

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host/oob.v
View file @ 05c77d23
...@@ -33,8 +33,6 @@ module oob #( ...@@ -33,8 +33,6 @@ module oob #(
input wire clk, input wire clk,
// reset oob // reset oob
input wire rst, input wire rst,
// gtx is ready = all resets are done TODO move it to control oobstart/status control block
input wire gtx_ready,
// oob responces // oob responces
input wire rxcominitdet_in, input wire rxcominitdet_in,
input wire rxcomwakedet_in, input wire rxcomwakedet_in,
...@@ -64,6 +62,8 @@ module oob #( ...@@ -64,6 +62,8 @@ module oob #(
// doc p265, link is established after 3back-to-back non-ALIGNp // doc p265, link is established after 3back-to-back non-ALIGNp
output wire link_up, output wire link_up,
// link goes down - if rxelecidle
output wire link_down,
// the device itself sends cominit // the device itself sends cominit
output wire cominit_req, output wire cominit_req,
...@@ -196,6 +196,17 @@ assign txelecidle = set_wait_cominit | txelecidle_r; ...@@ -196,6 +196,17 @@ assign txelecidle = set_wait_cominit | txelecidle_r;
// indicate if link up condition was made // indicate if link up condition was made
assign link_up = clr_wait_linkup; assign link_up = clr_wait_linkup;
// link goes down when line is idle
reg rxelecidle_r;
reg rxelecidle_rr;
always @ (posedge clk)
begin
rxelecidle_rr <= rxelecidle_r;
rxelecidle_r <= rxelecidle;
end
assign link_down = rxelecidle_rr;
// indicate that device is requesting for oob // indicate that device is requesting for oob
reg cominit_req_r; reg cominit_req_r;
wire cominit_req_set; wire cominit_req_set;
......
host/oob_ctrl.v 0 → 100644
View file @ 05c77d23
/*******************************************************************************
* Module: oob_ctrl
* Date: 2015-07-11
* Author: Alexey
* Description: module to start oob sequences and to handle errors
*
* Copyright (c) 2015 Elphel, Inc.
* oob_ctrl.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* oob_ctrl.v file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`include "oob.v"
module oob_ctrl #(
parameter DATA_BYTE_WIDTH = 4,
parameter CLK_SPEED_GRADE = 2 // 1 - 75 Mhz, 2 - 150Mhz, 4 - 300Mhz
)
(
// sata clk = usrclk2
input wire clk,
// reset oob
input wire rst,
// gtx is ready = all resets are done
input wire gtx_ready,
// oob responces
input wire rxcominitdet_in,
input wire rxcomwakedet_in,
input wire rxelecidle_in,
// oob issues
output wire txcominit,
output wire txcomwake,
output wire txelecidle,
// input data stream (if any data during OOB setting => ignored)
input wire [DATA_BYTE_WIDTH*8 - 1:0] txdata_in,
input wire [DATA_BYTE_WIDTH - 1:0] txcharisk_in,
// output data stream to gtx
output wire [DATA_BYTE_WIDTH*8 - 1:0] txdata_out,
output wire [DATA_BYTE_WIDTH - 1:0] txcharisk_out,
// input data from gtx
input wire [DATA_BYTE_WIDTH*8 - 1:0] rxdata_in,
input wire [DATA_BYTE_WIDTH - 1:0] rxcharisk_in,
// bypassed data from gtx
output wire [DATA_BYTE_WIDTH*8 - 1:0] rxdata_out,
output wire [DATA_BYTE_WIDTH - 1:0] rxcharisk_out,
// obvious
input wire rxbyteisaligned,
// shows if channel is ready
output wire phy_ready
);
// oob sequence needs to be issued
wire oob_start;
// connection established, all further data is valid
wire oob_done;
// doc p265, link is established after 3back-to-back non-ALIGNp
wire link_up;
wire link_down;
// the device itself sends cominit
wire cominit_req;
// allow to respond to cominit
wire cominit_allow;
// status information to handle by a control block if any exists
// incompatible host-device speed grades (host cannot lock to alignp)
wire oob_incompatible; // TODO
// timeout in an unexpected place
wire oob_error;
// noone responds to our cominits
wire oob_silence;
// for the resync sake
reg rxbyteisaligned_r;
reg rxbyteisaligned_rr;
always @ (posedge clk)
begin
rxbyteisaligned_rr <= rxbyteisaligned_r;
rxbyteisaligned <= rxbyteisaligned;
end
// 1 - link is up and running, 0 - probably not
reg link_state;
// 1 - connection is being established, 0 - is not
reg oob_state;
assign phy_ready = link_state & gtx_ready & rxbyteisaligned_rr;
always @ (posedge clk)
link_state <= (link_state | link_up) & ~link_down & ~rst;
always @ (posedge clk)
oob_state <= (oob_state | oob_start | cominit_req & cominit_allow) & ~oob_error & ~oob_silence & ~link_up & ~rst;
// decide when to issue oob: always when gtx is ready
assign oob_start = gtx_ready & ~oob_state;
// let devices always begin oob sequence, if only it's not a glitch
assign cominit_allow = cominit_req & link_state;
oob #(
.DATA_BYTE_WIDTH (DATA_BYTE_WIDTH),
.CLK_SPEED_GRADE (CLK_SPEED_GRADE)
)
oob
(
// sata clk = usrclk2
.clk (clk),
// reset oob
.rst (rst),
// oob responces
.rxcominitdet_in (rxcominitdet_in),
.rxcomwakedet_in (rxcomwakedet_in),
.rxelecidle_in (rxelecidle_in),
// oob issues
.txcominit (txcominit),
.txcomwake (txcomwake),
.txelecidle (txelecidle),
// input data stream (if any data during OOB setting => ignored)
.txdata_in (txdata_in),
.txcharisk_in (txcharisk_in),
// output data stream to gtx
.txdata_out (txdata_out),
.txcharisk_out (txcharisk_out),
// input data from gtx
.rxdata_in (rxdata_in),
.rxcharisk_in (rxcharisk_in),
// bypassed data from gtx
.rxdata_out (rxdata_out),
.rxcharisk_out (rxcharisk_out),
// oob sequence needs to be issued
.oob_start (oob_start),
// connection established, all further data is valid
.oob_done (oob_done),
// doc p265, link is established after 3back-to-back non-ALIGNp
.link_up (link_up),
.link_down (link_down),
// the device itself sends cominit
.cominit_req (cominit_req),
// allow to respond to cominit
.cominit_allow (cominit_allow),
// status information to handle by a control block if any exists
// incompatible host-device speed grades (host cannot lock to alignp)
.oob_incompatible (oob_incompatible),
// timeout in an unexpected place
.oob_error (oob_error),
// noone responds to our cominits
.oob_silence (oob_silence)
);
endmodule
sata_host.v
View file @ 05c77d23
This diff is collapsed.
sata_phy.v
View file @ 05c77d23
...@@ -2,7 +2,7 @@ ...@@ -2,7 +2,7 @@
* Module: sata_phy * Module: sata_phy
* Date: 2015-07-11 * Date: 2015-07-11
* Author: Alexey * Author: Alexey
* Description: Ashwin's sata_phy replacement with 7-series support * Description: phy-level, including oob, clock generation and GTXE2
* *
* Copyright (c) 2015 Elphel, Inc. * Copyright (c) 2015 Elphel, Inc.
* sata_phy.v is free software; you can redistribute it and/or modify * sata_phy.v is free software; you can redistribute it and/or modify
...@@ -18,46 +18,45 @@ ...@@ -18,46 +18,45 @@
* You should have received a copy of the GNU General Public License * You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> . * along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/ *******************************************************************************/
`include "oob_ctrl.v"
module sata_phy( module sata_phy(
input wire REFCLK_PAD_P_IN, // GTX reference clock input input wire rst,
input wire REFCLK_PAD_N_IN, // GTX reference clock input // sata clk, generated in pll as usrclk2
input wire RXP0_IN, // Receiver input output wire clk,
input wire RXN0_IN, // Receiver input
input wire GTXRESET_IN, // Main GTX reset
input wire CLKIN_150, // reliable clock input
// Input from Link Layer // state
input wire [31:0] tx_datain, output wire phy_ready,
input wire tx_charisk_in,
output wire DCMLOCKED_OUT, // DCM locked // top-level ifaces
output wire PLLLKDET_OUT_N, // PLL Lock Detect // ref clk from an external source, shall be connected to pads
output wire TXP0_OUT, input wire extclk_p,
output wire TXN0_OUT, input wire extclk_n,
output wire LINKUP, // sata link data pins
output wire LINKUP_led, output wire txp_out,
output wire GEN2_led, output wire txn_out,
output wire align_en_out, input wire rxp_in,
output wire sata_user_clk, input wire rxn_in,
// Outputs to Link Layer
output wire [31:0] rx_dataout, // to link layer
output wire [3:0] rx_charisk_out, output wire [31:0] ll_data_out,
output wire [7:0] CurrentState_out, output wire [3:0] ll_charisk_out,
output wire rxelecidle_out, output wire [3:0] ll_err_out, // TODO!!!
// Rudiments
input wire [35:0] sata_phy_ila_control, // from link layer
input wire [35:0] oob_control_ila_control input wire [31:0] ll_data_in,
input wire [3:0] ll_charisk_in
); );
parameter CHIPSCOPE = "FALSE"; parameter CHIPSCOPE = "FALSE";
wire [31:0] txdata; wire [31:0] txdata;
wire txcharisk; wire [3:0] txcharisk;
wire [63:0] rxdata; wire [63:0] rxdata;
wire [7:0] rxcharisk; wire [3:0] rxcharisk;
wire [31:0] rxdata_out; wire [31:0] rxdata_out;
wire [31:0] txdata_in;
wire [3:0] txcharisk_in;
wire [3:0] rxcharisk_out; wire [3:0] rxcharisk_out;
wire linkup;
wire linkup_led;
wire rxcomwakedet; wire rxcomwakedet;
wire rxcominitdet; wire rxcominitdet;
...@@ -69,37 +68,41 @@ wire rxelecidle; ...@@ -69,37 +68,41 @@ wire rxelecidle;
wire txelecidle; wire txelecidle;
wire rxbyteisaligned; wire rxbyteisaligned;
OOB_control oob_control(
.oob_control_ila_control (36'h0), oob_ctrl oob_ctrl(
//-------- GTX Ports --------/ // sata clk = usrclk2
.clk (sata_user_clk), .clk (clk),
.reset (GTXRESET_IN), // reset oob
.rxreset (/*rxreset*/), .rst (rst),
.rx_locked (cplllock), // gtx is ready = all resets are done
// OOB generation and detection signals from GTX .gtx_ready (gtx_ready),
.txcominit (txcominit), // oob responces
.txcomwake (txcomwake), .rxcominitdet_in (rxcominitdet),
.cominitdet (rxcominitdet), .rxcomwakedet_in (rxcomwakedet),
.comwakedet (rxcomwakedet), .rxelecidle_in (rxelecidle),
// oob issues
.rxelecidle (rxelecidle), .txcominit (txcominit),
.txelecidle_out (txelecidle), .txcomwake (txcomwake),
.rxbyteisaligned (rxbyteisaligned), .txelecidle (txelecidle),
.tx_dataout (txdata), // outgoing GTX data
.tx_charisk_out (txcharisk), // GTX charisk out // input data stream (if any data during OOB setting => ignored)
.rx_datain (rxdata[31:0]), // incoming GTX data .txdata_in (txdata_in),
.rx_charisk_in (rxcharisk[3:0]), // GTX charisk in .txcharisk_in (txcharisk_in),
.gen2 (1'b1), // for SATA Generation 2 // output data stream to gtx
.txdata_out (txdata_out),
//----- USER DATA PORTS---------// .txcharisk_out (txcharisk_out),
.tx_datain (tx_datain), // User datain port // input data from gtx
.tx_charisk_in (tx_charisk_in), // User charisk in port .rxdata_in (rxdata_in),
.rx_dataout (rxdata_out), // User dataout port .rxcharisk_in (rxcharisk_in),
.rx_charisk_out (rxcharisk_out), // User charisk out port // bypassed data from gtx
.linkup (linkup), .rxdata_out (rxdata_out),
.linkup_led_out (linkup_led), .rxcharisk_out (rxcharisk_out),
.align_en_out (align_en_out),
.CurrentState_out (CurrentState_out) // receiving data is aligned
.rxbyteisaligned (rxbyteisaligned),
// shows if channel is ready
.phy_ready (phy_ready)
); );
wire cplllockdetclk; // TODO wire cplllockdetclk; // TODO
...@@ -147,7 +150,7 @@ always @ (posedge gtrefclk) ...@@ -147,7 +150,7 @@ always @ (posedge gtrefclk)
*/ */
wire usrpll_locked; wire usrpll_locked;
assign cpllreset = GTXRESET_IN; assign cpllreset = rst;
assign rxreset = ~cplllock | cpllreset; assign rxreset = ~cplllock | cpllreset;
assign txreset = ~cplllock | cpllreset; assign txreset = ~cplllock | cpllreset;
assign rxuserrdy = usrpll_locked & cplllock & ~cpllreset & ~rxreset & rxeyereset_done; assign rxuserrdy = usrpll_locked & cplllock & ~cpllreset & ~rxreset & rxeyereset_done;
...@@ -226,23 +229,21 @@ usrclk_pll( ...@@ -226,23 +229,21 @@ usrclk_pll(
/* /*
* Padding for an external input clock @ 150 MHz * Padding for an external input clock @ 150 MHz
* TODO !!! Temporary moved to sata_top
*/ */
assign gtrefclk = CLKIN_150; localparam [1:0] CLKSWING_CFG = 2'b11;
/*localparam [1:0] CLKSWING_CFG = 2'b11;
IBUFDS_GTE2 #( IBUFDS_GTE2 #(
.CLKRCV_TRST ("TRUE"), .CLKRCV_TRST ("TRUE"),
.CLKCM_CFG ("TRUE"), .CLKCM_CFG ("TRUE"),
.CLKSWING_CFG (CLKSWING_CFG) .CLKSWING_CFG (CLKSWING_CFG)
) )
ext_clock_buf( ext_clock_buf(
.I (REFCLK_PAD_P_IN), .I (extclk_p),
.IB (REFCLK_PAD_N_IN), .IB (extclk_n),
.CEB (1'b0), .CEB (1'b0),
.O (gtrefclk), .O (gtrefclk),
.ODIV2 () .ODIV2 ()
); );
*/
GTXE2_CHANNEL #( GTXE2_CHANNEL #(
.SIM_RECEIVER_DETECT_PASS ("TRUE"), .SIM_RECEIVER_DETECT_PASS ("TRUE"),
.SIM_TX_EIDLE_DRIVE_LEVEL ("X"), .SIM_TX_EIDLE_DRIVE_LEVEL ("X"),
...@@ -656,7 +657,7 @@ dut( ...@@ -656,7 +657,7 @@ dut(
.TXOUTCLKPCS (), .TXOUTCLKPCS (),
.TXOUTCLKSEL (3'b010), .TXOUTCLKSEL (3'b010),
.TXRATEDONE (), .TXRATEDONE (),
.TXCHARISK ({7'b0, txcharisk}), .TXCHARISK ({4'b0, txcharisk}),
.TXGEARBOXREADY (), .TXGEARBOXREADY (),
.TXHEADER (3'd0), .TXHEADER (3'd0),
.TXSEQUENCE (7'd0), .TXSEQUENCE (7'd0),
...@@ -683,20 +684,17 @@ dut( ...@@ -683,20 +684,17 @@ dut(
/* /*
* Interfaces * Interfaces
*/ */
assign DCMLOCKED_OUT = usrpll_locked;
assign PLLLKDET_OUT_N = cplllock;
assign rxn = RXN0_IN;
assign rxp = RXP0_IN;
assign TXN0_OUT = txn;
assign TXP0_OUT = txp;
assign cplllockdetclk = CLKIN_150; assign cplllockdetclk = CLKIN_150;
assign drpclk = CLKIN_150; assign drpclk = CLKIN_150;
assign LINKUP = linkup;
assign LINKUP_led = linkup_led; assign clk = usrclk2;
assign rx_dataout = rxdata_out; assign rxn = rxn_in;
assign rx_charisk_out = rxcharisk_out; assign rxp = rxp_in;
assign rxelecidle_out = rxelecidle; assign txp_out = txn;
assign GEN2_led = 1'b0; assign txp_out = txp;
assign sata_user_clk = usrclk2; assign ll_data_out = rxdata_out;
assign ll_charisk_out = rxcharisk_out;
assign txdata_in = ll_data_in;
assign txcharisk_in = ll_charisk_in;
endmodule endmodule
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