more debugging

ahci/ahci_dma.v

@@ -177,7 +177,7 @@ module  ahci_dma (
     reg            data_irq; // interrupt at the end of this PRD
     reg     [21:1] wcount;  // Word count
     reg            wcount_set; 
-    reg     [21:1] qwcount; // only [21:3] are used
+    reg     [22:1] qwcount; // only [21:3] are used ([22] - carry from subtraction )
     
     reg     [21:3] qw_datawr_left;
     reg     [ 3:0] qw_datawr_burst;
@@ -216,12 +216,20 @@ module  ahci_dma (
     wire           raddr_ct_rq = cmd_start_hclk;
     reg            raddr_ct_pend;
 
+/*
     wire           addr_data_rq = (wcount_set || data_next_burst);
      
     wire           waddr_data_rq =  !dev_wr_hclk && addr_data_rq;
-    reg            waddr_data_pend;
-    
     wire           raddr_data_rq =   dev_wr_hclk && addr_data_rq;
+
+*/     
+    wire           addr_data_rq_w = (wcount_set || data_next_burst);
+    reg            addr_data_rq_r;
+     
+    wire           waddr_data_rq =  !dev_wr_hclk && addr_data_rq_r;
+    wire           raddr_data_rq =   dev_wr_hclk && addr_data_rq_r;
+
+    reg            waddr_data_pend;
     reg            raddr_data_pend;
     // count different types of AXI ID separately - just for debugging
     reg      [3:0] ct_id;
@@ -240,7 +248,8 @@ module  ahci_dma (
     assign ct_done = (ct_busy_r == 2'b10);
     assign first_prd_fetch = ct_over_prd_enabled == 2'b01;
     assign axi_set_raddr_w = axi_set_raddr_ready && (raddr_ct_pend || raddr_prd_pend || raddr_data_pend);    
-    assign axi_set_waddr_w = axi_set_raddr_ready && raddr_data_pend;    
+/// assign axi_set_waddr_w = axi_set_raddr_ready && raddr_data_pend;    
+    assign axi_set_waddr_w = axi_set_waddr_ready && waddr_data_pend;    
     assign axi_set_addr_data_w = (axi_set_raddr_ready && raddr_data_pend) || (axi_set_waddr_ready && waddr_data_pend);
     
     
@@ -314,7 +323,12 @@ module  ahci_dma (
     wire debug_01 = ct_busy_r[0] || prd_rd_busy ;      
     wire debug_02 =|afi_rcount[7:SAFE_RD_BITS];
     wire debug_03 = (afi_rvalid && !(|afi_rd_ctl));
+    
+    wire [21:1] wcount_plus_data_addr = wcount[21:1] + data_addr[2:1];
+    
     always @ (posedge hclk) begin
+        addr_data_rq_r <= addr_data_rq_w;
+        
         prd_start_hclk_r <= prd_start_hclk;
         
         if      (hrst || cmd_abort_hclk) prd_enabled <= 0;
@@ -366,13 +380,20 @@ module  ahci_dma (
         if (hrst) axi_set_waddr_r <= 0;
         else      axi_set_waddr_r <= axi_set_waddr_w;
         
-        if (addr_data_rq) data_len <= ((|qwcount[21:7]) || (&qwcount[6:3]))? 4'hf: qwcount[6:3];       // early calculate
+///     if (addr_data_rq)   data_len <= ((|qwcount[21:7]) || (&qwcount[6:3]))? 4'hf: qwcount[6:3];       // early calculate
+        if (addr_data_rq_r) data_len <= ((|qwcount[21:7]) || (&qwcount[6:3]))? 4'hf: qwcount[6:3];       // early calculate
+
+///     if      (wcount_set)          qwcount[21:1] <= wcount[21:1] + data_addr[2:1]; //minus 1
+///     else if (axi_set_addr_data_w) qwcount[21:7] <= qwcount[21:7] - 1; // may get negative
 
+        if      (wcount_set)          qwcount[22:1] <= {1'b0,wcount_plus_data_addr[21:1]}; // wcount[21:1] + data_addr[2:1]; //minus 1
+        else if (axi_set_addr_data_w) qwcount[22:7] <= qwcount[22:7] - 1; // may get negative
         
-        if      (wcount_set)          qwcount[21:1] <= wcount[21:1] + data_addr[2:1]; //minus 1
-        else if (axi_set_addr_data_w) qwcount[21:7] <= qwcount[21:7] - 1; // may get negative
+//wcount_plus_data_addr        
         
-        data_next_burst <= axi_set_addr_data_w && ((|qwcount[21:7]) || (&qwcount[6:3])); // same time as afi_awvalid || afi_arvalid
+///     data_next_burst <= axi_set_addr_data_w && ((|qwcount[21:7]) || (&qwcount[6:3])); // same time as afi_awvalid || afi_arvalid
+///        data_next_burst <= !qwcount[22] && axi_set_addr_data_w && ((|qwcount[21:7]) || (&qwcount[6:3])); // same time as afi_awvalid || afi_arvalid
+        data_next_burst <= !qwcount[22] && axi_set_addr_data_w && (|qwcount[21:7]); // same time as afi_awvalid || afi_arvalid
 
 // Get PRD data
         // store data address from PRD, increment when needed

ahci/ahci_top.v

@@ -92,7 +92,7 @@ module  ahci_top#(
     // write data
     output     [63:0] afi_wdata,
     output            afi_wvalid,
-    input             afi_wready,  // @SuppressThisWarning VEditor unused - used FIF0 level
+    input             afi_wready,  // @ SuppressThisWarning VEditor unused - used FIF0 level
     output     [ 5:0] afi_wid,
     output            afi_wlast,
     output     [ 7:0] afi_wstrb,

tb/tb_ahci.tf

@@ -680,7 +680,7 @@ localparam ATA_IDFY = 'hec; // Identify command
 // afi loopback
     assign #1 afi_sim_rd_valid = afi_sim_rd_ready;
     assign #1 afi_sim_rd_resp = afi_sim_rd_ready?2'b0:2'bx;
-    assign #1 afi_sim_wr_ready = afi_sim_wr_valid;
+    assign #1 afi_sim_wr_ready = 1; // afi_sim_wr_valid;
     assign #1 afi_sim_bresp_latency=4'h5; 
 //  assign #1 afi_sim_rd_data=  afi_sim_rd_ready?{2'h0,afi_sim_rd_address[31:3],1'h1,  2'h0,afi_sim_rd_address[31:3],1'h0}:64'bx;
     wire MEM_SEL = (afi_sim_rd_address[31:3] >= (SYS_MEM_START >> 3)) && (afi_sim_rd_address[31:3] < ((SYS_MEM_START + SYS_MEM_SIZE) >> 3));