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Commit fcb4d602 authored by Andrey Filippov's avatar Andrey Filippov
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Fixing operations in multiple configured modes

parent 7c906860
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dsp/mclt16x16_bayer3.v
View file @ fcb4d602
...@@ -150,7 +150,7 @@ module mclt16x16_bayer3#( ...@@ -150,7 +150,7 @@ module mclt16x16_bayer3#(
reg [SHIFT_WIDTH-1:0] x_shft_ram_reg; // reg [SHIFT_WIDTH-1:0] x_shft_ram_reg; //
reg [SHIFT_WIDTH-1:0] y_shft_ram_reg; // reg [SHIFT_WIDTH-1:0] y_shft_ram_reg; //
reg [1:0] rot_ram_copy; reg [1:0] rot_ram_copy;
reg [2:0] rot_ram_page; reg [3:0] rot_ram_page;
reg inv_checker_rot_ram_reg; // reg inv_checker_rot_ram_reg; //
reg valid_odd_rot_ram_reg; // reg valid_odd_rot_ram_reg; //
reg [SHIFT_WIDTH-1:0] x_shft_rot_ram_reg; // reg [SHIFT_WIDTH-1:0] x_shft_rot_ram_reg; //
...@@ -180,10 +180,10 @@ module mclt16x16_bayer3#( ...@@ -180,10 +180,10 @@ module mclt16x16_bayer3#(
x_shft_ram[regs_wa] <= x_shft_rf_ram_reg; x_shft_ram[regs_wa] <= x_shft_rf_ram_reg;
y_shft_ram[regs_wa] <= y_shft_rf_ram_reg; y_shft_ram[regs_wa] <= y_shft_rf_ram_reg;
inv_checker_rot_ram[{page,regs_wa}] <= inv_checker_rf_ram_reg; inv_checker_rot_ram[{page[0],regs_wa}] <= inv_checker_rf_ram_reg;
valid_odd_rot_ram[{page,regs_wa}] <= valid_odd_rf_ram_reg; valid_odd_rot_ram[{page[0],regs_wa}] <= valid_odd_rf_ram_reg;
x_shft_rot_ram[{page,regs_wa}] <= x_shft_rf_ram_reg; x_shft_rot_ram[{page[0],regs_wa}] <= x_shft_rf_ram_reg;
y_shft_rot_ram[{page,regs_wa}] <= y_shft_rf_ram_reg; y_shft_rot_ram[{page[0],regs_wa}] <= y_shft_rf_ram_reg;
end end
start_block_r <= {start_block_r[0], ((in_cntr[5:0] == 1) && (in_cntr[7:6] != 3))?1'b1:1'b0}; start_block_r <= {start_block_r[0], ((in_cntr[5:0] == 1) && (in_cntr[7:6] != 3))?1'b1:1'b0};
...@@ -196,10 +196,10 @@ module mclt16x16_bayer3#( ...@@ -196,10 +196,10 @@ module mclt16x16_bayer3#(
end end
if (rot_ram_copy[1]) begin if (rot_ram_copy[1]) begin
inv_checker_rot_ram_reg <= inv_checker_rot_ram[rot_ram_page]; inv_checker_rot_ram_reg <= inv_checker_rot_ram[rot_ram_page[2:0]];
valid_odd_rot_ram_reg <= valid_odd_rot_ram[rot_ram_page]; valid_odd_rot_ram_reg <= valid_odd_rot_ram[rot_ram_page[2:0]];
x_shft_rot_ram_reg <= x_shft_rot_ram[rot_ram_page]; x_shft_rot_ram_reg <= x_shft_rot_ram[rot_ram_page[2:0]];
y_shft_rot_ram_reg <= y_shft_rot_ram[rot_ram_page]; y_shft_rot_ram_reg <= y_shft_rot_ram[rot_ram_page[2:0]];
end end
//rot_ram_page rot_ram_copy //rot_ram_page rot_ram_copy
...@@ -329,6 +329,7 @@ module mclt16x16_bayer3#( ...@@ -329,6 +329,7 @@ module mclt16x16_bayer3#(
wire dtt_start_blue = (dtt_start16 & dtt_r_cntr[7:6] == 2); // after wire dtt_start_blue = (dtt_start16 & dtt_r_cntr[7:6] == 2); // after
wire dtt_start_green = (dtt_start16 & dtt_r_cntr[7:6] == 3); // after wire dtt_start_green = (dtt_start16 & dtt_r_cntr[7:6] == 3); // after
reg [TILE_PAGE_BITS + 3:0] dtt_out_ram_cntr; reg [TILE_PAGE_BITS + 3:0] dtt_out_ram_cntr;
wire [TILE_PAGE_BITS + 4:0] dtt_out_ram_cntr_ext={1'b0,dtt_out_ram_cntr};
reg [TILE_PAGE_BITS + 3:0] dtt_out_ram_wah; reg [TILE_PAGE_BITS + 3:0] dtt_out_ram_wah;
wire dtt_start_fill; // some data available in DTT output buffer, OK to start consecutive readout wire dtt_start_fill; // some data available in DTT output buffer, OK to start consecutive readout
reg dtt_start_red_fill; reg dtt_start_red_fill;
...@@ -375,7 +376,8 @@ module mclt16x16_bayer3#( ...@@ -375,7 +376,8 @@ module mclt16x16_bayer3#(
always @ (posedge clk) begin always @ (posedge clk) begin
rot_ram_copy <= {rot_ram_copy[0], dtt_start16}; rot_ram_copy <= {rot_ram_copy[0], dtt_start16};
if (rot_ram_copy[0]) rot_ram_page <= dtt_out_ram_cntr[4:2]; // if (rot_ram_copy[0]) rot_ram_page <= dtt_out_ram_cntr[4:2];
if (rot_ram_copy[0]) rot_ram_page <= dtt_out_ram_cntr_ext[5:2];
// reading memory and running DTT // reading memory and running DTT
start_dtt <= dtt_in_precntr == DTT_IN_DELAY; start_dtt <= dtt_in_precntr == DTT_IN_DELAY;
......
dsp/mclt_test_06.tf
View file @ fcb4d602
...@@ -77,8 +77,12 @@ module mclt_test_06 (); ...@@ -77,8 +77,12 @@ module mclt_test_06 ();
parameter DSP_P_WIDTH = 48; parameter DSP_P_WIDTH = 48;
parameter DEAD_CYCLES = 14; // start next block immedaitely, or with longer pause parameter DEAD_CYCLES = 14; // start next block immedaitely, or with longer pause
// parameter OUTS_AT_ONCE = 0; // 0: outputs with lowest latency, 1: all at once (with green) // parameter OUTS_AT_ONCE = 0; // 0: outputs with lowest latency, 1: all at once (with green)
parameter OUTS_AT_ONCE = 1; // 0: outputs with lowest latency, 1: all at once (with green)
parameter TILE_PAGE_BITS = 2; // 1 or 2 only: number of bits in tile counter (>=2 for simultaneous rotated readout, limited by red) // when OUTS_AT_ONCE==1 - TILE_PAGE_BITS should be 2, if ==0 - TILE_PAGE_BITS can be 1 or 2
parameter OUTS_AT_ONCE = 1; // 1; // 0: outputs with lowest latency, 1: all at once (with green)
parameter TILE_PAGE_BITS = 2; // 2; // 1 or 2 only: number of bits in tile counter (>=2 for simultaneous rotated readout, limited by red)
// TILE_PAGE_BITS=1 (with OUTS_AT_ONCE) is broken
reg RST = 1'b1; reg RST = 1'b1;
reg CLK = 1'b0; reg CLK = 1'b0;
...@@ -149,110 +153,140 @@ module mclt_test_06 (); ...@@ -149,110 +153,140 @@ module mclt_test_06 ();
localparam DTT_ROT_SIZE = 'h300; localparam DTT_ROT_SIZE = 'h300;
localparam DTT_ROT_END = DTT_ROT_START + DTT_ROT_SIZE; // SuppressThisWarning VEditor localparam DTT_ROT_END = DTT_ROT_START + DTT_ROT_SIZE; // SuppressThisWarning VEditor
integer java_all[0:5103]; //'h126f]; // SuppressThisWarning VEditor : assigned in $readmem() system task localparam NUM_TILES = 3;
integer java_all0[0:5103]; //'h126f]; // SuppressThisWarning VEditor : assigned in $readmem() system task
integer java_all1[0:5103]; //'h126f]; // SuppressThisWarning VEditor : assigned in $readmem() system task
integer java_all2[0:5103]; //'h126f]; // SuppressThisWarning VEditor : assigned in $readmem() system task
reg [1:0] TILE_SIZE2 = (TILE_SIDE - 16) >> 1; // 3; // 22; reg [1:0] TILE_SIZE2 = (TILE_SIDE - 16) >> 1; // 3; // 22;
// wire PIX_RE; // SuppressThisWarning VEditor : debug only reg [PIXEL_WIDTH-1 : 0] bayer_tiles[0:512*NUM_TILES]; // SuppressThisWarning VEditor : assigned in $readmem() system task
// wire [8:0] PIX_ADDR9; // reg [PIXEL_WIDTH-1 : 0] jav_pix_in [0:INTILE_SIZE*NUM_TILES-1];
// wire PIX_COPY_PAGE; // copy page address // SuppressThisWarning VEditor - not yet used reg [PIXEL_WIDTH-1 : 0] jav_pix_in [0:INTILE_SIZE*4-1];
// wire [PIXEL_WIDTH-1 : 0] PIX_D; reg [3 : 0] jav_signs [0:SGN_SIZE*NUM_TILES-1]; // SuppressThisWarning VEditor not yet used
reg [PIXEL_WIDTH-1 : 0] bayer_tiles[0:1023]; // SuppressThisWarning VEditor : assigned in $readmem() system task reg [WND_WIDTH-1 : 0] jav_wnd [0:WND_SIZE*NUM_TILES-1]; // SuppressThisWarning VEditor not yet used
reg [PIXEL_WIDTH-1 : 0] jav_pix_in [0:INTILE_SIZE*2-1]; reg [DTT_IN_WIDTH - 1:0] jav_dtt_in [0:DTT_IN_SIZE*NUM_TILES-1];
reg [3 : 0] jav_signs [0:SGN_SIZE*2-1]; // SuppressThisWarning VEditor not yet used reg [OUT_WIDTH - 1:0] jav_dtt_out[0:DTT_OUT_SIZE*NUM_TILES-1];
reg [WND_WIDTH-1 : 0] jav_wnd [0:WND_SIZE*2-1]; // SuppressThisWarning VEditor not yet used reg [OUT_WIDTH - 1:0] jav_dtt_rot[0:DTT_ROT_SIZE*NUM_TILES-1];
reg [DTT_IN_WIDTH - 1:0] jav_dtt_in [0:DTT_IN_SIZE*2-1]; reg [SHIFT_WIDTH-1:0] jav_shifts_x [0:3*NUM_TILES-1];
reg [OUT_WIDTH - 1:0] jav_dtt_out[0:DTT_OUT_SIZE*2-1]; reg [SHIFT_WIDTH-1:0] jav_shifts_y [0:3*NUM_TILES-1];
reg [OUT_WIDTH - 1:0] jav_dtt_rot[0:DTT_ROT_SIZE*2-1]; reg jav_inv_check[0:3*NUM_TILES-1];
reg [SHIFT_WIDTH-1:0] jav_shifts_x [0:3*2-1]; reg [7:0] jav_top_left[0:3*NUM_TILES-1];
reg [SHIFT_WIDTH-1:0] jav_shifts_y [0:3*2-1]; reg [1:0] jav_vld_rows[0:3*NUM_TILES-1];
reg jav_inv_check[0:3*2-1];
reg [7:0] jav_top_left[0:3*2-1];
reg [1:0] jav_vld_rows[0:3*2-1];
integer offs_x, offs_y, top_left; integer offs_x, offs_y, top_left;
reg [1:0] byr_index; // [0:2]; // bayer index of top-left 16x16 tile reg [1:0] byr_index; // [0:2]; // bayer index of top-left 16x16 tile
initial begin initial begin
// $readmemh("input_data/mclt_dtt_all_00_x1489_y951.dat", java_all); // $readmemh("input_data/mclt_dtt_all_00_x1489_y951.dat", java_all);
$readmemh("input_data/mclt_dtt_all_02_x1489_y951.dat", java_all); $readmemh("input_data/mclt_dtt_all_00_x1489_y951.dat", java_all0);
$readmemh("input_data/mclt_dtt_all_01_x1489_y951.dat", java_all1);
$readmemh("input_data/mclt_dtt_all_02_x1489_y951.dat", java_all2);
$display("000c: %h", java_all['h000c]); $display("000c: %h %h %h", java_all0['h000c],java_all1['h000c],java_all2['h000c]);
$display("01f0: %h", java_all['h01f0]); $display("01f0: %h %h %h", java_all0['h01f0], java_all1['h01f0], java_all2['h01f0]);
$display("02f0: %h", java_all['h02f0]); $display("02f0: %h %h %h", java_all0['h02f0], java_all1['h02f0], java_all2['h02f0]);
$display("03f0: %h", java_all['h03f0]); $display("03f0: %h %h %h", java_all0['h03f0], java_all1['h03f0], java_all2['h03f0]);
$display("04f0: %h", java_all['h04f0]); $display("04f0: %h %h %h", java_all0['h04f0], java_all1['h04f0], java_all2['h04f0]);
$display("05f0: %h", java_all['h05f0]); $display("05f0: %h %h %h", java_all0['h05f0], java_all1['h05f0], java_all2['h05f0]);
$display("06f0: %h", java_all['h06f0]); $display("06f0: %h %h %h", java_all0['h06f0], java_all1['h06f0], java_all2['h06f0]);
$display("07f0: %h", java_all['h07f0]); $display("07f0: %h %h %h", java_all0['h07f0], java_all1['h07f0], java_all2['h07f0]);
$display("08f0: %h", java_all['h08f0]); $display("08f0: %h %h %h", java_all0['h08f0], java_all1['h08f0], java_all2['h08f0]);
$display("09f0: %h", java_all['h09f0]); $display("09f0: %h %h %h", java_all0['h09f0], java_all1['h09f0], java_all2['h09f0]);
$display("0af0: %h", java_all['h0af0]); $display("0af0: %h %h %h", java_all0['h0af0], java_all1['h0af0], java_all2['h0af0]);
$display("0bf0: %h", java_all['h0bf0]); $display("0bf0: %h %h %h", java_all0['h0bf0], java_all1['h0bf0], java_all2['h0bf0]);
$display("0cf0: %h", java_all['h0cf0]); $display("0cf0: %h %h %h", java_all0['h0cf0], java_all1['h0cf0], java_all2['h0cf0]);
$display("0df0: %h", java_all['h0df0]); $display("0df0: %h %h %h", java_all0['h0df0], java_all1['h0df0], java_all2['h0df0]);
$display("0ef0: %h", java_all['h0ef0]); $display("0ef0: %h %h %h", java_all0['h0ef0], java_all1['h0ef0], java_all2['h0ef0]);
$display("0ff0: %h", java_all['h0ff0]); $display("0ff0: %h %h %h", java_all0['h0ff0], java_all1['h0ff0], java_all2['h0ff0]);
$display("10f0: %h %h %h", java_all0['h10f0], java_all1['h10f0], java_all2['h10f0]);
$display("11f0: %h %h %h", java_all0['h11f0], java_all1['h11f0], java_all2['h11f0]);
$display("12f0: %h %h %h", java_all0['h12f0], java_all1['h12f0], java_all2['h12f0]);
$display("10f0: %h", java_all['h10f0]);
$display("11f0: %h", java_all['h11f0]);
$display("12f0: %h", java_all['h12f0]);
for (i=0; i<3; i=i+1) begin for (i=0; i<3; i=i+1) begin
jav_shifts_x[0 + i] = java_all[0 + 4 * i][SHIFT_WIDTH-1:0]; jav_shifts_x[0 + i] = java_all0[0 + 4 * i][SHIFT_WIDTH-1:0];
jav_shifts_x[3 + i] = java_all[0 + 4 * i][SHIFT_WIDTH-1:0]; jav_shifts_x[3 + i] = java_all1[0 + 4 * i][SHIFT_WIDTH-1:0];
jav_shifts_y[0 + i] = java_all[1 + 4 * i][SHIFT_WIDTH-1:0]; jav_shifts_x[6 + i] = java_all2[0 + 4 * i][SHIFT_WIDTH-1:0];
jav_shifts_y[3 + i] = java_all[1 + 4 * i][SHIFT_WIDTH-1:0]; jav_shifts_y[0 + i] = java_all0[1 + 4 * i][SHIFT_WIDTH-1:0];
jav_shifts_y[3 + i] = java_all1[1 + 4 * i][SHIFT_WIDTH-1:0];
jav_shifts_y[6 + i] = java_all2[1 + 4 * i][SHIFT_WIDTH-1:0];
end
for (i=0; i < 3; i=i+1) begin // first tile
byr_index = (java_all0[2 + 4 * i] & 1) + ((java_all0[3 + 4 * i] & 1) << 1); // bayer index of top left 16x16 tile
offs_x= java_all0[2 + 4 * i] - java_all0[2 + 4 * 2] + TILE_SIZE2;
offs_y= java_all0[3 + 4 * i] - java_all0[3 + 4 * 2] + TILE_SIZE2;
top_left = offs_x + TILE_SIDE * offs_y;
jav_top_left[0 + i] = top_left[7:0];
jav_inv_check[0 + i] = ((i == 2)? 1'b0 : 1'b1) ^ byr_index[0] ^ byr_index[1];
jav_vld_rows[0 + i] = (i == 2)? 2'h3 : ((i == 1)?{~byr_index[1],byr_index[1]}:{byr_index[1],~byr_index[1]});
end end
for (i=0; i < 3; i=i+1) begin // two sets for (i=0; i < 3; i=i+1) begin // second tile
byr_index = (java_all[2 + 4 * i] & 1) + ((java_all[3 + 4 * i] & 1) << 1); // bayer index of top left 16x16 tile byr_index = (java_all1[2 + 4 * i] & 1) + ((java_all1[3 + 4 * i] & 1) << 1); // bayer index of top left 16x16 tile
offs_x= java_all[2 + 4 * i] - java_all[2 + 4 * 2] + TILE_SIZE2; offs_x= java_all1[2 + 4 * i] - java_all1[2 + 4 * 2] + TILE_SIZE2;
offs_y= java_all[3 + 4 * i] - java_all[3 + 4 * 2] + TILE_SIZE2; offs_y= java_all1[3 + 4 * i] - java_all1[3 + 4 * 2] + TILE_SIZE2;
top_left = offs_x + TILE_SIDE * offs_y; top_left = offs_x + TILE_SIDE * offs_y;
jav_top_left[0 + i] = top_left[7:0];
jav_top_left[3 + i] = top_left[7:0]; jav_top_left[3 + i] = top_left[7:0];
jav_inv_check[0 + i] = ((i == 2)? 1'b0 : 1'b1) ^ byr_index[0] ^ byr_index[1];
jav_inv_check[3 + i] = ((i == 2)? 1'b0 : 1'b1) ^ byr_index[0] ^ byr_index[1]; jav_inv_check[3 + i] = ((i == 2)? 1'b0 : 1'b1) ^ byr_index[0] ^ byr_index[1];
jav_vld_rows[0 + i] = (i == 2)? 2'h3 : ((i == 1)?{~byr_index[1],byr_index[1]}:{byr_index[1],~byr_index[1]});
jav_vld_rows[3 + i] = (i == 2)? 2'h3 : ((i == 1)?{~byr_index[1],byr_index[1]}:{byr_index[1],~byr_index[1]}); jav_vld_rows[3 + i] = (i == 2)? 2'h3 : ((i == 1)?{~byr_index[1],byr_index[1]}:{byr_index[1],~byr_index[1]});
end end
for (i=0; i < 2; i=i+1) begin // two sets for (i=0; i < 3; i=i+1) begin // third tile
byr_index = (java_all2[2 + 4 * i] & 1) + ((java_all2[3 + 4 * i] & 1) << 1); // bayer index of top left 16x16 tile
offs_x= java_all2[2 + 4 * i] - java_all2[2 + 4 * 2] + TILE_SIZE2;
offs_y= java_all2[3 + 4 * i] - java_all2[3 + 4 * 2] + TILE_SIZE2;
top_left = offs_x + TILE_SIDE * offs_y;
jav_top_left[6 + i] = top_left[7:0];
jav_inv_check[6 + i] = ((i == 2)? 1'b0 : 1'b1) ^ byr_index[0] ^ byr_index[1];
jav_vld_rows[6 + i] = (i == 2)? 2'h3 : ((i == 1)?{~byr_index[1],byr_index[1]}:{byr_index[1],~byr_index[1]});
// $display("i=%h, byr_index= %h, offs_x = %h, offs_y = %h, inv = %h",i, byr_index, offs_x, offs_y,
// ((i == 2)? 1'b0 : 1'b1) ^ byr_index[0] ^ byr_index[1]);
end end
for (i=0; i<TILE_SIZE; i=i+1) begin for (i=0; i<TILE_SIZE; i=i+1) begin
bayer_tiles['h000 + i] = java_all[TILE_START+i][PIXEL_WIDTH-1 : 0]; bayer_tiles['h000 + i] = java_all0[TILE_START+i][PIXEL_WIDTH-1 : 0];
bayer_tiles['h200 + i] = java_all[TILE_START+i][PIXEL_WIDTH-1 : 0]; bayer_tiles['h200 + i] = java_all1[TILE_START+i][PIXEL_WIDTH-1 : 0];
bayer_tiles['h400 + i] = java_all2[TILE_START+i][PIXEL_WIDTH-1 : 0];
end end
for (i=0; i<INTILE_SIZE; i=i+1) begin for (i=0; i<INTILE_SIZE; i=i+1) begin
jav_pix_in[0 + i] = java_all[INTILE_START+i][PIXEL_WIDTH-1 : 0]; jav_pix_in[0 * INTILE_SIZE + i] = java_all0[INTILE_START+i][PIXEL_WIDTH-1 : 0];
jav_pix_in[INTILE_SIZE + i] = java_all[INTILE_START+i][PIXEL_WIDTH-1 : 0]; jav_pix_in[1 * INTILE_SIZE + i] = java_all1[INTILE_START+i][PIXEL_WIDTH-1 : 0];
jav_pix_in[2 * INTILE_SIZE + i] = java_all2[INTILE_START+i][PIXEL_WIDTH-1 : 0];
end end
for (i=0; i<SGN_SIZE; i=i+1) begin for (i=0; i<SGN_SIZE; i=i+1) begin
jav_signs[ + i] = java_all[SGN_START+i][3 : 0]; jav_signs[0 * SGN_SIZE + i] = java_all0[SGN_START+i][3 : 0];
jav_signs[SGN_SIZE + i] = java_all[SGN_START+i][3 : 0]; jav_signs[1 * SGN_SIZE + i] = java_all1[SGN_START+i][3 : 0];
jav_signs[2 * SGN_SIZE + i] = java_all2[SGN_START+i][3 : 0];
end end
for (i=0; i<WND_SIZE; i=i+1) begin for (i=0; i<WND_SIZE; i=i+1) begin
jav_wnd[ + i] = java_all[WND_START+i][WND_WIDTH-1 : 0]; jav_wnd[0 * WND_SIZE + i] = java_all0[WND_START+i][WND_WIDTH-1 : 0];
jav_wnd[WND_SIZE + i] = java_all[WND_START+i][WND_WIDTH-1 : 0]; jav_wnd[1 * WND_SIZE + i] = java_all1[WND_START+i][WND_WIDTH-1 : 0];
jav_wnd[2 * WND_SIZE + i] = java_all2[WND_START+i][WND_WIDTH-1 : 0];
end end
for (i=0; i<DTT_IN_SIZE; i=i+1) begin for (i=0; i<DTT_IN_SIZE; i=i+1) begin
jav_dtt_in[ + i] = java_all[DTT_IN_START+i][DTT_IN_WIDTH-1 : 0]; jav_dtt_in[0 * DTT_IN_SIZE + i] = java_all0[DTT_IN_START+i][DTT_IN_WIDTH-1 : 0];
jav_dtt_in[DTT_IN_SIZE + i] = java_all[DTT_IN_START+i][DTT_IN_WIDTH-1 : 0]; jav_dtt_in[1 * DTT_IN_SIZE + i] = java_all1[DTT_IN_START+i][DTT_IN_WIDTH-1 : 0];
jav_dtt_in[2 * DTT_IN_SIZE + i] = java_all2[DTT_IN_START+i][DTT_IN_WIDTH-1 : 0];
end end
for (i=0; i<DTT_OUT_SIZE; i=i+1) begin for (i=0; i<DTT_OUT_SIZE; i=i+1) begin
jav_dtt_out[ + i] = java_all[DTT_OUT_START+i][OUT_WIDTH-1 : 0]; jav_dtt_out[0 * DTT_OUT_SIZE + i] = java_all0[DTT_OUT_START+i][OUT_WIDTH-1 : 0];
jav_dtt_out[DTT_OUT_SIZE + i] = java_all[DTT_OUT_START+i][OUT_WIDTH-1 : 0]; jav_dtt_out[1 * DTT_OUT_SIZE + i] = java_all1[DTT_OUT_START+i][OUT_WIDTH-1 : 0];
jav_dtt_out[2 * DTT_OUT_SIZE + i] = java_all2[DTT_OUT_START+i][OUT_WIDTH-1 : 0];
end end
for (i=0; i<DTT_ROT_SIZE; i=i+1) begin for (i=0; i<DTT_ROT_SIZE; i=i+1) begin
jav_dtt_rot[ + i] = java_all[DTT_ROT_START+i][OUT_WIDTH-1 : 0]; jav_dtt_rot[0 * DTT_ROT_SIZE + i] = java_all0[DTT_ROT_START+i][OUT_WIDTH-1 : 0];
jav_dtt_rot[DTT_ROT_SIZE + i] = java_all[DTT_ROT_START+i][OUT_WIDTH-1 : 0]; jav_dtt_rot[1 * DTT_ROT_SIZE + i] = java_all1[DTT_ROT_START+i][OUT_WIDTH-1 : 0];
jav_dtt_rot[2 * DTT_ROT_SIZE + i] = java_all2[DTT_ROT_START+i][OUT_WIDTH-1 : 0];
end end
end end
...@@ -265,35 +299,23 @@ module mclt_test_06 (); ...@@ -265,35 +299,23 @@ module mclt_test_06 ();
reg in_run; reg in_run;
wire pre_last_count = (in_cntr == 'hfe); wire pre_last_count = (in_cntr == 'hfe);
reg last_count_r; reg last_count_r;
// wire pre_last_128 = (in_cntr[6:0] == 'h7e);
// reg last_128_r;
// wire start = START | (last_128_r && ! in_cntr[8]);
// reg PAGE; // full page, 192 clocks
integer PAGE; // full page, 192 clocks integer PAGE; // full page, 192 clocks
// reg [2:0] SUB_PAGE; // single color page
// reg PIX_PAGE;
// wire [9:0] PIX_ADDR10 = {PIX_PAGE,PIX_ADDR9}; // SuppressThisWarning VEditor debug output
always @ (posedge CLK) begin always @ (posedge CLK) begin
last_count_r <= pre_last_count; last_count_r <= pre_last_count;
// last_128_r <= pre_last_128;
if (RST) in_run <= 0; if (RST) in_run <= 0;
else if (START) in_run <= 1; else if (START) in_run <= 1;
else if (last_count_r) in_run <= 0; else if (last_count_r) in_run <= 0;
if (!in_run) in_cntr <= 0; // if (!in_run) in_cntr <= 0;
if (!in_run || START) in_cntr <= 0;
else in_cntr <= in_cntr + 1; else in_cntr <= in_cntr + 1;
if (RST) PAGE <= 0; if (RST) PAGE <= 0;
// else if (pre_last_count) PAGE <= PAGE + 1;
else if (in_cntr == 'hf0) PAGE <= PAGE + 1; else if (in_cntr == 'hf0) PAGE <= PAGE + 1;
// if (RST) SUB_PAGE <= 0;
// else if (pre_last_128) SUB_PAGE <= SUB_PAGE + 1;
// if (PIX_COPY_PAGE) PIX_PAGE <= PAGE;
if (RST) PRE_BUSY <= 0; if (RST) PRE_BUSY <= 0;
else if (START) PRE_BUSY <= 1; else if (START) PRE_BUSY <= 1;
else if (in_cntr == 'hf0) PRE_BUSY <= 0; else if (in_cntr == 'hf0) PRE_BUSY <= 0;
...@@ -314,10 +336,8 @@ module mclt_test_06 (); ...@@ -314,10 +336,8 @@ module mclt_test_06 ();
#1 START = 1; #1 START = 1;
@(posedge CLK) @(posedge CLK)
#1 START = 0; #1 START = 0;
for (n = 0; n < 1; n = n+1) begin for (n = 0; n < NUM_TILES-1; n = n+1) begin
if (n >= 1) LATE = 1; if (n >= 1) LATE = 1;
// if (n >= 0) LATE = 1;
// while (!in_cntr[8]) begin
while (!in_cntr[7]) begin while (!in_cntr[7]) begin
@(posedge CLK); @(posedge CLK);
#1; #1;
...@@ -327,7 +347,10 @@ module mclt_test_06 (); ...@@ -327,7 +347,10 @@ module mclt_test_06 ();
/// while (pre_busy3 || LATE) begin /// while (pre_busy3 || LATE) begin
/// if (!pre_busy3) LATE = 0; /// if (!pre_busy3) LATE = 0;
while (PRE_BUSY || LATE) begin while (PRE_BUSY || LATE) begin
if (!PRE_BUSY) LATE = 0; if (!PRE_BUSY) begin // wait and miss no-delay start
while (pre_busy3) @(posedge CLK);
LATE = 0;
end
@(posedge CLK); @(posedge CLK);
#1; #1;
end end
...@@ -340,66 +363,61 @@ module mclt_test_06 (); ...@@ -340,66 +363,61 @@ module mclt_test_06 ();
end end
initial begin
repeat (12000) @(posedge CLK);
$finish;
end
integer n1, cntr1, diff1, p1;// SuppressThisWarning VEditor : assigned in $readmem() system task integer n1, cntr1, diff1, p1;// SuppressThisWarning VEditor : assigned in $readmem() system task
wire start1;
reg [1:0] color1;
reg [1:0] tile1;
wire [7:0] wnd_a_w = mclt16x16_bayer3_i.mclt_bayer_fold_rgb_i.wnd_a_w; wire [7:0] wnd_a_w = mclt16x16_bayer3_i.mclt_bayer_fold_rgb_i.wnd_a_w;
wire [2:0] pix_page= 3 * n1 + p1; wire [3:0] jav_pix_in_now_ah = color1 + 3 * tile1;
wire [2:0] pix_page_d; wire [11:0] jav_pix_in_now_a = {jav_pix_in_now_ah, wnd_a_w};
wire [10:0] jav_pix_in_now_a = {pix_page_d, wnd_a_w}; wire [PIXEL_WIDTH-1 : 0] jav_pix_in_now = PIX_RE3D?jav_pix_in[jav_pix_in_now_a]:{PIXEL_WIDTH{1'bz}};
wire [PIXEL_WIDTH-1 : 0] jav_pix_in_now = cntr1[7]?{PIXEL_WIDTH{1'bz}}:jav_pix_in[jav_pix_in_now_a];
wire [PIXEL_WIDTH-1 : 0] jav_pix_in_now_d; wire [PIXEL_WIDTH-1 : 0] jav_pix_in_now_d;
dly_var #( dly_var #(
.WIDTH(PIXEL_WIDTH), .WIDTH(1),
.DLY_WIDTH(4) .DLY_WIDTH(4)
) dly_jav_pix_in_now_d_i ( ) dly_start1_d_i (
.clk (CLK), // input .clk (CLK), // input
.rst (RST), // input .rst (RST), // input
.dly (4'h4), // input[3:0] .dly (4'h1), // input[3:0]
.din (jav_pix_in_now), // input[0:0] .din (mclt16x16_bayer3_i.mclt_bayer_fold_rgb_i.start), // input[0:0]
.dout (jav_pix_in_now_d) // output[0:0] .dout (start1) // output[0:0]
); );
always @ (posedge CLK) begin
if (start1) begin
color1 <= mclt16x16_bayer3_i.in_cntr[7:6];
tile1 <= PAGE;
end
diff1 <= PIX_D3 - jav_pix_in_now_d;
end
dly_var #( dly_var #(
.WIDTH(3), .WIDTH(PIXEL_WIDTH),
.DLY_WIDTH(4) .DLY_WIDTH(4)
) dly_jav_pix_page_d_i ( ) dly_jav_pix_in_now_d_i (
.clk (CLK), // input .clk (CLK), // input
.rst (RST), // input .rst (RST), // input
.dly (4'h0), // 7), // input[3:0] .dly (4'h4), // input[3:0]
.din (pix_page), // input[0:0] .din (jav_pix_in_now), // input[0:0]
.dout (pix_page_d) // output[0:0] .dout (jav_pix_in_now_d) // output[0:0]
); );
initial begin
while (RST) @(negedge CLK);
for (n1 = 0; n1 < 2; n1 = n1+1) begin
while (!mclt16x16_bayer3_i.mclt_bayer_fold_rgb_i.run_r[0] ||
(mclt16x16_bayer3_i.mclt_bayer_fold_rgb_i.in_cntr != 2)) begin
@(negedge CLK);
end
for (p1 = 0; p1 <3; p1=p1+1) begin
for (cntr1 = 0; cntr1 < ((p1 > 1)?128:64); cntr1 = cntr1 + 1) begin
diff1 = PIX_D3 - jav_pix_in_now_d; // java_fold_index[cntr1];
@(negedge CLK);
end
end
end
end
//Compare DTT inputs //Compare DTT inputs
integer n4, cntr4, diff4,p4; // SuppressThisWarning VEditor : assigned in $readmem() system task integer n4, cntr4, diff4,p4; // SuppressThisWarning VEditor : assigned in $readmem() system task
wire [DTT_IN_WIDTH-1:0] data_dtt_in = mclt16x16_bayer3_i.data_dtt_in; wire [DTT_IN_WIDTH-1:0] data_dtt_in = mclt16x16_bayer3_i.data_dtt_in;
wire [2:0] page4 = 3 * n4 + p4; wire [3:0] page4 = 3 * n4 + p4;
wire [10:0] java_dtt_in_addr = (p4>1)? wire [11:0] java_dtt_in_addr = (p4>1)?
{page4, 1'b0, cntr4[0],cntr4[6:1]} : {page4, 1'b0, cntr4[0],cntr4[6:1]} :
{page4, 1'b0, 1'b0, cntr4[5:0]}; {page4, 1'b0, 1'b0, cntr4[5:0]};
wire [DTT_IN_WIDTH-1:0] java_data_dtt_in = jav_dtt_in[java_dtt_in_addr]; // java_dtt_in0[{cntr4[1:0],cntr4[7:2]}] wire [DTT_IN_WIDTH-1:0] java_data_dtt_in = jav_dtt_in[java_dtt_in_addr]; // java_dtt_in0[{cntr4[1:0],cntr4[7:2]}]
initial begin initial begin
while (RST) @(negedge CLK); while (RST) @(negedge CLK);
for (n4 = 0; n4 < 2; n4 = n4+1) begin for (n4 = 0; n4 < 3; n4 = n4+1) begin
`ifdef DSP_ACCUM_FOLD `ifdef DSP_ACCUM_FOLD
while ((mclt16x16_bayer3_i.dtt_in_precntr != 1) ||!mclt16x16_bayer3_i.dtt_prewe) begin while ((mclt16x16_bayer3_i.dtt_in_precntr != 1) ||!mclt16x16_bayer3_i.dtt_prewe) begin
@(negedge CLK); @(negedge CLK);
...@@ -421,11 +439,8 @@ module mclt_test_06 (); ...@@ -421,11 +439,8 @@ module mclt_test_06 ();
integer n5, cntr5, diff5,p5; // SuppressThisWarning VEditor : assigned in $readmem() system task integer n5, cntr5, diff5,p5; // SuppressThisWarning VEditor : assigned in $readmem() system task
wire [2:0] page5 = 3 * n5 + p5; wire [3:0] page5 = 3 * n5 + p5;
// wire [10:0] java_dtt_r_addr = (p5>1)? wire [11:0] java_dtt_r_addr = {page5, 1'b0, cntr5[6:0]};
// {page5, 1'b0, cntr5[6:0]} :
// {page5, 2'b0, cntr5[5:0]};
wire [10:0] java_dtt_r_addr = {page5, 1'b0, cntr5[6:0]};
wire [DTT_IN_WIDTH-1:0] dtt_r_data = mclt16x16_bayer3_i.dtt_r_data; wire [DTT_IN_WIDTH-1:0] dtt_r_data = mclt16x16_bayer3_i.dtt_r_data;
wire [DTT_IN_WIDTH-1:0] java_dtt_r_data = jav_dtt_in[java_dtt_r_addr]; // java_dtt_in0[cntr5[7:0]]; wire [DTT_IN_WIDTH-1:0] java_dtt_r_data = jav_dtt_in[java_dtt_r_addr]; // java_dtt_in0[cntr5[7:0]];
...@@ -453,40 +468,10 @@ module mclt_test_06 (); ...@@ -453,40 +468,10 @@ module mclt_test_06 ();
end end
end end
/*
integer n50, cntr50, diff50; // SuppressThisWarning VEditor : assigned in $readmem() system task
wire [DTT_IN_WIDTH-1:0] dtt_r_data0 = mclt16x16_bayer_i.dtt_r_data;
wire [DTT_IN_WIDTH-1:0] java_dtt_r_data0 = jav_dtt_in[{n50[2:0], 1'b0, cntr50[6:0]}]; // java_dtt_in0[cntr5[7:0]];
wire dtt_r_regen0 = mclt16x16_bayer_i.dtt_r_regen;
reg dtt_r_dv0; // SuppressThisWarning VEditor just for simulation
always @ (posedge CLK) begin
if (RST) dtt_r_dv0 <= 0;
else dtt_r_dv0 <= dtt_r_regen0;
end
initial begin
while (RST) @(negedge CLK);
for (n50 = 0; n50 < 6; n50 = n50+1) begin
while ((!dtt_r_dv0) || (mclt16x16_bayer_i.dtt_r_cntr[6:0] != 2)) begin
@(negedge CLK);
end
for (cntr50 = 0; cntr50 < 128; cntr50 = cntr50 + 1) begin
#1;
diff50 = dtt_r_data0 - java_dtt_r_data0;
@(negedge CLK);
end
end
end
*/
integer n6, cntr6, diff6r, diff6b, diff6g; // SuppressThisWarning VEditor : assigned in $readmem() system task integer n6, cntr6, diff6r, diff6b, diff6g; // SuppressThisWarning VEditor : assigned in $readmem() system task
wire [TILE_PAGE_BITS+5:0] dtt_rd_ra_r = mclt16x16_bayer3_i.dtt_rd_ra_r; wire [TILE_PAGE_BITS+5:0] dtt_rd_ra_r = mclt16x16_bayer3_i.dtt_rd_ra_r; // SuppressThisWarning VEditor : doex not propagate parameters
wire [TILE_PAGE_BITS+5:0] dtt_rd_ra_b = mclt16x16_bayer3_i.dtt_rd_ra_b; wire [TILE_PAGE_BITS+5:0] dtt_rd_ra_b = mclt16x16_bayer3_i.dtt_rd_ra_b; // SuppressThisWarning VEditor : doex not propagate parameters
wire [7:0] dtt_rd_ra_g = mclt16x16_bayer3_i.dtt_rd_ra_g; wire [7:0] dtt_rd_ra_g = mclt16x16_bayer3_i.dtt_rd_ra_g;
wire [1:0] dtt_rd_regen_r = mclt16x16_bayer3_i.dtt_rd_regen_r; wire [1:0] dtt_rd_regen_r = mclt16x16_bayer3_i.dtt_rd_regen_r;
wire [1:0] dtt_rd_regen_b = mclt16x16_bayer3_i.dtt_rd_regen_b; wire [1:0] dtt_rd_regen_b = mclt16x16_bayer3_i.dtt_rd_regen_b;
...@@ -494,9 +479,25 @@ module mclt_test_06 (); ...@@ -494,9 +479,25 @@ module mclt_test_06 ();
wire [DTT_IN_WIDTH-1:0] dtt_rd_data_r = mclt16x16_bayer3_i.dtt_rd_data_r; wire [DTT_IN_WIDTH-1:0] dtt_rd_data_r = mclt16x16_bayer3_i.dtt_rd_data_r;
wire [DTT_IN_WIDTH-1:0] dtt_rd_data_b = mclt16x16_bayer3_i.dtt_rd_data_b; wire [DTT_IN_WIDTH-1:0] dtt_rd_data_b = mclt16x16_bayer3_i.dtt_rd_data_b;
wire [DTT_IN_WIDTH-1:0] dtt_rd_data_g = mclt16x16_bayer3_i.dtt_rd_data_g; wire [DTT_IN_WIDTH-1:0] dtt_rd_data_g = mclt16x16_bayer3_i.dtt_rd_data_g;
wire [DTT_IN_WIDTH-1:0] java_dtt_rd_data_r=jav_dtt_out['h300*dtt_rd_ra_r[6] + 'h000 + dtt_rd_ra_r[5:0]]; // wire [DTT_IN_WIDTH-1:0] java_dtt_rd_data_r=jav_dtt_out['h300*dtt_rd_ra_r[7:6] + 'h000 + dtt_rd_ra_r[5:0]];
wire [DTT_IN_WIDTH-1:0] java_dtt_rd_data_b=jav_dtt_out['h300*dtt_rd_ra_b[6] + 'h100 + dtt_rd_ra_b[5:0]]; // wire [DTT_IN_WIDTH-1:0] java_dtt_rd_data_b=jav_dtt_out['h300*dtt_rd_ra_b[7:6] + 'h100 + dtt_rd_ra_b[5:0]];
wire [DTT_IN_WIDTH-1:0] java_dtt_rd_data_g=jav_dtt_out['h300*dtt_rd_ra_g[7] + 'h200 + dtt_rd_ra_g[6:0]]; /// wire [DTT_IN_WIDTH-1:0] java_dtt_rd_data_r=jav_dtt_out['h300*dtt_rd_ra_r[7:6] + 'h000 + dtt_rd_ra_r[5:0]];
/// wire [DTT_IN_WIDTH-1:0] java_dtt_rd_data_b=jav_dtt_out['h300*dtt_rd_ra_b[7:6] + 'h100 + dtt_rd_ra_b[5:0]];
wire [DTT_IN_WIDTH-1:0] java_dtt_rd_data_r=jav_dtt_out['h300*{dtt_rd_ra_r7,dtt_rd_ra_r[6]} + 'h000 + dtt_rd_ra_r[5:0]];
wire [DTT_IN_WIDTH-1:0] java_dtt_rd_data_b=jav_dtt_out['h300*{dtt_rd_ra_b7,dtt_rd_ra_b[6]} + 'h100 + dtt_rd_ra_b[5:0]];
wire [DTT_IN_WIDTH-1:0] java_dtt_rd_data_g=jav_dtt_out['h300*{dtt_rd_ra_g8,dtt_rd_ra_g[7]} + 'h200 + dtt_rd_ra_g[6:0]];
// regenerate extra address bit for internal green FD buffer
reg dtt_pre_last_out_g;
reg dtt_rd_ra_g8;
reg [3:0] ROT_RAM_PAGE;
reg [5:0] DTT_OUT_RAM_CNTR;
reg dtt_pre_last_out_r;
reg dtt_rd_ra_r7;
reg dtt_pre_last_out_b;
reg dtt_rd_ra_b7;
wire [DTT_IN_WIDTH-1:0] java_dtt_rd_data_rd; wire [DTT_IN_WIDTH-1:0] java_dtt_rd_data_rd;
wire [DTT_IN_WIDTH-1:0] java_dtt_rd_data_bd; wire [DTT_IN_WIDTH-1:0] java_dtt_rd_data_bd;
wire [DTT_IN_WIDTH-1:0] java_dtt_rd_data_gd; wire [DTT_IN_WIDTH-1:0] java_dtt_rd_data_gd;
...@@ -505,6 +506,26 @@ module mclt_test_06 (); ...@@ -505,6 +506,26 @@ module mclt_test_06 ();
reg dtt_rd_regen_gv; reg dtt_rd_regen_gv;
always @ (posedge CLK) begin always @ (posedge CLK) begin
if (mclt16x16_bayer3_i.dtt_start_red) DTT_OUT_RAM_CNTR <= {page3[1:0],4'b0};
else if (mclt16x16_bayer3_i.dtt_inc16) DTT_OUT_RAM_CNTR <= DTT_OUT_RAM_CNTR + 1;
if (mclt16x16_bayer3_i.rot_ram_copy[0]) ROT_RAM_PAGE <= DTT_OUT_RAM_CNTR [5:2];
dtt_pre_last_out_g <= (mclt16x16_bayer3_i.phase_rotator_g_i.dtt_rd_cntr_pre[8:0] == 'h1ff);
if (RST) dtt_rd_ra_g8 <= 0;
// else if (dtt_pre_last_out_g) dtt_rd_ra_g8 <= mclt16x16_bayer3_i.rot_ram_page[3];
else if (dtt_pre_last_out_g) dtt_rd_ra_g8 <= ROT_RAM_PAGE[3];
dtt_pre_last_out_r <= (mclt16x16_bayer3_i.phase_rotator_r_i.dtt_rd_cntr_pre[8:0] == 'h1ff);
if (RST) dtt_rd_ra_r7 <= 0;
else if (dtt_pre_last_out_r) dtt_rd_ra_r7 <= ROT_RAM_PAGE[3];
dtt_pre_last_out_b <= (mclt16x16_bayer3_i.phase_rotator_b_i.dtt_rd_cntr_pre[8:0] == 'h1ff);
if (RST) dtt_rd_ra_b7 <= 0;
else if (dtt_pre_last_out_b) dtt_rd_ra_b7 <= ROT_RAM_PAGE[3];
dtt_rd_regen_rv <= dtt_rd_regen_r[1]; dtt_rd_regen_rv <= dtt_rd_regen_r[1];
dtt_rd_regen_bv <= dtt_rd_regen_b[1]; dtt_rd_regen_bv <= dtt_rd_regen_b[1];
dtt_rd_regen_gv <= dtt_rd_regen_g[1]; dtt_rd_regen_gv <= dtt_rd_regen_g[1];
...@@ -576,76 +597,28 @@ module mclt_test_06 (); ...@@ -576,76 +597,28 @@ module mclt_test_06 ();
diff7g <= dv_g? (dout_g - java_dout_g) : 'bz; diff7g <= dv_g? (dout_g - java_dout_g) : 'bz;
end end
/*
mclt16x16_bayer #(
.SHIFT_WIDTH (SHIFT_WIDTH),
.PIX_ADDR_WIDTH (PIX_ADDR_WIDTH),
.EXT_PIX_LATENCY (EXT_PIX_LATENCY), // 2), // external pixel buffer a->d latency (may increase to 4 for gamma)
.COORD_WIDTH (COORD_WIDTH),
.PIXEL_WIDTH (PIXEL_WIDTH),
.WND_WIDTH (WND_WIDTH),
.OUT_WIDTH (OUT_WIDTH),
.DTT_IN_WIDTH (DTT_IN_WIDTH),
.TRANSPOSE_WIDTH (TRANSPOSE_WIDTH),
.OUT_RSHIFT (OUT_RSHIFT1),
.OUT_RSHIFT2 (OUT_RSHIFT2),
.DSP_B_WIDTH (DSP_B_WIDTH),
.DSP_A_WIDTH (DSP_A_WIDTH),
.DSP_P_WIDTH (DSP_P_WIDTH),
.DEAD_CYCLES (DEAD_CYCLES)
) mclt16x16_bayer_i (
.clk (CLK), // input
.rst (RST), // input
.start (start), // input
.tile_size (TILE_SIZE2), // input[1:0]
.inv_checker (jav_inv_check[SUB_PAGE]), // INV_CHECKER), // input
.top_left (jav_top_left[SUB_PAGE]), // TOP_LEFT), // input[7:0]
.valid_rows (jav_vld_rows[SUB_PAGE]), // VALID_ROWS), // input[1:0]
.x_shft (jav_shifts_x[SUB_PAGE]), //CLT_SHIFT_X), // input[6:0]
.y_shft (jav_shifts_y[SUB_PAGE]), //CLT_SHIFT_Y), // input[6:0]
.pix_addr (PIX_ADDR9), // output[8:0]
.pix_re (PIX_RE), // output
.pix_page (PIX_COPY_PAGE), // output
.pix_d (PIX_D), // input[15:0]
.pre_busy (pre_busy), // output
.pre_last_in (pre_last_in), // output
.pre_first_out (pre_first_out), // output
.pre_last_out (pre_last_out), // output
.out_addr (out_addr), // output[7:0]
.dv (dv), // output
.dout0 (dout0), // output[24:0] signed
.dout1 (dout1) // output[24:0] signed
);
dly_var #(
.WIDTH(PIXEL_WIDTH),
.DLY_WIDTH(4)
) dly_pix_dly_i (
.clk (CLK), // input
.rst (RST), // input
.dly (4'h1), // input[3:0]
.din (PIX_RE?bayer_tiles[PIX_ADDR10]:{PIXEL_WIDTH{1'bz}}), // input[0:0]
.dout (PIX_D) // output[0:0]
);
*/
wire PIX_RE3; // SuppressThisWarning VEditor : debug only wire PIX_RE3, PIX_RE3D; // SuppressThisWarning VEditor : debug only
wire [8:0] PIX_ADDR93; wire [8:0] PIX_ADDR93;
reg [TILE_PAGE_BITS-1:0] PIX_PAGE3; // reg [TILE_PAGE_BITS-1:0] PIX_PAGE3;
wire [9:0] PIX_ADDR103 = {PIX_PAGE3,PIX_ADDR93}; // SuppressThisWarning VEditor debug output reg [1:0] PIX_PAGE3;
wire [10:0] PIX_ADDR103 = {PIX_PAGE3,PIX_ADDR93}; // SuppressThisWarning VEditor debug output
wire PIX_COPY_PAGE3; // copy page address // SuppressThisWarning VEditor - not yet used wire PIX_COPY_PAGE3; // copy page address // 1 ahead
reg PIX_COPY_PAGE3_R; // copy page address // 1 ahead
wire [PIXEL_WIDTH-1 : 0] PIX_D3; wire [PIXEL_WIDTH-1 : 0] PIX_D3;
reg start3; reg start3;
reg [TILE_PAGE_BITS-1 : 0] page3; // 1/2-nd bayer tile // reg [TILE_PAGE_BITS-1 : 0] page3; // 1/2-nd bayer tile
reg [1 : 0] page3; // 1/2-nd bayer tile
reg pre_run; reg pre_run;
reg [1:0] pre_run_cntr; reg [1:0] pre_run_cntr;
wire [2:0] color_page = pre_run_cntr + 3 * page3; // SuppressThisWarning VEditor - VDT bug (used as index) wire [3:0] color_page = pre_run_cntr + 3 * page3; // SuppressThisWarning VEditor - VDT bug (used as index)
reg pending; reg pending;
always @ (posedge CLK) begin always @ (posedge CLK) begin
if (START) page3 <= PAGE[TILE_PAGE_BITS-1:0]; // (SUB_PAGE > 2);
// if (START) page3 <= PAGE[TILE_PAGE_BITS-1:0]; // (SUB_PAGE > 2);
if (START) page3 <= PAGE[1:0]; // (SUB_PAGE > 2);
if (RST) pre_run <= 0; if (RST) pre_run <= 0;
else if (START) pre_run <= 1; else if (START) pre_run <= 1;
...@@ -654,7 +627,9 @@ module mclt_test_06 (); ...@@ -654,7 +627,9 @@ module mclt_test_06 ();
if (!pre_run) pre_run_cntr <= 0; if (!pre_run) pre_run_cntr <= 0;
else pre_run_cntr <= pre_run_cntr + 1; else pre_run_cntr <= pre_run_cntr + 1;
if (PIX_COPY_PAGE3) PIX_PAGE3 <= page3; PIX_COPY_PAGE3_R <= PIX_COPY_PAGE3;
// if (PIX_COPY_PAGE3_R) PIX_PAGE3 <= page3[TILE_PAGE_BITS-1:0];
if (PIX_COPY_PAGE3_R) PIX_PAGE3 <= page3[1:0];
if (RST) pending <= 0; if (RST) pending <= 0;
else if (pre_run_cntr == 1) pending <= 1; else if (pre_run_cntr == 1) pending <= 1;
...@@ -662,6 +637,7 @@ module mclt_test_06 (); ...@@ -662,6 +637,7 @@ module mclt_test_06 ();
start3 <= pending && !pre_busy3; // (pre_run_cntr == 2); start3 <= pending && !pre_busy3; // (pre_run_cntr == 2);
end end
mclt16x16_bayer3 #( mclt16x16_bayer3 #(
...@@ -686,7 +662,7 @@ module mclt_test_06 (); ...@@ -686,7 +662,7 @@ module mclt_test_06 ();
.clk (CLK), // input .clk (CLK), // input
.rst (RST), // input .rst (RST), // input
.start (start3), // input .start (start3), // input
.page (page3), // input .page (page3[TILE_PAGE_BITS-1:0]), // input
.tile_size (TILE_SIZE2), // input[1:0] .tile_size (TILE_SIZE2), // input[1:0]
.color_wa (pre_run_cntr), // input[1:0] .color_wa (pre_run_cntr), // input[1:0]
.inv_checker (jav_inv_check[color_page]), // input .inv_checker (jav_inv_check[color_page]), // input
...@@ -732,6 +708,16 @@ module mclt_test_06 (); ...@@ -732,6 +708,16 @@ module mclt_test_06 ();
.din (PIX_RE3?bayer_tiles[PIX_ADDR103]:{PIXEL_WIDTH{1'bz}}), // input[0:0] .din (PIX_RE3?bayer_tiles[PIX_ADDR103]:{PIXEL_WIDTH{1'bz}}), // input[0:0]
.dout (PIX_D3) // output[0:0] .dout (PIX_D3) // output[0:0]
); );
dly_var #(
.WIDTH(1),
.DLY_WIDTH(4)
) dly_pix_re_dly3_i (
.clk (CLK), // input
.rst (RST), // input
.dly (4'h1), // input[3:0]
.din (PIX_RE3), // input[0:0]
.dout (PIX_RE3D) // output[0:0]
);
......
dsp/phase_rotator_rgb.v
View file @ fcb4d602
...@@ -45,9 +45,9 @@ module phase_rotator_rgb#( ...@@ -45,9 +45,9 @@ module phase_rotator_rgb#(
parameter DSP_A_WIDTH = 25, parameter DSP_A_WIDTH = 25,
parameter DSP_P_WIDTH = 48, parameter DSP_P_WIDTH = 48,
parameter COEFF_WIDTH = 17, // = DSP_B_WIDTH - 1 or positive numbers, parameter COEFF_WIDTH = 17, // = DSP_B_WIDTH - 1 or positive numbers,
parameter GREEN = 1, // 0: use 1 DTT block (R,B), 1: use two DTT blocks (G) parameter GREEN = 0, // 0: use 1 DTT block (R,B), 1: use two DTT blocks (G)
parameter START_DELAY = 128, // delay start of input memory readout parameter START_DELAY = 128, // delay start of input memory readout
parameter TILE_PAGE_BITS = 1 // 1 or 2 only: number of bits in tile counter (>=2 for simultaneous rotated readout, limited by red) parameter TILE_PAGE_BITS = 2 // 1 or 2 only: number of bits in tile counter (>=2 for simultaneous rotated readout, limited by red)
)( )(
input clk, //!< system clock, posedge input clk, //!< system clock, posedge
input rst, //!< sync reset input rst, //!< sync reset
...@@ -76,7 +76,7 @@ module phase_rotator_rgb#( ...@@ -76,7 +76,7 @@ module phase_rotator_rgb#(
reg [1:0] dtt_start_out; reg [1:0] dtt_start_out;
reg [7:0] dtt_dly_cntr; reg [7:0] dtt_dly_cntr;
reg [4:0] dtt_rd_regen_dv; reg [4:0] dtt_rd_regen_dv;
reg [8:0] dtt_rd_cntr_pre; // 1 ahead of the former counter for dtt readout to rotator reg [TILE_PAGE_BITS + 7:0] dtt_rd_cntr_pre; // 1 ahead of the former counter for dtt readout to rotator
reg [7:0] in_addr_r; //!< input buffer address reg [7:0] in_addr_r; //!< input buffer address
reg [8:0] out_addr_r; reg [8:0] out_addr_r;
assign in_addr = in_addr_r[GREEN + TILE_PAGE_BITS + 5:0]; assign in_addr = in_addr_r[GREEN + TILE_PAGE_BITS + 5:0];
...@@ -84,6 +84,8 @@ module phase_rotator_rgb#( ...@@ -84,6 +84,8 @@ module phase_rotator_rgb#(
// assign fd_wa = {out_addr_r[8], out_addr_r[0],out_addr_r[1],out_addr_r[4:2],out_addr_r[7:5]}; // assign fd_wa = {out_addr_r[8], out_addr_r[0],out_addr_r[1],out_addr_r[4:2],out_addr_r[7:5]};
assign fd_wa = {out_addr_r[8], out_addr_r[1],out_addr_r[0],out_addr_r[4:2],out_addr_r[7:5]}; assign fd_wa = {out_addr_r[8], out_addr_r[1],out_addr_r[0],out_addr_r[4:2],out_addr_r[7:5]};
wire [TILE_PAGE_BITS + 8:0] dtt_rd_cntr_pre_ext = {1'b0,dtt_rd_cntr_pre}; // to make sure it is 10 bits at least
always @ (posedge clk) begin always @ (posedge clk) begin
if (start) begin if (start) begin
shift_h_r <= shift_h; shift_h_r <= shift_h;
...@@ -114,7 +116,7 @@ module phase_rotator_rgb#( ...@@ -114,7 +116,7 @@ module phase_rotator_rgb#(
if (GREEN) in_addr_r <= {dtt_rd_cntr_pre[8], if (GREEN) in_addr_r <= {dtt_rd_cntr_pre[8],
dtt_rd_cntr_pre[0] ^ dtt_rd_cntr_pre[1], dtt_rd_cntr_pre[0] ^ dtt_rd_cntr_pre[1],
dtt_rd_cntr_pre[0] ? (~dtt_rd_cntr_pre[7:2]) : dtt_rd_cntr_pre[7:2]}; dtt_rd_cntr_pre[0] ? (~dtt_rd_cntr_pre[7:2]) : dtt_rd_cntr_pre[7:2]};
else in_addr_r <= {1'b0, else in_addr_r <= {dtt_rd_cntr_pre_ext[9], // 1'b0,
dtt_rd_cntr_pre[8], dtt_rd_cntr_pre[8],
// dtt_rd_cntr_pre[0] ^ dtt_rd_cntr_pre[1], // dtt_rd_cntr_pre[0] ^ dtt_rd_cntr_pre[1],
dtt_rd_cntr_pre[1] ? dtt_rd_cntr_pre[1] ?
......
mclt_test_06.sav
View file @ fcb4d602
[*] [*]
[*] GTKWave Analyzer v3.3.78 (w)1999-2016 BSI [*] GTKWave Analyzer v3.3.78 (w)1999-2016 BSI
[*] Sat Dec 30 07:52:57 2017 [*] Sun Dec 31 05:57:37 2017
[*] [*]
[dumpfile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/simulation/mclt_test_06-20171230003356794.fst" [dumpfile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/simulation/mclt_test_06-20171230225640461.fst"
[dumpfile_mtime] "Sat Dec 30 07:33:59 2017" [dumpfile_mtime] "Sun Dec 31 05:56:44 2017"
[dumpfile_size] 938964 [dumpfile_size] 1539177
[savefile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/mclt_test_06.sav" [savefile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/mclt_test_06.sav"
[timestart] 0 [timestart] 0
[size] 1824 1171 [size] 1824 1171
[pos] 0 0 [pos] 0 0
*-21.184513 5550000 4825000 5405000 6875000 6955000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 *-21.247999 5735000 4825000 5405000 6875000 6955000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] mclt_test_06. [treeopen] mclt_test_06.
[treeopen] mclt_test_06.mclt16x16_bayer3_i. [treeopen] mclt_test_06.mclt16x16_bayer3_i.
[treeopen] mclt_test_06.mclt16x16_bayer3_i.mclt_baeyer_fold_accum_rgb_i.
[treeopen] mclt_test_06.mclt16x16_bayer3_i.mclt_baeyer_fold_accum_rgb_i.dsp_fold_cs_i. [treeopen] mclt_test_06.mclt16x16_bayer3_i.mclt_baeyer_fold_accum_rgb_i.dsp_fold_cs_i.
[treeopen] mclt_test_06.mclt16x16_bayer3_i.mclt_bayer_fold_rgb_i.
[treeopen] mclt_test_06.mclt16x16_bayer3_i.phase_rotator_b_i. [treeopen] mclt_test_06.mclt16x16_bayer3_i.phase_rotator_b_i.
[treeopen] mclt_test_06.mclt16x16_bayer3_i.phase_rotator_g_i. [treeopen] mclt_test_06.mclt16x16_bayer3_i.phase_rotator_g_i.
[treeopen] mclt_test_06.mclt16x16_bayer3_i.phase_rotator_r_i.
[treeopen] mclt_test_06.mclt16x16_bayer3_i.phase_rotator_r_i.phase_rotator0_i. [treeopen] mclt_test_06.mclt16x16_bayer3_i.phase_rotator_r_i.phase_rotator0_i.
[sst_width] 366 [sst_width] 283
[signals_width] 316 [signals_width] 321
[sst_expanded] 1 [sst_expanded] 1
[sst_vpaned_height] 343 [sst_vpaned_height] 343
@22 @22
mclt_test_06.PAGE mclt_test_06.PAGE
@c00200
-mclt_test_06.in_cntr
@1401200
-group_end
@28 @28
mclt_test_06.CLK mclt_test_06.CLK
@29 mclt_test_06.START
mclt_test_06.page3[1:0] @c00201
-top_details
@28
mclt_test_06.LATE
mclt_test_06.PRE_BUSY
mclt_test_06.pending
mclt_test_06.pre_busy3
mclt_test_06.start3
@420 @420
mclt_test_06.n1 mclt_test_06.n
mclt_test_06.p1 @28
mclt_test_06.cntr1 mclt_test_06.PIX_COPY_PAGE3
mclt_test_06.PIX_RE3D
@c00022
mclt_test_06.PIX_ADDR103[10:0]
@28
(0)mclt_test_06.PIX_ADDR103[10:0]
(1)mclt_test_06.PIX_ADDR103[10:0]
(2)mclt_test_06.PIX_ADDR103[10:0]
(3)mclt_test_06.PIX_ADDR103[10:0]
(4)mclt_test_06.PIX_ADDR103[10:0]
(5)mclt_test_06.PIX_ADDR103[10:0]
(6)mclt_test_06.PIX_ADDR103[10:0]
(7)mclt_test_06.PIX_ADDR103[10:0]
(8)mclt_test_06.PIX_ADDR103[10:0]
(9)mclt_test_06.PIX_ADDR103[10:0]
(10)mclt_test_06.PIX_ADDR103[10:0]
@1401200
-group_end
@22
mclt_test_06.PIX_D3[15:0]
@200
-
@1401201
-top_details
@c00022 @c00022
mclt_test_06.wnd_a_w[7:0] mclt_test_06.wnd_a_w[7:0]
@28 @28
...@@ -51,9 +74,25 @@ mclt_test_06.wnd_a_w[7:0] ...@@ -51,9 +74,25 @@ mclt_test_06.wnd_a_w[7:0]
@1401200 @1401200
-group_end -group_end
@22 @22
mclt_test_06.jav_pix_in_now_a[10:0]
mclt_test_06.jav_pix_in_now[15:0] mclt_test_06.jav_pix_in_now[15:0]
@c00022 @c00022
mclt_test_06.jav_pix_in_now_a[11:0]
@28
(0)mclt_test_06.jav_pix_in_now_a[11:0]
(1)mclt_test_06.jav_pix_in_now_a[11:0]
(2)mclt_test_06.jav_pix_in_now_a[11:0]
(3)mclt_test_06.jav_pix_in_now_a[11:0]
(4)mclt_test_06.jav_pix_in_now_a[11:0]
(5)mclt_test_06.jav_pix_in_now_a[11:0]
(6)mclt_test_06.jav_pix_in_now_a[11:0]
(7)mclt_test_06.jav_pix_in_now_a[11:0]
(8)mclt_test_06.jav_pix_in_now_a[11:0]
(9)mclt_test_06.jav_pix_in_now_a[11:0]
(10)mclt_test_06.jav_pix_in_now_a[11:0]
(11)mclt_test_06.jav_pix_in_now_a[11:0]
@1401200
-group_end
@c00022
[color] 3 [color] 3
mclt_test_06.jav_pix_in_now_d[15:0] mclt_test_06.jav_pix_in_now_d[15:0]
@28 @28
...@@ -93,15 +132,43 @@ mclt_test_06.jav_pix_in_now_d[15:0] ...@@ -93,15 +132,43 @@ mclt_test_06.jav_pix_in_now_d[15:0]
-group_end -group_end
@420 @420
mclt_test_06.diff1 mclt_test_06.diff1
@c00200
-mclt
@28 @28
mclt_test_06.START mclt_test_06.mclt16x16_bayer3_i.set_inv_checker
mclt_test_06.start3 mclt_test_06.mclt16x16_bayer3_i.set_valid_odd
mclt_test_06.pre_busy3 mclt_test_06.mclt16x16_bayer3_i.set_top_left
mclt_test_06.mclt16x16_bayer3_i.set_x_shft
mclt_test_06.mclt16x16_bayer3_i.set_y_shft
@22 @22
mclt_test_06.mclt16x16_bayer3_i.in_cntr[7:0] mclt_test_06.mclt16x16_bayer3_i.color_wa[1:0]
mclt_test_06.pix_page_d[2:0] @28
mclt_test_06.mclt16x16_bayer3_i.inv_checker
mclt_test_06.mclt16x16_bayer3_i.start
(1)mclt_test_06.mclt16x16_bayer3_i.copy_regs[1:0]
(0)mclt_test_06.mclt16x16_bayer3_i.copy_regs[1:0]
@22
mclt_test_06.mclt16x16_bayer3_i.regs_wa[1:0]
@28
mclt_test_06.mclt16x16_bayer3_i.inv_checker_rf_ram_reg
mclt_test_06.mclt16x16_bayer3_i.valid_odd_rf_ram_reg
@22
mclt_test_06.mclt16x16_bayer3_i.x_shft_rf_ram_reg[6:0]
mclt_test_06.mclt16x16_bayer3_i.y_shft_rf_ram_reg[6:0]
@28
(1)mclt_test_06.mclt16x16_bayer3_i.start_block_r[1:0]
(0)mclt_test_06.mclt16x16_bayer3_i.in_cntr[7:0]
(1)mclt_test_06.mclt16x16_bayer3_i.in_cntr[7:0]
mclt_test_06.mclt16x16_bayer3_i.inv_checker_ram_reg
mclt_test_06.mclt16x16_bayer3_i.valid_odd_ram_reg
@22
mclt_test_06.mclt16x16_bayer3_i.top_left_ram_reg[7:0]
mclt_test_06.mclt16x16_bayer3_i.x_shft_ram_reg[6:0]
mclt_test_06.mclt16x16_bayer3_i.y_shft_ram_reg[6:0]
@200 @200
- -
@1401200
-mclt
@420 @420
mclt_test_06.n4 mclt_test_06.n4
mclt_test_06.p4 mclt_test_06.p4
...@@ -143,8 +210,6 @@ mclt_test_06.cntr4 ...@@ -143,8 +210,6 @@ mclt_test_06.cntr4
@1401200 @1401200
-group_end -group_end
@22 @22
mclt_test_06.page4[2:0]
mclt_test_06.java_dtt_in_addr[10:0]
mclt_test_06.data_dtt_in[24:0] mclt_test_06.data_dtt_in[24:0]
mclt_test_06.java_data_dtt_in[24:0] mclt_test_06.java_data_dtt_in[24:0]
@8420 @8420
...@@ -154,6 +219,8 @@ mclt_test_06.diff4 ...@@ -154,6 +219,8 @@ mclt_test_06.diff4
@420 @420
mclt_test_06.n5 mclt_test_06.n5
mclt_test_06.p5 mclt_test_06.p5
@22
mclt_test_06.page5[3:0]
@8420 @8420
mclt_test_06.cntr5 mclt_test_06.cntr5
@22 @22
...@@ -177,10 +244,58 @@ mclt_test_06.mclt16x16_bayer3_i.dtt_r_cntr[7:0] ...@@ -177,10 +244,58 @@ mclt_test_06.mclt16x16_bayer3_i.dtt_r_cntr[7:0]
-group_end -group_end
@22 @22
mclt_test_06.mclt16x16_bayer3_i.dtt_r_data[24:0] mclt_test_06.mclt16x16_bayer3_i.dtt_r_data[24:0]
@200 @c00200
- -tmp
@28
mclt_test_06.mclt16x16_bayer3_i.inv_checker_rf_ram_reg
mclt_test_06.mclt16x16_bayer3_i.inv_checker_ram_reg
mclt_test_06.mclt16x16_bayer3_i.inv_checker_rot_ram_reg
@22
mclt_test_06.mclt16x16_bayer3_i.top_left_rf_ram_reg[7:0]
mclt_test_06.mclt16x16_bayer3_i.x_shft_rf_ram_reg[6:0]
mclt_test_06.mclt16x16_bayer3_i.y_shft_rf_ram_reg[6:0]
mclt_test_06.mclt16x16_bayer3_i.x_shft_rot_ram_reg[6:0]
mclt_test_06.mclt16x16_bayer3_i.x_shft_ram_reg[6:0]
mclt_test_06.mclt16x16_bayer3_i.y_shft_ram_reg[6:0]
mclt_test_06.mclt16x16_bayer3_i.y_shft_rot_ram_reg[6:0]
mclt_test_06.mclt16x16_bayer3_i.rot_ram_page[3:0]
mclt_test_06.ROT_RAM_PAGE[3:0]
@28
mclt_test_06.dtt_pre_last_out_r
mclt_test_06.dtt_pre_last_out_g
@c00022
mclt_test_06.mclt16x16_bayer3_i.phase_rotator_r_i.dtt_rd_cntr_pre[8:0]
@28
(0)mclt_test_06.mclt16x16_bayer3_i.phase_rotator_r_i.dtt_rd_cntr_pre[8:0]
(1)mclt_test_06.mclt16x16_bayer3_i.phase_rotator_r_i.dtt_rd_cntr_pre[8:0]
(2)mclt_test_06.mclt16x16_bayer3_i.phase_rotator_r_i.dtt_rd_cntr_pre[8:0]
(3)mclt_test_06.mclt16x16_bayer3_i.phase_rotator_r_i.dtt_rd_cntr_pre[8:0]
(4)mclt_test_06.mclt16x16_bayer3_i.phase_rotator_r_i.dtt_rd_cntr_pre[8:0]
(5)mclt_test_06.mclt16x16_bayer3_i.phase_rotator_r_i.dtt_rd_cntr_pre[8:0]
(6)mclt_test_06.mclt16x16_bayer3_i.phase_rotator_r_i.dtt_rd_cntr_pre[8:0]
(7)mclt_test_06.mclt16x16_bayer3_i.phase_rotator_r_i.dtt_rd_cntr_pre[8:0]
(8)mclt_test_06.mclt16x16_bayer3_i.phase_rotator_r_i.dtt_rd_cntr_pre[8:0]
@1401200
-group_end
@c00022
mclt_test_06.DTT_OUT_RAM_CNTR[5:0]
@28
(0)mclt_test_06.DTT_OUT_RAM_CNTR[5:0]
(1)mclt_test_06.DTT_OUT_RAM_CNTR[5:0]
(2)mclt_test_06.DTT_OUT_RAM_CNTR[5:0]
(3)mclt_test_06.DTT_OUT_RAM_CNTR[5:0]
(4)mclt_test_06.DTT_OUT_RAM_CNTR[5:0]
(5)mclt_test_06.DTT_OUT_RAM_CNTR[5:0]
@1401200
-group_end
@8022 @8022
mclt_test_06.dtt_rd_ra_g[7:0] mclt_test_06.dtt_rd_ra_g[7:0]
@200
-
@1401200
-tmp
@28
mclt_test_06.dtt_pre_last_out_g
@22 @22
mclt_test_06.dtt_rd_data_r[24:0] mclt_test_06.dtt_rd_data_r[24:0]
mclt_test_06.dtt_rd_data_b[24:0] mclt_test_06.dtt_rd_data_b[24:0]
...@@ -228,12 +343,11 @@ mclt_test_06.cntr7b[7:0] ...@@ -228,12 +343,11 @@ mclt_test_06.cntr7b[7:0]
mclt_test_06.n7g mclt_test_06.n7g
@22 @22
mclt_test_06.cntr7g[7:0] mclt_test_06.cntr7g[7:0]
@800200 @c00200
-mclt16x16 -mclt16x16
@28 @28
mclt_test_06.LATE mclt_test_06.LATE
mclt_test_06.mclt16x16_bayer3_i.start mclt_test_06.mclt16x16_bayer3_i.start
mclt_test_06.mclt16x16_bayer3_i.page[1:0]
mclt_test_06.mclt16x16_bayer3_i.run_r mclt_test_06.mclt16x16_bayer3_i.run_r
mclt_test_06.mclt16x16_bayer3_i.pre_busy mclt_test_06.mclt16x16_bayer3_i.pre_busy
mclt_test_06.mclt16x16_bayer3_i.pre_busy_r mclt_test_06.mclt16x16_bayer3_i.pre_busy_r
...@@ -277,7 +391,7 @@ mclt_test_06.mclt16x16_bayer3_i.in_cntr[7:0] ...@@ -277,7 +391,7 @@ mclt_test_06.mclt16x16_bayer3_i.in_cntr[7:0]
mclt_test_06.mclt16x16_bayer3_i.dead_cntr[3:0] mclt_test_06.mclt16x16_bayer3_i.dead_cntr[3:0]
@200 @200
- -
@1000200 @1401200
-mclt16x16 -mclt16x16
@c00200 @c00200
-dtt_iv_8x8_ad -dtt_iv_8x8_ad
...@@ -290,8 +404,11 @@ mclt_test_06.mclt16x16_bayer3_i.dtt_iv_8x8_ad_i.xin[24:0] ...@@ -290,8 +404,11 @@ mclt_test_06.mclt16x16_bayer3_i.dtt_iv_8x8_ad_i.xin[24:0]
- -
@1401200 @1401200
-dtt_iv_8x8_ad -dtt_iv_8x8_ad
@800200 @c00200
-pre_rot_buffers -pre_rot_buffers
@20000
-
-
@c08022 @c08022
mclt_test_06.mclt16x16_bayer3_i.dtt_out_ram_wa_rb[8:0] mclt_test_06.mclt16x16_bayer3_i.dtt_out_ram_wa_rb[8:0]
@28 @28
...@@ -304,24 +421,15 @@ mclt_test_06.mclt16x16_bayer3_i.dtt_out_ram_wa_rb[8:0] ...@@ -304,24 +421,15 @@ mclt_test_06.mclt16x16_bayer3_i.dtt_out_ram_wa_rb[8:0]
(6)mclt_test_06.mclt16x16_bayer3_i.dtt_out_ram_wa_rb[8:0] (6)mclt_test_06.mclt16x16_bayer3_i.dtt_out_ram_wa_rb[8:0]
(7)mclt_test_06.mclt16x16_bayer3_i.dtt_out_ram_wa_rb[8:0] (7)mclt_test_06.mclt16x16_bayer3_i.dtt_out_ram_wa_rb[8:0]
(8)mclt_test_06.mclt16x16_bayer3_i.dtt_out_ram_wa_rb[8:0] (8)mclt_test_06.mclt16x16_bayer3_i.dtt_out_ram_wa_rb[8:0]
@1409200 @1401200
-group_end -group_end
@20000 @20000
- -
- -
- -
@c08022 @c00200
mclt_test_06.mclt16x16_bayer3_i.dtt_rd_ra_r[7:0] -mclt_test_06.mclt16x16_bayer3_i.dtt_rd_ra_r
@28 @1401200
(0)mclt_test_06.mclt16x16_bayer3_i.dtt_rd_ra_r[7:0]
(1)mclt_test_06.mclt16x16_bayer3_i.dtt_rd_ra_r[7:0]
(2)mclt_test_06.mclt16x16_bayer3_i.dtt_rd_ra_r[7:0]
(3)mclt_test_06.mclt16x16_bayer3_i.dtt_rd_ra_r[7:0]
(4)mclt_test_06.mclt16x16_bayer3_i.dtt_rd_ra_r[7:0]
(5)mclt_test_06.mclt16x16_bayer3_i.dtt_rd_ra_r[7:0]
(6)mclt_test_06.mclt16x16_bayer3_i.dtt_rd_ra_r[7:0]
(7)mclt_test_06.mclt16x16_bayer3_i.dtt_rd_ra_r[7:0]
@1409200
-group_end -group_end
@20000 @20000
- -
...@@ -333,10 +441,13 @@ mclt_test_06.mclt16x16_bayer3_i.dtt_out_ram_wa_g[8:0] ...@@ -333,10 +441,13 @@ mclt_test_06.mclt16x16_bayer3_i.dtt_out_ram_wa_g[8:0]
- -
- -
- -
@8022
mclt_test_06.mclt16x16_bayer3_i.dtt_rd_ra_g[7:0]
@20000
-
-
@28 @28
mclt_test_06.mclt16x16_bayer3_i.clk mclt_test_06.mclt16x16_bayer3_i.clk
@22
mclt_test_06.mclt16x16_bayer3_i.dtt_out_ram_cntr[5:0]
@c00022 @c00022
mclt_test_06.mclt16x16_bayer3_i.dtt_out_ram_wa_rb[8:0] mclt_test_06.mclt16x16_bayer3_i.dtt_out_ram_wa_rb[8:0]
@28 @28
...@@ -351,21 +462,10 @@ mclt_test_06.mclt16x16_bayer3_i.dtt_out_ram_wa_rb[8:0] ...@@ -351,21 +462,10 @@ mclt_test_06.mclt16x16_bayer3_i.dtt_out_ram_wa_rb[8:0]
(8)mclt_test_06.mclt16x16_bayer3_i.dtt_out_ram_wa_rb[8:0] (8)mclt_test_06.mclt16x16_bayer3_i.dtt_out_ram_wa_rb[8:0]
@1401200 @1401200
-group_end -group_end
@c00022 @c00200
mclt_test_06.mclt16x16_bayer3_i.dtt_rd_ra_r[7:0] -mclt_test_06.mclt16x16_bayer3_i.dtt_rd_ra_r
@28
(0)mclt_test_06.mclt16x16_bayer3_i.dtt_rd_ra_r[7:0]
(1)mclt_test_06.mclt16x16_bayer3_i.dtt_rd_ra_r[7:0]
(2)mclt_test_06.mclt16x16_bayer3_i.dtt_rd_ra_r[7:0]
(3)mclt_test_06.mclt16x16_bayer3_i.dtt_rd_ra_r[7:0]
(4)mclt_test_06.mclt16x16_bayer3_i.dtt_rd_ra_r[7:0]
(5)mclt_test_06.mclt16x16_bayer3_i.dtt_rd_ra_r[7:0]
(6)mclt_test_06.mclt16x16_bayer3_i.dtt_rd_ra_r[7:0]
(7)mclt_test_06.mclt16x16_bayer3_i.dtt_rd_ra_r[7:0]
@1401200 @1401200
-group_end -group_end
@22
mclt_test_06.mclt16x16_bayer3_i.dtt_rd_ra_b[7:0]
@200 @200
- -
@28 @28
...@@ -377,17 +477,56 @@ mclt_test_06.mclt16x16_bayer3_i.dtt_out_wd[24:0] ...@@ -377,17 +477,56 @@ mclt_test_06.mclt16x16_bayer3_i.dtt_out_wd[24:0]
mclt_test_06.mclt16x16_bayer3_i.dtt_out_ram_wa_g[8:0] mclt_test_06.mclt16x16_bayer3_i.dtt_out_ram_wa_g[8:0]
mclt_test_06.mclt16x16_bayer3_i.dtt_rd_ra_g[7:0] mclt_test_06.mclt16x16_bayer3_i.dtt_rd_ra_g[7:0]
mclt_test_06.dtt_rd_data_g[24:0] mclt_test_06.dtt_rd_data_g[24:0]
@1000200 @1401200
-pre_rot_buffers -pre_rot_buffers
@c00200 @c00200
-rotators -rotators
-rotators_top @800200
-top
@28 @28
mclt_test_06.mclt16x16_bayer3_i.dtt_rd_regen_r[1:0] mclt_test_06.mclt16x16_bayer3_i.inv_checker
@c00200 mclt_test_06.mclt16x16_bayer3_i.set_inv_checker
-mclt_test_06.mclt16x16_bayer3_i.dtt_rd_ra_r @22
mclt_test_06.mclt16x16_bayer3_i.in_cntr[7:0]
@28
mclt_test_06.mclt16x16_bayer3_i.inv_checker_rf_ram_reg
mclt_test_06.mclt16x16_bayer3_i.page
@22
mclt_test_06.mclt16x16_bayer3_i.regs_wa[1:0]
@200
-
@1000200
-top
@800028
mclt_test_06.mclt16x16_bayer3_i.copy_regs[1:0]
@28
(0)mclt_test_06.mclt16x16_bayer3_i.copy_regs[1:0]
(1)mclt_test_06.mclt16x16_bayer3_i.copy_regs[1:0]
@1001200
-group_end
@c00022
mclt_test_06.mclt16x16_bayer3_i.rot_ram_page[3:0]
@28
(0)mclt_test_06.mclt16x16_bayer3_i.rot_ram_page[3:0]
(1)mclt_test_06.mclt16x16_bayer3_i.rot_ram_page[3:0]
(2)mclt_test_06.mclt16x16_bayer3_i.rot_ram_page[3:0]
(3)mclt_test_06.mclt16x16_bayer3_i.rot_ram_page[3:0]
@1401200 @1401200
-group_end -group_end
@28
(1)mclt_test_06.mclt16x16_bayer3_i.rot_ram_copy[1:0]
[color] 3
mclt_test_06.mclt16x16_bayer3_i.inv_checker_rot_ram_reg
mclt_test_06.mclt16x16_bayer3_i.valid_odd_rot_ram_reg
@22
mclt_test_06.mclt16x16_bayer3_i.y_shft_rot_ram_reg[6:0]
mclt_test_06.mclt16x16_bayer3_i.x_shft_rot_ram_reg[6:0]
@200
-
@c00200
-rotators_top
@28
mclt_test_06.mclt16x16_bayer3_i.dtt_rd_regen_r[1:0]
@22 @22
mclt_test_06.mclt16x16_bayer3_i.dtt_rd_data_r[24:0] mclt_test_06.mclt16x16_bayer3_i.dtt_rd_data_r[24:0]
@28 @28
...@@ -413,9 +552,9 @@ mclt_test_06.mclt16x16_bayer3_i.phase_rotator_r_i.odd_rows ...@@ -413,9 +552,9 @@ mclt_test_06.mclt16x16_bayer3_i.phase_rotator_r_i.odd_rows
mclt_test_06.mclt16x16_bayer3_i.phase_rotator_r_i.inv[2:0] mclt_test_06.mclt16x16_bayer3_i.phase_rotator_r_i.inv[2:0]
@28 @28
(1)mclt_test_06.mclt16x16_bayer3_i.phase_rotator_r_i.dtt_start_out[1:0] (1)mclt_test_06.mclt16x16_bayer3_i.phase_rotator_r_i.dtt_start_out[1:0]
@22 @8022
mclt_test_06.mclt16x16_bayer3_i.phase_rotator_r_i.dtt_rd_cntr_pre[8:0] mclt_test_06.mclt16x16_bayer3_i.phase_rotator_r_i.in_addr_r[7:0]
@800200 @c00200
-rotator -rotator
@28 @28
mclt_test_06.mclt16x16_bayer3_i.phase_rotator_r_i.phase_rotator0_i.start mclt_test_06.mclt16x16_bayer3_i.phase_rotator_r_i.phase_rotator0_i.start
...@@ -483,10 +622,11 @@ mclt_test_06.mclt16x16_bayer3_i.phase_rotator_r_i.phase_rotator0_i.ceb2_2 ...@@ -483,10 +622,11 @@ mclt_test_06.mclt16x16_bayer3_i.phase_rotator_r_i.phase_rotator0_i.ceb2_2
- -
@28 @28
mclt_test_06.mclt16x16_bayer3_i.phase_rotator_r_i.phase_rotator0_i.negm_1 mclt_test_06.mclt16x16_bayer3_i.phase_rotator_r_i.phase_rotator0_i.negm_1
@1000200 @1401200
-rotator -rotator
@1000200
-rotator_red -rotator_red
@c00200 @800200
-rotator_blue -rotator_blue
@28 @28
mclt_test_06.mclt16x16_bayer3_i.phase_rotator_b_i.start mclt_test_06.mclt16x16_bayer3_i.phase_rotator_b_i.start
...@@ -498,11 +638,10 @@ mclt_test_06.mclt16x16_bayer3_i.phase_rotator_b_i.inv[2:0] ...@@ -498,11 +638,10 @@ mclt_test_06.mclt16x16_bayer3_i.phase_rotator_b_i.inv[2:0]
@28 @28
(1)mclt_test_06.mclt16x16_bayer3_i.phase_rotator_b_i.dtt_start_out[1:0] (1)mclt_test_06.mclt16x16_bayer3_i.phase_rotator_b_i.dtt_start_out[1:0]
@22 @22
mclt_test_06.mclt16x16_bayer3_i.phase_rotator_b_i.dtt_rd_cntr_pre[8:0]
mclt_test_06.mclt16x16_bayer3_i.phase_rotator_b_i.in_addr_r[7:0] mclt_test_06.mclt16x16_bayer3_i.phase_rotator_b_i.in_addr_r[7:0]
@200 @200
- -
@1401200 @1000200
-rotator_blue -rotator_blue
@c00200 @c00200
-green_upstream -green_upstream
...@@ -523,7 +662,7 @@ mclt_test_06.mclt16x16_bayer3_i.dtt_rd_regen_g[1:0] ...@@ -523,7 +662,7 @@ mclt_test_06.mclt16x16_bayer3_i.dtt_rd_regen_g[1:0]
mclt_test_06.mclt16x16_bayer3_i.phase_rotator_g_i.fd_din[24:0] mclt_test_06.mclt16x16_bayer3_i.phase_rotator_g_i.fd_din[24:0]
@1401200 @1401200
-green_upstream -green_upstream
@c00200 @800200
-rotator_green -rotator_green
@28 @28
mclt_test_06.mclt16x16_bayer3_i.phase_rotator_g_i.start mclt_test_06.mclt16x16_bayer3_i.phase_rotator_g_i.start
...@@ -551,8 +690,8 @@ mclt_test_06.mclt16x16_bayer3_i.phase_rotator_g_i.phase_rotator0_i.start ...@@ -551,8 +690,8 @@ mclt_test_06.mclt16x16_bayer3_i.phase_rotator_g_i.phase_rotator0_i.start
- -
@1000200 @1000200
-rotator -rotator
@1401200
-rotator_green -rotator_green
@1401200
-rotators -rotators
[pattern_trace] 1 [pattern_trace] 1
[pattern_trace] 0 [pattern_trace] 0
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