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x393
Commit faaa504f authored by Andrey Filippov's avatar Andrey Filippov
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added DQS_IDELAY vs PHASE measurement/calculation

parent 3d603296
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Showing with 1093 additions and 76 deletions
py393/get_test_dq_dqs_data.py
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py393/x393_lma.py
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py393/x393_mcntrl_adjust.py
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py393/x393_pio_sequences.py
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...@@ -441,13 +441,17 @@ class X393PIOSequences(object): ...@@ -441,13 +441,17 @@ class X393PIOSequences(object):
ba, # input [ 2:0] ba; ba, # input [ 2:0] ba;
ra, # input [14:0] ra; ra, # input [14:0] ra;
ca, #input [ 9:0] ca; ca, #input [ 9:0] ca;
num8=64,
sel=1,
verbose=0): verbose=0):
""" """
Setup read block sequence at parameter defined address in the sequencer memory Setup read block sequence at parameter defined address in the sequencer memory
<ba> 3-bit memory bank address @ba 3-bit memory bank address
<ra> 15-bit memory row address @ra 15-bit memory row address
<ca> 10-bit memory column address @ca 10-bit memory column address
<verbose> print data being written (default: False) @num8 - number of 8-bursts to read (maximal 64, min- 2)
@sel - 0 - early, 1 - late read command
@verbose print data being written (default: False)
""" """
cmd_addr = vrlg.MCONTR_CMD_WR_ADDR + vrlg.READ_BLOCK_OFFSET cmd_addr = vrlg.MCONTR_CMD_WR_ADDR + vrlg.READ_BLOCK_OFFSET
...@@ -464,34 +468,34 @@ class X393PIOSequences(object): ...@@ -464,34 +468,34 @@ class X393PIOSequences(object):
# first read # first read
# read # read
# addr bank RCW ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD NOP, B_RST # addr bank RCW ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD NOP, B_RST
data=self.func_encode_cmd(ca&0x3ff, ba, 2, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0) data=self.func_encode_cmd(ca&0x3ff, ba, 2, 0, 0, sel, 0, 0, 0, 1, 1, 0, 0, 0)
self.x393_mem.axi_write_single_w(cmd_addr, data, verbose) self.x393_mem.axi_write_single_w(cmd_addr, data, verbose)
cmd_addr += 1 cmd_addr += 1
# nop # nop
# skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST # skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
data=self.func_encode_skip( 0, 0, ba, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0) data=self.func_encode_skip( 0, 0, ba, 0, 0, sel, 0, 0, 0, 1, 1, 0, 0)
self.x393_mem.axi_write_single_w(cmd_addr, data, verbose) self.x393_mem.axi_write_single_w(cmd_addr, data, verbose)
cmd_addr += 1 cmd_addr += 1
#repeat remaining reads #repeat remaining reads
for i in range(1,64): for i in range(1,num8):
# read # read
# addr bank RCW ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD NOP, B_RST # addr bank RCW ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD NOP, B_RST
data=self.func_encode_cmd((ca & 0x3ff)+(i<<3),ba, 2, 0, 0, 1, 0, 0, 0, 1, 1, 0, 1, 0) data=self.func_encode_cmd((ca & 0x3ff)+(i<<3),ba, 2, 0, 0, sel, 0, 0, 0, 1, 1, 0, 1, 0)
self.x393_mem.axi_write_single_w(cmd_addr, data, verbose) self.x393_mem.axi_write_single_w(cmd_addr, data, verbose)
cmd_addr += 1 cmd_addr += 1
# nop - all 3 below are the same? - just repeat? # nop - all 3 below are the same? - just repeat?
# skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST # skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
data=self.func_encode_skip( 0, 0, ba, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0) data=self.func_encode_skip( 0, 0, ba, 0, 0, sel, 0, 0, 0, 1, 0, 0, 0)
self.x393_mem.axi_write_single_w(cmd_addr, data, verbose) self.x393_mem.axi_write_single_w(cmd_addr, data, verbose)
cmd_addr += 1 cmd_addr += 1
# nop # nop
# skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST # skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
data=self.func_encode_skip( 0, 0, ba, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0) data=self.func_encode_skip( 0, 0, ba, 0, 0, sel, 0, 0, 0, 1, 0, 0, 0)
self.x393_mem.axi_write_single_w(cmd_addr, data, verbose) self.x393_mem.axi_write_single_w(cmd_addr, data, verbose)
cmd_addr += 1 cmd_addr += 1
# nop # nop
# skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST # skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
data=self.func_encode_skip( 0, 0, ba, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0) data=self.func_encode_skip( 0, 0, ba, 0, 0, sel, 0, 0, 0, 1, 0, 0, 0)
self.x393_mem.axi_write_single_w(cmd_addr, data, verbose) self.x393_mem.axi_write_single_w(cmd_addr, data, verbose)
cmd_addr += 1 cmd_addr += 1
# tRTP = 4*tCK is already satisfied, no skip here # tRTP = 4*tCK is already satisfied, no skip here
......
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