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Elphel
x393
Commits
faaa504f
Commit
faaa504f
authored
Mar 31, 2015
by
Andrey Filippov
Browse files
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added DQS_IDELAY vs PHASE measurement/calculation
parent
3d603296
Changes
4
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Showing
4 changed files
with
1093 additions
and
76 deletions
+1093
-76
get_test_dq_dqs_data.py
py393/get_test_dq_dqs_data.py
+321
-1
x393_lma.py
py393/x393_lma.py
+317
-25
x393_mcntrl_adjust.py
py393/x393_mcntrl_adjust.py
+440
-39
x393_pio_sequences.py
py393/x393_pio_sequences.py
+15
-11
No files found.
py393/get_test_dq_dqs_data.py
View file @
faaa504f
...
...
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\ No newline at end of file
]
def
get_dqi_dqsi
():
return
{
'early'
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None
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0
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0
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None
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None
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0
,
1
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0
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0
,
0
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0
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[
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,
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None
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None
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None
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None
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0
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0
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2
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0
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0
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None
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None
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None
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None
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None
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None
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None
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0
,
2
,
0
,
0
,
0
,
0
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[
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None
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None
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None
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None
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None
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None
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4
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5
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2
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6
,
1
,
3
,
0
,
3
],
[
None
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None
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None
,
None
,
None
,
None
,
None
,
None
,
4
,
5
,
2
,
6
,
1
,
3
,
0
,
3
],
[
None
,
None
,
None
,
None
,
None
,
None
,
None
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None
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4
,
5
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2
,
6
,
1
,
3
,
0
,
3
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None
,
None
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None
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None
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None
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None
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None
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5
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6
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1
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0
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3
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1
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0
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0
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3
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0
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0
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9
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7
,
11
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5
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8
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4
,
7
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[
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,
0
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0
,
0
,
3
,
0
,
0
,
0
,
9
,
10
,
7
,
11
,
6
,
8
,
5
,
8
],
[
2
,
0
,
0
,
0
,
3
,
0
,
0
,
0
,
9
,
10
,
7
,
11
,
6
,
8
,
5
,
8
],
[
2
,
0
,
1
,
0
,
4
,
0
,
0
,
0
,
10
,
11
,
7
,
12
,
6
,
9
,
5
,
8
],
[
3
,
0
,
1
,
0
,
4
,
0
,
1
,
0
,
10
,
11
,
8
,
12
,
7
,
9
,
6
,
9
],
[
7
,
2
,
5
,
3
,
8
,
4
,
5
,
2
,
14
,
15
,
12
,
16
,
11
,
13
,
10
,
13
],
[
7
,
3
,
5
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3
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9
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5
,
5
,
2
,
14
,
15
,
12
,
16
,
11
,
13
,
10
,
13
],
[
7
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3
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5
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3
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9
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5
,
5
,
2
,
14
,
15
,
12
,
16
,
11
,
14
,
10
,
13
],
[
8
,
3
,
6
,
4
,
9
,
5
,
6
,
3
,
15
,
16
,
12
,
17
,
11
,
14
,
10
,
13
],
[
8
,
3
,
6
,
4
,
10
,
6
,
6
,
3
,
15
,
16
,
13
,
17
,
12
,
14
,
11
,
14
],
[
12
,
8
,
10
,
8
,
14
,
10
,
10
,
7
,
19
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20
,
16
,
21
,
15
,
18
,
14
,
17
],
[
13
,
8
,
11
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9
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15
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10
,
11
,
8
,
19
,
20
,
17
,
21
,
16
,
18
,
15
,
18
],
[
13
,
8
,
11
,
9
,
14
,
10
,
11
,
8
,
19
,
20
,
17
,
21
,
16
,
18
,
15
,
18
],
[
13
,
9
,
11
,
9
,
15
,
11
,
11
,
8
,
19
,
21
,
17
,
22
,
16
,
19
,
15
,
18
],
[
14
,
9
,
12
,
10
,
15
,
11
,
12
,
9
,
20
,
21
,
18
,
22
,
17
,
19
,
16
,
19
],
[
18
,
13
,
16
,
13
,
19
,
15
,
16
,
12
,
24
,
25
,
21
,
26
,
20
,
23
,
19
,
22
],
[
19
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13
,
16
,
14
,
20
,
16
,
16
,
13
,
24
,
25
,
22
,
26
,
21
,
23
,
20
,
23
],
[
18
,
13
,
16
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14
,
20
,
16
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16
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13
,
24
,
25
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22
,
26
,
21
,
23
,
20
,
23
],
[
19
,
14
,
17
,
15
,
20
,
16
,
17
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14
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24
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26
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22
,
27
,
21
,
24
,
20
,
23
],
[
19
,
14
,
17
,
15
,
21
,
16
,
17
,
14
,
25
,
26
,
23
,
27
,
21
,
24
,
21
,
24
],
[
24
,
18
,
21
,
19
,
25
,
20
,
21
,
18
,
29
,
30
,
26
,
31
,
25
,
28
,
24
,
27
],
[
24
,
19
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22
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20
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26
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21
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22
,
19
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29
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30
,
27
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31
,
25
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28
,
24
,
28
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[
24
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19
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22
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19
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26
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21
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22
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18
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29
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30
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27
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32
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26
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28
,
25
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28
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[
25
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19
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22
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20
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26
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22
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22
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19
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29
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27
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26
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29
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,
28
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[
25
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20
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22
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20
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26
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22
,
23
,
19
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30
,
31
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28
,
32
,
26
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29
,
25
,
29
],
[
29
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23
,
26
,
24
,
30
,
26
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120
,
115
,
119
],
[
113
,
104
,
106
,
105
,
114
,
107
,
110
,
103
,
120
,
121
,
119
,
126
,
116
,
120
,
115
,
120
],
[
114
,
104
,
107
,
105
,
115
,
107
,
111
,
103
,
120
,
122
,
119
,
126
,
117
,
120
,
116
,
120
],
[
118
,
109
,
111
,
109
,
119
,
112
,
115
,
108
,
125
,
126
,
123
,
130
,
121
,
125
,
120
,
124
],
[
119
,
109
,
112
,
110
,
120
,
112
,
116
,
108
,
125
,
126
,
123
,
131
,
121
,
125
,
120
,
125
],
[
119
,
109
,
112
,
110
,
119
,
112
,
115
,
108
,
125
,
126
,
124
,
131
,
121
,
125
,
120
,
125
],
[
119
,
110
,
112
,
110
,
120
,
113
,
116
,
109
,
125
,
127
,
124
,
131
,
122
,
125
,
121
,
125
],
[
120
,
110
,
112
,
111
,
120
,
113
,
116
,
109
,
126
,
127
,
124
,
132
,
122
,
126
,
121
,
126
],
[
123
,
114
,
116
,
114
,
124
,
117
,
120
,
113
,
130
,
131
,
128
,
136
,
126
,
130
,
125
,
129
],
[
124
,
114
,
117
,
115
,
125
,
117
,
121
,
113
,
130
,
131
,
129
,
136
,
126
,
130
,
125
,
130
],
[
124
,
114
,
117
,
115
,
125
,
117
,
121
,
113
,
130
,
131
,
129
,
136
,
126
,
130
,
125
,
130
],
[
124
,
115
,
117
,
115
,
125
,
118
,
121
,
114
,
130
,
132
,
129
,
137
,
127
,
131
,
126
,
130
],
[
125
,
115
,
117
,
116
,
126
,
118
,
122
,
114
,
131
,
132
,
129
,
137
,
127
,
131
,
126
,
131
],
[
129
,
119
,
121
,
120
,
130
,
122
,
126
,
118
,
135
,
136
,
133
,
141
,
131
,
135
,
130
,
135
],
[
130
,
119
,
122
,
120
,
130
,
123
,
126
,
118
,
135
,
136
,
134
,
141
,
131
,
135
,
130
,
135
],
[
130
,
119
,
122
,
120
,
130
,
123
,
126
,
118
,
135
,
136
,
134
,
141
,
131
,
135
,
130
,
135
],
[
130
,
120
,
122
,
121
,
131
,
123
,
127
,
119
,
136
,
137
,
134
,
142
,
132
,
136
,
131
,
135
],
[
130
,
120
,
123
,
121
,
131
,
123
,
127
,
119
,
136
,
137
,
135
,
142
,
132
,
136
,
131
,
136
],
[
134
,
124
,
126
,
125
,
135
,
127
,
131
,
123
,
140
,
141
,
138
,
146
,
136
,
140
,
135
,
140
],
[
135
,
125
,
127
,
125
,
136
,
128
,
132
,
124
,
140
,
141
,
139
,
147
,
136
,
140
,
135
,
140
],
[
135
,
125
,
127
,
125
,
136
,
128
,
131
,
123
,
140
,
142
,
139
,
147
,
136
,
140
,
136
,
140
],
[
135
,
125
,
127
,
126
,
136
,
128
,
132
,
124
,
141
,
142
,
139
,
147
,
137
,
141
,
136
,
141
],
[
136
,
125
,
128
,
126
,
136
,
129
,
132
,
124
,
141
,
142
,
140
,
148
,
137
,
141
,
136
,
141
],
[
140
,
129
,
132
,
130
,
140
,
133
,
136
,
128
,
145
,
146
,
144
,
152
,
141
,
145
,
140
,
145
],
[
141
,
130
,
132
,
131
,
141
,
133
,
137
,
129
,
145
,
147
,
144
,
152
,
141
,
145
,
140
,
145
],
[
140
,
130
,
132
,
131
,
141
,
133
,
137
,
129
,
145
,
147
,
144
,
152
,
142
,
146
,
141
,
145
],
[
141
,
130
,
133
,
131
,
142
,
134
,
137
,
129
,
146
,
147
,
144
,
152
,
142
,
146
,
141
,
146
],
[
141
,
131
,
133
,
131
,
142
,
134
,
138
,
130
,
146
,
147
,
145
,
153
,
142
,
146
,
141
,
146
],
[
145
,
135
,
137
,
135
,
146
,
138
,
142
,
133
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
],
[
146
,
135
,
138
,
136
,
147
,
139
,
143
,
134
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
],
[
146
,
135
,
138
,
136
,
147
,
138
,
142
,
134
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
],
[
146
,
136
,
138
,
136
,
147
,
139
,
143
,
134
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
],
[
147
,
136
,
138
,
137
,
147
,
139
,
143
,
135
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
],
[
150
,
139
,
142
,
140
,
151
,
143
,
147
,
138
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
],
[
151
,
140
,
142
,
141
,
152
,
143
,
148
,
139
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
],
[
151
,
140
,
142
,
141
,
152
,
143
,
147
,
139
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
],
[
152
,
140
,
143
,
141
,
152
,
144
,
148
,
139
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
],
[
152
,
141
,
143
,
142
,
152
,
144
,
148
,
140
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
],
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
]
}
def
get_adjust_cmda_odelay
():
return
{
'cmda_odly_period'
:
-
1
,
'cmda_fine_corr'
:[
0.030713940147897745
,
-
0.31142995369410897
,
0.25855967931439255
,
0.33272217450114078
,
-
0.044430686684212156
],
'cmda_odly_b'
:
45.0047826387
,
'cmda_bspe'
:[{
'ldly'
:
45
,
'period'
:
-
1
,
'err'
:
-
0.035496578892797004
},
{
'ldly'
:
44
,
'period'
:
-
1
,
'err'
:
0.44070548107222152
},
{
'ldly'
:
42
,
'period'
:
-
1
,
'err'
:
-
0.46122745179348357
},
{
'ldly'
:
41
,
'period'
:
-
1
,
'err'
:
0.50981961434792566
},
{
'ldly'
:
39
,
'period'
:
-
1
,
'err'
:
-
0.35612221952906253
},
{
'ldly'
:
38
,
'period'
:
-
1
,
'err'
:
-
0.33221764758151551
},
{
'ldly'
:
37
,
'period'
:
-
1
,
'err'
:
0.1430022807381377
},
{
'ldly'
:
35
,
'period'
:
-
1
,
'err'
:
-
0.22809454696245979
},
{
'ldly'
:
34
,
'period'
:
-
1
,
'err'
:
0.24810751300255873
},
{
'ldly'
:
33
,
'period'
:
-
1
,
'err'
:
0.27201208495010576
},
{
'ldly'
:
31
,
'period'
:
-
1
,
'err'
:
0.31722164627826288
},
{
'ldly'
:
30
,
'period'
:
-
1
,
'err'
:
0.37613518556916148
},
{
'ldly'
:
28
,
'period'
:
-
1
,
'err'
:
-
0.52481561565117474
},
{
'ldly'
:
27
,
'period'
:
-
1
,
'err'
:
-
0.049595687331521532
},
{
'ldly'
:
25
,
'period'
:
-
1
,
'err'
:
-
0.42069251503212257
},
{
'ldly'
:
24
,
'period'
:
-
1
,
'err'
:
0.055509544932892396
},
{
'ldly'
:
23
,
'period'
:
-
1
,
'err'
:
0.079414116880446528
},
{
'ldly'
:
21
,
'period'
:
-
1
,
'err'
:
0.1246236782086001
},
{
'ldly'
:
20
,
'period'
:
-
1
,
'err'
:
0.18353721749949869
},
{
'ldly'
:
19
,
'period'
:
-
1
,
'err'
:
0.65973927746451366
},
{
'ldly'
:
17
,
'period'
:
-
1
,
'err'
:
-
0.24219365540118432
},
{
'ldly'
:
15
,
'period'
:
-
1
,
'err'
:
-
0.61329048310178536
},
{
'ldly'
:
14
,
'period'
:
-
1
,
'err'
:
-
0.13708842313677039
},
{
'ldly'
:
13
,
'period'
:
-
1
,
'err'
:
-
0.11318385118921803
},
{
'ldly'
:
11
,
'period'
:
-
1
,
'err'
:
-
0.067974289861062687
},
{
'ldly'
:
10
,
'period'
:
-
1
,
'err'
:
-
0.0090607505701782998
},
{
'ldly'
:
9
,
'period'
:
-
1
,
'err'
:
0.46714130939483667
},
{
'ldly'
:
7
,
'period'
:
-
1
,
'err'
:
-
0.4347916234708622
},
{
'ldly'
:
6
,
'period'
:
-
1
,
'err'
:
0.53625544267054437
},
{
'ldly'
:
4
,
'period'
:
-
1
,
'err'
:
-
0.32968639120644738
},
{
'ldly'
:
3
,
'period'
:
-
1
,
'err'
:
-
0.30578181925889458
},
{
'ldly'
:
2
,
'period'
:
-
1
,
'err'
:
0.16943810906075885
},
{
'ldly'
:
0
,
'period'
:
-
1
,
'err'
:
-
0.20165871863984108
},
{
'ldly'
:
156
,
'period'
:
0
,
'err'
:
0.62311009744971102
},
{
'ldly'
:
154
,
'period'
:
0
,
'err'
:
-
0.24283173642726297
},
{
'ldly'
:
153
,
'period'
:
0
,
'err'
:
-
0.21892716447970884
},
{
'ldly'
:
151
,
'period'
:
0
,
'err'
:
-
0.17371760315154461
},
{
'ldly'
:
150
,
'period'
:
0
,
'err'
:
-
0.11480406386064601
},
{
'ldly'
:
149
,
'period'
:
0
,
'err'
:
0.36139799610438672
},
{
'ldly'
:
148
,
'period'
:
0
,
'err'
:
0.38530256805194085
},
{
'ldly'
:
146
,
'period'
:
0
,
'err'
:
0.43051212938004824
},
{
'ldly'
:
144
,
'period'
:
0
,
'err'
:
-
0.43542970449692575
},
{
'ldly'
:
143
,
'period'
:
0
,
'err'
:
-
0.41152513254937162
},
{
'ldly'
:
142
,
'period'
:
0
,
'err'
:
0.063694795770260271
},
{
'ldly'
:
140
,
'period'
:
0
,
'err'
:
-
0.30740203193033722
},
{
'ldly'
:
139
,
'period'
:
0
,
'err'
:
0.16880002803469552
},
{
'ldly'
:
138
,
'period'
:
0
,
'err'
:
0.19270459998224965
},
{
'ldly'
:
136
,
'period'
:
0
,
'err'
:
0.23791416131038545
},
{
'ldly'
:
135
,
'period'
:
0
,
'err'
:
0.29682770060128405
},
{
'ldly'
:
133
,
'period'
:
0
,
'err'
:
-
0.6041231006190344
},
{
'ldly'
:
132
,
'period'
:
0
,
'err'
:
-
0.12890317229940251
},
{
'ldly'
:
130
,
'period'
:
0
,
'err'
:
-
0.5
},
{
'ldly'
:
129
,
'period'
:
0
,
'err'
:
-
0.023797940034967269
},
{
'ldly'
:
128
,
'period'
:
0
,
'err'
:
0.00010663191257265225
},
{
'ldly'
:
126
,
'period'
:
0
,
'err'
:
0.045316193240722669
},
{
'ldly'
:
125
,
'period'
:
0
,
'err'
:
0.10422973253162127
},
{
'ldly'
:
124
,
'period'
:
0
,
'err'
:
0.58043179249663979
},
{
'ldly'
:
122
,
'period'
:
0
,
'err'
:
-
0.32150114036905109
},
{
'ldly'
:
121
,
'period'
:
0
,
'err'
:
0.64954592577234394
},
{
'ldly'
:
119
,
'period'
:
0
,
'err'
:
-
0.21639590810464426
},
{
'ldly'
:
118
,
'period'
:
0
,
'err'
:
-
0.19249133615709013
},
{
'ldly'
:
116
,
'period'
:
0
,
'err'
:
-
0.14728177482894012
},
{
'ldly'
:
115
,
'period'
:
0
,
'err'
:
-
0.088368235538041517
},
{
'ldly'
:
114
,
'period'
:
0
,
'err'
:
0.387833824426977
},
{
'ldly'
:
113
,
'period'
:
0
,
'err'
:
0.41173839637453113
},
{
'ldly'
:
111
,
'period'
:
0
,
'err'
:
0.45694795770268115
},
{
'ldly'
:
109
,
'period'
:
0
,
'err'
:
-
0.40899387617430705
},
{
'ldly'
:
108
,
'period'
:
0
,
'err'
:
-
0.38508930422675292
},
{
'ldly'
:
107
,
'period'
:
0
,
'err'
:
0.090130624092907397
},
{
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:
105
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:
0
,
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:
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:
104
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:
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:
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:
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:
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:
101
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:
0
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:
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:
100
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:
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:
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:
98
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:
0
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:
-
0.5776872722964157
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:
97
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:
0
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:
-
0.10246734397675539
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{
'ldly'
:
95
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:
0
,
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:
-
0.47356417167736709
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{
'ldly'
:
94
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:
0
,
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:
0.0026378882876372245
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{
'ldly'
:
93
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:
0
,
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:
0.026542460235191356
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{
'ldly'
:
91
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:
0
,
'err'
:
0.071752021563355584
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'ldly'
:
90
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:
0
,
'err'
:
0.13066556085423997
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:
89
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:
0
,
'err'
:
0.60686762081925849
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{
'ldly'
:
87
,
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:
0
,
'err'
:
-
0.29506531204643238
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:
85
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:
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:
-
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:
84
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:
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:
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:
83
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:
0
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:
-
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'ldly'
:
81
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:
0
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'err'
:
-
0.12084594650632141
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'ldly'
:
80
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:
0
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'err'
:
-
0.061932407215422813
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'ldly'
:
79
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:
0
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'err'
:
0.41426965274959571
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'ldly'
:
78
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:
0
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:
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:
76
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:
0
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74
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0
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:
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:
73
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:
0
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:
-
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:
72
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0
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:
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:
70
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:
0
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:
-
0.2545303752850856
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'ldly'
:
69
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:
0
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'err'
:
0.22167168467993292
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'ldly'
:
68
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:
0
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'err'
:
0.24557625662748706
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'ldly'
:
66
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:
0
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'err'
:
0.29078581795562286
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:
65
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:
0
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:
0.34969935724652146
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'ldly'
:
63
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:
0
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'err'
:
-
0.5512514439738041
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'ldly'
:
62
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:
0
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'err'
:
-
0.076031515654150894
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'ldly'
:
60
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:
0
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:
-
0.44712834335474838
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'ldly'
:
59
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:
0
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:
0.029073716610277245
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58
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0
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:
56
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:
0
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:
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'ldly'
:
55
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'period'
:
0
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'err'
:
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{
'ldly'
:
54
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'period'
:
0
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'err'
:
0.6333034491418843
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{
'ldly'
:
52
,
'period'
:
0
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'err'
:
-
0.26862948372382078
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{
'ldly'
:
50
,
'period'
:
0
,
'err'
:
-
0.63972631142441827
},
{
'ldly'
:
49
,
'period'
:
0
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'err'
:
-
0.16352425145939975
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{
'ldly'
:
48
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'period'
:
0
,
'err'
:
-
0.13961967951185272
},
{
'ldly'
:
46
,
'period'
:
0
,
'err'
:
-
0.094410118183695602
}],
'cmda_odly_a'
:
-
1.40105743313
}
def
get_wlev_data
():
return
{
'wlev_dqs_odly_b'
:[
52.119267926792674
,
49.885802580258002
],
'wlev_dqs_period'
:[
-
1
,
-
1
],
'wlev_dqs_bspe'
:[[{
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:
53
,
'period'
:
-
1
,
'err'
:
0.15836650331700497
},
{
'ldly'
:
52
,
'period'
:
-
1
,
'err'
:
0.58329899656632733
},
{
'ldly'
:
49
,
'period'
:
-
1
,
'err'
:
-
0.10726153212335987
},
{
'ldly'
:
48
,
'period'
:
-
1
,
'err'
:
-
0.30379371270459643
},
{
'ldly'
:
47
,
'period'
:
-
1
,
'err'
:
0.12113878054472593
},
{
'ldly'
:
44
,
'period'
:
-
1
,
'err'
:
-
0.56942174814496838
},
{
'ldly'
:
43
,
'period'
:
-
1
,
'err'
:
-
0.76595392872619783
},
{
'ldly'
:
41
,
'period'
:
-
1
,
'err'
:
0.095354535453544997
},
{
'ldly'
:
39
,
'period'
:
-
1
,
'err'
:
-
1.0315819641665698
},
{
'ldly'
:
39
,
'period'
:
-
1
,
'err'
:
0.48103129715956783
},
{
'ldly'
:
38
,
'period'
:
-
1
,
'err'
:
0.28449911657833127
},
{
'ldly'
:
37
,
'period'
:
-
1
,
'err'
:
0.70943160982765363
},
{
'ldly'
:
34
,
'period'
:
-
1
,
'err'
:
0.018871081137966428
},
{
'ldly'
:
33
,
'period'
:
-
1
,
'err'
:
-
0.17766109944327013
},
{
'ldly'
:
32
,
'period'
:
-
1
,
'err'
:
0.24727139380605223
},
{
'ldly'
:
29
,
'period'
:
-
1
,
'err'
:
-
0.44328913488363497
},
{
'ldly'
:
28
,
'period'
:
-
1
,
'err'
:
-
0.63982131546487508
},
{
'ldly'
:
25
,
'period'
:
-
1
,
'err'
:
-
0.19156715671566715
},
{
'ldly'
:
24
,
'period'
:
-
1
,
'err'
:
-
0.90544935090523637
},
{
'ldly'
:
24
,
'period'
:
-
1
,
'err'
:
0.60716391042089768
},
{
'ldly'
:
21
,
'period'
:
-
1
,
'err'
:
-
0.2406730673067301
},
{
'ldly'
:
22
,
'period'
:
-
1
,
'err'
:
0.83556422308897993
},
{
'ldly'
:
19
,
'period'
:
-
1
,
'err'
:
0.14500369439929628
},
{
'ldly'
:
18
,
'period'
:
-
1
,
'err'
:
-
0.051528486181947386
},
{
'ldly'
:
17
,
'period'
:
-
1
,
'err'
:
0.37340400706738208
},
{
'ldly'
:
14
,
'period'
:
-
1
,
'err'
:
-
0.3171565216223069
},
{
'ldly'
:
13
,
'period'
:
-
1
,
'err'
:
-
0.51368870220354701
},
{
'ldly'
:
10
,
'period'
:
-
1
,
'err'
:
-
0.065434543454344407
},
{
'ldly'
:
9
,
'period'
:
-
1
,
'err'
:
-
0.7793167376439083
},
{
'ldly'
:
9
,
'period'
:
-
1
,
'err'
:
0.7332965236822222
},
{
'ldly'
:
6
,
'period'
:
-
1
,
'err'
:
-
0.11454045404540381
},
{
'ldly'
:
7
,
'period'
:
-
1
,
'err'
:
0.96169683635031067
},
{
'ldly'
:
4
,
'period'
:
-
1
,
'err'
:
0.27113630766062169
},
{
'ldly'
:
3
,
'period'
:
-
1
,
'err'
:
0.074604127079380245
},
{
'ldly'
:
2
,
'period'
:
-
1
,
'err'
:
0.49953662032870971
},
{
'ldly'
:
2
,
'period'
:
-
1
,
'err'
:
2.0121498816548402
},
{
'ldly'
:
2
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:
-
1
,
'err'
:
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},
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:
0
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:
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1
,
'err'
:
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:
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:
0
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:
-
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:
159
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:
0
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'err'
:
-
3.5532561315833107
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:
159
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:
0
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'err'
:
-
2.0406428702571873
},
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'ldly'
:
159
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:
0
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'err'
:
-
0.52802960893103545
},
{
'ldly'
:
158
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:
0
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'err'
:
-
0.72456178951227912
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:
156
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:
0
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'err'
:
0.1367466746674495
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:
154
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:
0
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'err'
:
-
0.99018982495266528
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:
154
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:
0
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'err'
:
0.52242343637348654
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:
151
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:
0
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'err'
:
-
0.3254135413541519
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'ldly'
:
152
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:
0
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:
0.75082374904158655
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:
149
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:
0
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:
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:
148
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:
0
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:
-
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'ldly'
:
147
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:
0
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'err'
:
0.28866353301995673
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:
144
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:
0
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:
-
0.40189699566974468
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'ldly'
:
143
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:
0
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:
-
0.59842917625095993
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:
140
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:
0
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:
-
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:
139
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:
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:
-
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:
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:
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:
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:
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:
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:
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:
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:
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:
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:
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:
-
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:
128
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:
0
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:
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:
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:
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:
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:
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:
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:
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:
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:
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:
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:
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:
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:
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:
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:
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:
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:
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:
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:
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:
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:
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:
114
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:
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:
-
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:
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:
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:
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:
112
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:
0
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:
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:
109
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:
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:
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:
108
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:
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:
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:
106
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:
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:
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:
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:
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:
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:
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:
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:
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:
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:
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:
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:
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:
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:
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:
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:
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:
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:
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:
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:
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:
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:
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:
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:
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:
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:
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:
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:
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:
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:
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:
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:
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:
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'wlev_dqs_odly_a'
:[
-
1.5126132613261327
,
-
1.4928112811281129
],
'wlev_dqs_fine_corr'
:[[
-
1.2132753275327497
,
-
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,
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,
0.72236556989032386
,
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],
[
-
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,
-
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,
-
0.53355535553554745
,
0.96330402270997262
,
0.081728172817291833
]],
}
def
get_dqi_dqsi_parameters
():
return
[{
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,
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,
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,
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,
-
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,
-
66.850049366341011
],
'tDQSHL'
:
33.630627491376956
,
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:
[
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,
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,
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18.181179822359098
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,
11.405923805850376
,
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18.928113920491676
,
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8.1128573798139989
,
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17.408789192927088
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1.6784422575078048
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5.7664758916114911
,
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18.231183132897023
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0.46315232003504803
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8.8850427413296931
,
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16.381481961618071
,
-
6.1174342247526683
,
-
0.82283483445295313
,
6.7778815926356089
],
'tCDQS'
:
[
-
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,
-
7.2757801319630229
,
-
2.5421518060152657
,
-
7.5603992191772083
,
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2.2055383942761204
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6.567005178636669
,
2.2874275225718126
,
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2.4826716594707356
,
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3.9070988518160283
,
-
7.0454853282507406
,
-
7.0592219194082384
,
-
11.875950010996496
,
-
8.1897709787402579
,
-
8.8611382356966004
,
-
7.4771065174616496
,
-
7.9803816333132609
,
-
8.5942156314275113
,
-
2.4121425692062815
,
0.33707038068398676
,
3.0848764289567301
,
3.8499782486228042
,
4.5061334038974064
,
4.6048528083479141
,
0.11787918795170077
,
-
3.0461173388003537
,
-
2.8646101441124636
,
1.2473306831273321
,
5.5221447897347211
,
5.5801911846440824
,
6.5311420195002867
],
'tDQ'
:
[
178.54993633069836
,
116.65061870453647
,
159.03578832976919
,
126.78532767972659
,
202.90886522937919
,
147.34955168578901
,
150.5973655908777
,
113.57908737512665
],
'tDQS'
:
0.0
,
'anaScale'
:
14.440746252956936
,
'tSDQS'
:
16.081739769147354
,
'tSDQ'
:
[
14.629922533518178
,
15.32021309800418
,
15.358553006242195
,
15.317433438991307
,
14.736478243160605
,
15.178983370614914
,
14.792911008035999
,
15.42410605101378
],
'tFDQS'
:
[
-
20.920976712365256
,
-
14.851051240024837
,
2.544249229934898
,
11.436496687716323
]},
{
'tDQHL'
:
[
-
46.92862204920484
,
-
45.873438129654339
,
-
169.48428151560637
,
-
108.63460880868871
,
-
99.945595444819844
,
-
114.23567500178559
,
-
79.910981307637172
,
-
108.15257217444315
],
'tDQSHL'
:
-
63.73607957321687
,
'tFDQ'
:
[
-
22.651208080162565
,
-
9.6742387595856307
,
1.6398758560518707
,
11.54610375430673
,
-
20.232881982908012
,
-
11.280847426552146
,
0.55718928848580018
,
9.1882686270403138
,
-
19.697511431229653
,
-
7.3788999105222377
,
-
3.0481680405296463
,
11.644035069268249
,
-
14.788579667174496
,
-
9.5382118978718218
,
1.0032294552390997
,
8.1729278773105705
,
-
21.378807382538035
,
-
9.5665771864962146
,
-
1.6206612289815727
,
10.87690300433092
,
-
19.567199352107099
,
-
7.8974633039664246
,
3.7463643516202096
,
9.296256580781975
,
-
21.677030891494294
,
-
11.638328204580649
,
1.2612350558170864
,
10.941149227972524
,
-
15.777849021516966
,
-
6.950745912105897
,
4.7761338973479601
,
6.1653134248130286
],
'tCDQS'
:
[
-
6.6540068568819404
,
-
9.710432593520018
,
-
10.898311539862851
,
-
8.3495211811059971
,
-
9.9648005738403533
,
-
9.8822240868698259
,
-
10.374184346489738
,
-
3.600757867511521
,
3.017721438680292
,
1.1439974675125524
,
3.5446130727629153
,
-
1.7810713995265357
,
-
3.7222951788697238
,
-
5.1561798397448477
,
-
6.8559122320934298
,
-
8.4425997702883766
,
-
6.7022369345283312
,
-
5.5222500342883594
,
-
5.3711888327888762
,
-
6.1798317970983154
,
-
3.1812468245595431
,
-
1.5243912445920293
,
-
3.8961253294496134
,
0.22045216697579145
,
0.60574328325657445
,
-
4.4894441298077377
,
-
0.63488407214268139
,
-
5.0567724757990842
,
-
3.5610372972266342
,
-
5.524375838152439
],
'tDQ'
:
[
403.59125625398372
,
419.2736920286585
,
368.27332134758177
,
424.54923786790363
,
354.16339946510629
,
389.42079118966922
,
339.42258324461545
,
382.15216838629846
],
'tDQS'
:
0.0
,
'anaScale'
:
15.848122667310021
,
'tSDQS'
:
15.054401696282699
,
'tSDQ'
:
[
15.090935942384293
,
15.068960000988493
,
14.991028033299427
,
14.592811409659639
,
15.152223949474106
,
14.983660572919542
,
15.150210715479881
,
14.9599076073857
],
'tFDQS'
:
[
-
21.824409224001187
,
-
10.830180678770162
,
1.5698858542328959
,
11.267851084349177
]}]
def
get_dqsi_vs_phase
(
variant
):
if
variant
==
0
:
return
[[(
37
,
0.25
,
'n'
),
(
20
,
0.25
,
'n'
)],
[(
35
,
None
,
'n'
),
(
23
,
0.0
,
'n'
)],
[(
35
,
None
,
'n'
),
(
24
,
-
0.5
,
'n'
)],
[(
40
,
0.25
,
'n'
),
(
20
,
None
,
'n'
)],
[(
42
,
0.25
,
'n'
),
(
25
,
0.5
,
'n'
)],
[(
40
,
None
,
'n'
),
(
27
,
-
0.5
,
'n'
)],
[(
40
,
None
,
'n'
),
(
29
,
-
0.5
,
'n'
)],
[(
46
,
0.0
,
'n'
),
(
32
,
0.0
,
'n'
)],
[(
49
,
0.75
,
'n'
),
(
30
,
-
0.5
,
'n'
)],
[(
45
,
None
,
'n'
),
(
30
,
None
,
'n'
)],
[(
45
,
None
,
'n'
),
(
30
,
None
,
'n'
)],
[(
51
,
0.25
,
'n'
),
(
35
,
-
0.5
,
'n'
)],
[(
54
,
0.0
,
'n'
),
(
35
,
None
,
'n'
)],
[(
50
,
None
,
'n'
),
(
39
,
-
0.5
,
'n'
)],
[(
55
,
0.5
,
'n'
),
(
41
,
0.25
,
'n'
)],
[(
58
,
0.0
,
'n'
),
(
42
,
-
0.5
,
'n'
)],
[(
55
,
None
,
'n'
),
(
40
,
None
,
'n'
)],
[(
55
,
None
,
'n'
),
(
45
,
-
0.25
,
'n'
)],
[(
61
,
0.5
,
'n'
),
(
49
,
0.0
,
'n'
)],
[(
64
,
0.0
,
'n'
),
(
45
,
None
,
'n'
)],
[(
60
,
None
,
'n'
),
(
45
,
None
,
'n'
)],
[(
65
,
0.25
,
'n'
),
(
54
,
0.0
,
'n'
)],
[(
68
,
0.0
,
'n'
),
(
50
,
None
,
'n'
)],
[(
69
,
0.0
,
'n'
),
(
55
,
0.25
,
'n'
)],
[(
65
,
None
,
'n'
),
(
58
,
-
0.25
,
'n'
)],
[(
70
,
0.75
,
'n'
),
(
56
,
-
0.5
,
'n'
)],
[(
66
,
None
,
'n'
),
(
55
,
None
,
'n'
)],
[(
70
,
None
,
'n'
),
(
55
,
None
,
'n'
)],
[(
75
,
0.75
,
'n'
),
(
64
,
0.0
,
'n'
)],
[(
76
,
0.0
,
'n'
),
(
60
,
None
,
'n'
)],
[(
74
,
None
,
'n'
),
(
60
,
None
,
'n'
)],
[(
75
,
None
,
'n'
),
(
67
,
-
0.75
,
'n'
)],
None
,
[(
84
,
0.25
,
'n'
),
(
71
,
0.5
,
'n'
)],
[(
80
,
None
,
'n'
),
(
72
,
0.25
,
'n'
)],
[(
85
,
0.0
,
'n'
),
(
70
,
None
,
'n'
)],
[(
None
,
None
,
'n'
),
(
70
,
None
,
'n'
)],
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
[(
126
,
0.25
,
'e'
),
(
118
,
-
0.25
,
'e'
)],
[(
125
,
None
,
'e'
),
(
115
,
None
,
'e'
)],
[(
125
,
None
,
'e'
),
(
115
,
None
,
'e'
)],
[(
130
,
0.75
,
'e'
),
(
123
,
0.0
,
'e'
)],
[(
132
,
0.0
,
'e'
),
(
124
,
0.5
,
'e'
)],
[(
134
,
0.25
,
'e'
),
(
120
,
None
,
'e'
)],
[(
135
,
0.75
,
'e'
),
(
125
,
0.0
,
'e'
)],
[(
136
,
0.75
,
'e'
),
(
125
,
0.0
,
'e'
)],
[(
138
,
0.0
,
'e'
),
(
125
,
None
,
'e'
)],
[(
135
,
None
,
'e'
),
(
125
,
None
,
'e'
)],
[(
140
,
0.0
,
'e'
),
(
131
,
0.25
,
'e'
)],
[(
143
,
0.0
,
'e'
),
(
133
,
0.0
,
'e'
)],
[(
140
,
None
,
'e'
),
(
130
,
None
,
'e'
)],
[(
140
,
None
,
'e'
),
(
135
,
0.0
,
'e'
)],
[(
145
,
0.5
,
'e'
),
(
135
,
None
,
'e'
)],
[(
149
,
0.5
,
'e'
),
(
139
,
-
0.5
,
'e'
)],
[(
145
,
None
,
'e'
),
(
139
,
-
0.75
,
'e'
)],
[(
145
,
None
,
'e'
),
(
141
,
0.25
,
'e'
)],
[(
151
,
0.75
,
'e'
),
(
143
,
0.0
,
'e'
)],
[(
150
,
None
,
'e'
),
(
140
,
None
,
'e'
)],
[(
150
,
None
,
'e'
),
(
140
,
None
,
'e'
)],
[(
155
,
0.0
,
'e'
),
(
148
,
0.25
,
'e'
)],
[(
159
,
0.0
,
'e'
),
(
149
,
-
0.5
,
'e'
)],
[(
None
,
None
,
'e'
),
(
150
,
0.75
,
'e'
)],
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
[(
20
,
None
,
'n'
),
(
7
,
-
0.25
,
'n'
)],
[(
29
,
0.25
,
'n'
),
(
5
,
None
,
'n'
)],
[(
25
,
None
,
'n'
),
(
10
,
0.75
,
'n'
)],
[(
25
,
None
,
'n'
),
(
14
,
0.25
,
'n'
)],
[(
31
,
0.75
,
'n'
),
(
10
,
None
,
'n'
)],
[(
34
,
0.0
,
'n'
),
(
16
,
-
0.25
,
'n'
)],
[(
30
,
None
,
'n'
),
(
17
,
0.0
,
'n'
)],
[(
30
,
None
,
'n'
),
(
19
,
-
0.75
,
'n'
)]]
def
get_dqsi_vs_phase_prim_steps
(
variant
=
0
):
# while scanning, compare this delay with 1 less by primary(not fine) step,
# save None for fraction in unknown (previous -0.5, next +0.5)
if
variant
in
(
0
,):
return
1
else
:
return
0
def
get_dqsi_phase
():
dqsi_optimal_ps
=
[
-
662.3378911803243
,
-
945.8229473629233
]
dqsi_phase
=
[
[
114
,
115
,
116
,
119
,
120
,
120
,
124
,
124
,
125
,
127
,
129
,
130
,
130
,
133
,
134
,
135
,
135
,
139
,
139
,
140
,
141
,
144
,
145
,
145
,
149
,
149
,
150
,
152
,
154
,
155
,
0
,
2
,
4
,
5
,
5
,
8
,
9
,
10
,
10
,
14
,
14
,
15
,
18
,
19
,
20
,
20
,
24
,
24
,
25
,
27
,
29
,
30
,
30
,
33
,
34
,
35
,
35
,
39
,
39
,
40
,
41
,
44
,
45
,
45
,
49
,
49
,
50
,
52
,
54
,
55
,
55
,
58
,
59
,
60
,
60
,
64
,
64
,
65
,
66
,
69
,
70
,
70
,
74
,
74
,
75
,
77
,
79
,
80
,
80
,
83
,
84
,
85
,
85
,
89
,
89
,
90
,
91
,
94
,
95
,
95
,
99
,
99
,
100
,
102
,
104
,
105
,
105
,
108
,
109
,
110
,
110
,
114
],
[
104
,
105
,
105
,
109
,
109
,
110
,
113
,
114
,
115
,
115
,
119
,
119
,
120
,
124
,
124
,
125
,
127
,
129
,
130
,
130
,
134
,
134
,
135
,
138
,
139
,
140
,
141
,
144
,
145
,
145
,
149
,
149
,
150
,
153
,
154
,
155
,
156
,
159
,
159
,
None
,
None
,
None
,
None
,
0
,
3
,
4
,
5
,
7
,
9
,
10
,
10
,
14
,
14
,
15
,
18
,
19
,
20
,
21
,
24
,
25
,
25
,
29
,
29
,
30
,
32
,
34
,
35
,
35
,
39
,
39
,
40
,
43
,
44
,
45
,
47
,
49
,
50
,
50
,
54
,
54
,
55
,
58
,
59
,
60
,
61
,
64
,
65
,
65
,
69
,
69
,
70
,
73
,
74
,
75
,
75
,
79
,
79
,
80
,
84
,
84
,
85
,
87
,
89
,
90
,
90
,
94
,
94
,
95
,
98
,
99
,
100
,
101
]]
return
{
"dqsi_optimal_ps"
:
dqsi_optimal_ps
,
"dqsi_phase"
:
dqsi_phase
}
py393/x393_lma.py
View file @
faaa504f
...
...
@@ -177,7 +177,9 @@ class X393LMA(object):
y
=
np
.
zeros
((
n
,),
dtype
=
np
.
int
)
#[0]*n
w
=
np
.
zeros
((
n
,))
#[0]*n
f
=
np
.
full
((
n
,),
np
.
nan
)
# fractions
# f=np.full((n,),np.nan) # fractions
f
=
np
.
empty
((
n
,))
# fractions
f
[:]
=
np
.
nan
yf
=
np
.
zeros
((
n
,))
# y with added fractions
if
not
periods
is
None
:
p
=
np
.
zeros
((
n
),
dtype
=
np
.
int
)
#[0]*n
...
...
@@ -291,7 +293,48 @@ class X393LMA(object):
print
(
"?"
,
end
=
" "
)
print
()
def
showENLresults
(
self
,
DQvDQS
):
rslt_names
=
(
"early"
,
"nominal"
,
"late"
)
numBits
=
0
for
n
in
DQvDQS
:
try
:
for
d
in
DQvDQS
[
n
]:
try
:
numBits
=
len
(
d
)
# print ("d=",d)
break
except
:
pass
break
except
:
pass
if
not
numBits
:
raise
Exception
(
"showENLresults(): No no-None data provided"
)
# print ("numBits=%d"%(numBits))
enl_list
=
[]
for
k
in
rslt_names
:
if
DQvDQS
[
k
]:
enl_list
.
append
(
k
)
print
(
"DQS"
,
end
=
" "
)
for
enl
in
enl_list
:
for
b
in
range
(
numBits
):
print
(
"
%
s
%
d"
%
(
enl
[
0
]
.
upper
(),
b
),
end
=
" "
)
print
()
for
dly
in
range
(
len
(
DQvDQS
[
enl_list
[
0
]])):
print
(
"
%
d"
%
(
dly
),
end
=
" "
)
for
enl
in
enl_list
:
if
DQvDQS
[
enl
][
dly
]
is
None
:
print
(
"? "
*
numBits
,
end
=
""
)
else
:
for
b
in
range
(
numBits
):
if
DQvDQS
[
enl
][
dly
][
b
]
is
None
:
print
(
"?"
,
end
=
" "
)
else
:
print
(
"
%
d"
%
(
DQvDQS
[
enl
][
dly
][
b
]),
end
=
" "
)
print
()
def
normalizeParameters
(
self
,
parameters
,
isMask
=
False
):
...
...
@@ -453,7 +496,7 @@ class X393LMA(object):
index
+=
1
return
parameters
def
estimate_from_histograms
(
self
,
def
dqi_dqsi_
estimate_from_histograms
(
self
,
lane
,
# byte lane
bin_size
,
clk_period
,
...
...
@@ -773,16 +816,16 @@ class X393LMA(object):
print
()
return
data_periods_map
def
lma_fit
(
self
,
lane
,
# byte lane
bin_size
,
clk_period
,
dly_step_ds
,
primary_set
,
data_set
,
compare_prim_steps
,
scale_w
,
quiet
=
1
):
def
lma_fit
_dqi_dqsi
(
self
,
lane
,
# byte lane
bin_size
,
clk_period
,
dly_step_ds
,
primary_set
,
data_set
,
compare_prim_steps
,
scale_w
,
quiet
=
1
):
"""
Initialize parameters and y-vector
using datasheet delay/step (without fine step delay)
...
...
@@ -793,8 +836,7 @@ class X393LMA(object):
After initial parametersn are created - run LMA to find optimal ones,
then return up to 3 varints (early, nominal, late) providing the best
DQ input delay for each DQS one
@lane byte lane to process
@lane byte lane to process (or non-number - process all byte lanes of the device)
@bin_size bin size for the histograms (should be 5/10/20/40)
@clk_period SDCLK period in ps
@dly_step_ds IDELAY step (from the datasheet)
...
...
@@ -807,11 +849,58 @@ class X393LMA(object):
@return 3-element dictionary of ('early','nominal','late'), each being None or a 160-element list,
each element being either None, or a list of 3 best DQ delay values for the DQS delay (some mey be None too)
"""
if
not
isinstance
(
lane
,(
int
,
long
)):
# ignore content, process both lanes
lane_rslt
=
[]
numLanes
=
2
parametersKey
=
'parameters'
for
lane
in
range
(
numLanes
):
lane_rslt
.
append
(
self
.
lma_fit
(
lane
,
# byte lane
bin_size
,
clk_period
,
dly_step_ds
,
primary_set
,
data_set
,
compare_prim_steps
,
scale_w
,
quiet
))
rslt
=
{}
for
k
in
lane_rslt
[
0
]
.
keys
():
if
k
!=
parametersKey
:
for
r
in
lane_rslt
:
try
:
l
=
len
(
r
[
k
])
break
except
:
pass
else
:
rslt
[
k
]
=
None
continue
rslt
[
k
]
=
[]
for
dly
in
range
(
l
):
w
=
[]
for
lane
in
range
(
numLanes
):
if
(
lane_rslt
[
lane
][
k
]
is
None
)
or
(
lane_rslt
[
lane
][
k
][
dly
]
is
None
):
w
+=
[
None
]
*
8
else
:
w
+=
lane_rslt
[
lane
][
k
][
dly
]
for
b
in
w
:
if
not
b
is
None
:
rslt
[
k
]
.
append
(
w
)
break
else
:
rslt
[
k
]
.
append
(
None
)
rslt
[
parametersKey
]
=
[]
for
lane
in
range
(
numLanes
):
rslt
[
parametersKey
]
.
append
(
lane_rslt
[
lane
][
parametersKey
])
return
rslt
# byte lanes combined
if
quiet
<
3
:
print
(
"init_parameters(): scale_w=
%
f"
%
(
scale_w
))
self
.
clk_period
=
clk_period
hist_estimated
=
self
.
estimate_from_histograms
(
lane
,
# byte lane
hist_estimated
=
self
.
dqi_dqsi_
estimate_from_histograms
(
lane
,
# byte lane
bin_size
,
clk_period
,
dly_step_ds
,
...
...
@@ -997,6 +1086,7 @@ class X393LMA(object):
rslt_names
=
(
"early"
,
"nominal"
,
"late"
)
for
i
,
d
in
enumerate
(
DQvDQS
):
rslt
[
rslt_names
[
i
]]
=
d
rslt
[
'parameters'
]
=
parameters
return
rslt
# return DQvDQS
# Returns 3-element dictionary of ('early','nominal','late'), each being None or a 160-element list,
...
...
@@ -1386,22 +1476,14 @@ class X393LMA(object):
w_vector
=
ywp
[
'w'
]
except
:
w_vector
=
np
.
full
((
len
(
fxj
[
'fx'
]),),
1.0
)
# print("w_vector=",w_vector)
# print("fxj['jacob']=",fxj['jacob'])
# JT=np.transpose(fxj['jacob'])
# print("JT=",JT)
wJ
=
fxj
[
'jacob'
]
*
w_vector
# JT=np.transpose(wJ) # fxj['jacob'])
JT
=
np
.
transpose
(
fxj
[
'jacob'
])
# print("wJ=",wJ)
#np.fill_diagonal(z3,np.diag(z3)*0.1)
jByJT
=
np
.
dot
(
wJ
,
JT
)
# print("jByJT=",jByJT)
for
i
,
_
in
enumerate
(
jByJT
):
jByJT
[
i
,
i
]
+=
lmbda
*
jByJT
[
i
,
i
]
jByDiff
=
-
np
.
dot
(
wJ
,
fxj
[
'fx'
])
delta
=
np
.
linalg
.
solve
(
jByJT
,
jByDiff
)
# print("*****delta=",delta)
return
delta
"""
...
...
@@ -1415,8 +1497,218 @@ class X393LMA(object):
s=if-ir+of-or
d=ir-if+of-or
"""
def
lma_fit_dqsi_phase
(
self
,
lane
,
# byte lane
bin_size_ps
,
clk_period
,
# phase_step, # ~22ps
# dly_step_ds,
# primary_set,
dqsi_dqi_parameters
,
data_set
,
compare_prim_steps
,
scale_w
,
numPhaseSteps
,
quiet
=
1
):
def
show_input_data
(
filtered
):
print
((
'unfiltered'
,
'filtered'
)[
filtered
])
for
phase
,
d
in
enumerate
(
data_set
):
print
(
"
%
d"
%
(
phase
),
end
=
" "
)
if
not
d
is
None
:
for
lane
,
dl
in
enumerate
(
d
):
if
(
not
dl
is
None
)
and
(
not
dl
[
0
]
is
None
)
and
((
not
filtered
)
or
(
not
dl
[
1
]
is
None
)):
dly
=
dl
[
0
]
if
dl
[
1
]
is
None
:
dly
+=
halfStep
# print ("%f %f"%(dly, dly-phase*phase_step/dbg_tSDQS[lane]), end=" ")
# print ("%f %f"%(dly*dbg_tSDQS[lane]/phase_step, dly*dbg_tSDQS[lane]/phase_step-phase), end=" ")
print
(
"
%
f
%
f"
%
(
dly
*
dbg_tSDQS
[
lane
],
dly
*
dbg_tSDQS
[
lane
]
-
phase
*
phase_step
),
end
=
" "
)
else
:
print
(
"? ?"
,
end
=
" "
)
print
()
def
get_shift_by_hist
(
span
=
5
):
for
phase
,
d
in
enumerate
(
data_set
):
if
not
d
is
None
:
dl
=
d
[
lane
]
if
(
not
dl
is
None
)
and
(
not
dl
[
0
]
is
None
):
dly
=
dl
[
0
]
if
dl
[
1
]
is
None
:
dly
+=
halfStep
diff_ps
=
dly
*
tSDQS
-
phase
*
phase_step
binArr
[
int
((
diff_ps
-
minVal
)
/
bin_size_ps
)]
+=
1
if
quiet
<
3
:
for
i
,
h
in
enumerate
(
binArr
):
print
(
"
%
d
%
d"
%
(
i
,
h
))
indx
=
0
for
i
,
h
in
enumerate
(
binArr
):
if
h
>
binArr
[
indx
]:
indx
=
i
low
=
max
(
0
,
indx
-
span
)
high
=
min
(
len
(
binArr
)
-
1
,
indx
+
span
)
S0
=
0
SX
=
0.0
for
i
in
range
(
low
,
high
+
1
):
S0
+=
binArr
[
i
]
SX
+=
binArr
[
i
]
*
i
if
S0
>
0
:
SX
/=
S0
print
(
"SX="
,
SX
)
return
minVal
+
bin_size_ps
*
(
SX
+
0.5
)
# ps
if
not
isinstance
(
lane
,(
int
,
long
)):
# ignore content, process both lanes
rslt_names
=
(
"dqsi_optimal_ps"
,
"dqsi_phase"
)
rslt
=
{}
for
name
in
rslt_names
:
rslt
[
name
]
=
[]
for
lane
in
range
(
2
):
rslt_lane
=
self
.
lma_fit_dqsi_phase
(
lane
,
# byte lane
bin_size_ps
,
clk_period
,
dqsi_dqi_parameters
,
data_set
,
compare_prim_steps
,
scale_w
,
numPhaseSteps
,
quiet
=
1
)
for
name
in
rslt_names
:
rslt
[
name
]
.
append
(
rslt_lane
[
name
])
if
quiet
<
3
:
print
(
'dqsi_optimal_ps=
%
s'
%
(
str
(
rslt
[
'dqsi_optimal_ps'
])))
print
(
'dqsi_phase=['
)
for
lane
in
rslt
[
'dqsi_phase'
]:
print
(
" ["
,
end
=
" "
)
for
i
,
d
in
enumerate
(
lane
):
last
=
i
==
(
len
(
lane
)
-
1
)
print
(
"
%
s"
%
(
str
(
d
)),
end
=
" "
)
if
not
last
:
print
(
","
,
end
=
" "
)
if
((
i
+
1
)
%
16
)
==
0
:
print
(
"
\n
"
,
end
=
""
)
else
:
print
(
'],'
)
print
(
']'
)
# print(rslt)
return
rslt
phase_step
=
clk_period
/
numPhaseSteps
tSDQS
=
dqsi_dqi_parameters
[
lane
][
'tSDQS'
]
# ~16.081739769147354
dbg_tSDQS
=
(
dqsi_dqi_parameters
[
0
][
'tSDQS'
],
dqsi_dqi_parameters
[
1
][
'tSDQS'
])
halfStep
=
0.5
*
(
1
,
compare_prim_steps
)[
compare_prim_steps
]
#phase_step/tSDQS
print
(
phase_step
,
dbg_tSDQS
)
if
quiet
<
2
:
for
filtered
in
range
(
2
):
show_input_data
(
filtered
)
# all preliminary teset above
maxVal
=
DLY_STEPS
*
tSDQS
minVal
=
-
clk_period
num_bins
=
int
((
maxVal
-
minVal
)
/
bin_size_ps
)
+
1
binArr
=
[
0
]
*
num_bins
print
(
"minVal="
,
minVal
)
print
(
"maxVal="
,
maxVal
)
print
(
"num_bins="
,
num_bins
)
#find main max
dly_max0
=
get_shift_by_hist
()
# delay in ps, corresponding to largest maximum
print
(
"max0=
%
f, (
%
f)"
%
(
dly_max0
,
dly_max0
/
tSDQS
))
periods
=
[
None
]
*
len
(
data_set
)
for
phase
,
d
in
enumerate
(
data_set
):
if
not
d
is
None
:
dl
=
d
[
lane
]
if
(
not
dl
is
None
)
and
(
not
dl
[
0
]
is
None
):
dly
=
dl
[
0
]
if
dl
[
1
]
is
None
:
dly
+=
halfStep
periods
[
phase
]
=
int
(
round
((
dly
*
tSDQS
-
phase
*
phase_step
)
/
clk_period
))
w
=
[
0.0
]
*
len
(
data_set
)
if
quiet
<
2
:
for
i
,
p
in
enumerate
(
periods
):
print
(
"
%
d
%
s"
%
(
i
,
str
(
p
)))
tFDQS
=
dqsi_dqi_parameters
[
lane
][
'tFDQS'
]
# [-21.824409224001187, -10.830180678770162, 1.5698858542328959, 11.267851084349177]
tFDQS
.
append
(
-
tFDQS
[
0
]
-
tFDQS
[
1
]
-
tFDQS
[
2
]
-
tFDQS
[
3
])
SY
=
0.0
S0
=
0.0
for
phase
,
d
in
enumerate
(
data_set
):
if
not
d
is
None
:
dl
=
d
[
lane
]
if
(
not
dl
is
None
)
and
(
not
dl
[
0
]
is
None
):
dly
=
dl
[
0
]
w
[
i
]
=
1.0
if
dl
[
1
]
is
None
:
dly
+=
halfStep
w
[
i
]
=
scale_w
d
=
dly
*
tSDQS
-
periods
[
phase
]
*
clk_period
-
tFDQS
[
dl
[
0
]
%
FINE_STEPS
]
y
=
d
-
phase
*
phase_step
S0
+=
w
[
i
]
SY
+=
w
[
i
]
*
y
if
S0
>
0.0
:
SY
/=
S0
print
(
"shift="
,
SY
,
" ps"
)
if
quiet
<
2
:
for
phase
,
d
in
enumerate
(
data_set
):
print
(
"
%
d"
%
(
phase
),
end
=
" "
)
if
not
d
is
None
:
dl
=
d
[
lane
]
if
(
not
dl
is
None
)
and
(
not
dl
[
0
]
is
None
):
dly
=
dl
[
0
]
if
dl
[
1
]
is
None
:
dly
+=
halfStep
d
=
dly
*
tSDQS
-
periods
[
phase
]
*
clk_period
-
tFDQS
[
dl
[
0
]
%
FINE_STEPS
]
print
(
"
%
f
%
f"
%
(
d
,
w
[
i
]),
end
=
" "
)
if
not
dl
[
1
]
is
None
:
print
(
d
,
end
=
" "
)
else
:
print
(
"?"
,
end
=
" "
)
else
:
print
(
"? ?"
,
end
=
" "
)
print
(
"
%
f"
%
(
SY
+
phase
*
phase_step
),
end
=
" "
)
print
()
# Now shift SY by clk_period/2.0, for each phase find the closest DQSI match (None if does not exist)
dqsi_range
=
tSDQS
*
DLY_STEPS
# full range of the DQSI delay for this lane
# dqsi_middle_in_ps = SY-clk_period*round(SY/clk_period)-0.5
# dqsi_middle_in_ps = (SY-clk_period/2)-clk_period*round((SY-clk_period/2)/clk_period)
# dqsi_middle_in_ps = (SY-clk_period/2)-clk_period*round(SY/clk_period -0.5)
dqsi_middle_in_ps
=
SY
-
clk_period
*
(
round
(
SY
/
clk_period
-
0.5
)
+
0.5
)
dqsi_phase
=
[
None
]
*
numPhaseSteps
for
phase
in
range
(
numPhaseSteps
):
dly_ps
=
phase_step
*
phase
+
dqsi_middle_in_ps
dly_ps
-=
clk_period
*
round
(
dly_ps
/
clk_period
-
0.5
)
# positive, <clk_period
#Using lowest delay branch if multiple are possible
if
dly_ps
>
dqsi_range
:
continue
# no valid dqs_idelay for this phase
idly
=
int
(
round
(
dly_ps
/
tSDQS
))
low
=
max
(
0
,
idly
-
FINE_STEPS
)
high
=
min
(
DLY_STEPS
-
1
,
idly
+
FINE_STEPS
)
idly
=
low
for
i
in
range
(
low
,
high
+
1
):
if
abs
(
i
*
tSDQS
-
tFDQS
[
i
%
FINE_STEPS
]
-
dly_ps
)
<
abs
(
idly
*
tSDQS
-
tFDQS
[
idly
%
FINE_STEPS
]
-
dly_ps
):
idly
=
i
dqsi_phase
[
phase
]
=
idly
if
quiet
<
3
:
for
phase
,
d
in
enumerate
(
data_set
):
print
(
"
%
d"
%
(
phase
),
end
=
" "
)
if
(
not
d
is
None
)
and
(
not
d
[
lane
]
is
None
)
and
(
not
d
[
lane
][
0
]
is
None
):
dly
=
d
[
lane
][
0
]
if
d
[
lane
][
1
]
is
None
:
dly
+=
halfStep
print
(
"
%
f"
%
(
dly
),
end
=
" "
)
else
:
print
(
"?"
,
end
=
" "
)
if
not
dqsi_phase
[
phase
]
is
None
:
print
(
"
%
f"
%
(
dqsi_phase
[
phase
]),
end
=
" "
)
else
:
print
(
"?"
,
end
=
" "
)
print
()
return
{
"dqsi_optimal_ps"
:
dqsi_middle_in_ps
,
"dqsi_phase"
:
dqsi_phase
}
\ No newline at end of file
py393/x393_mcntrl_adjust.py
View file @
faaa504f
...
...
@@ -51,6 +51,7 @@ import x393_lma
#import vrlg
NUM_FINE_STEPS
=
5
NUM_DLY_STEPS
=
NUM_FINE_STEPS
*
32
# =160
class
X393McntrlAdjust
(
object
):
DRY_MODE
=
True
# True
...
...
@@ -208,7 +209,28 @@ class X393McntrlAdjust(object):
mem16
.
append
(((
w32
[
i
]
>>
24
)
&
0xff
)
|
(((
w32
[
i
+
1
]
>>
24
)
&
0xff
)
<<
8
))
return
mem16
def
set_phase_with_refresh
(
self
,
# check result for not None
phase
,
quiet
=
2
):
"""
Set specified phase and matching cmda_odelay while temporarily turning off refresh
@phase phase to set, signed short
@quiet reduce output
@return cmda_odelay linear value or None if there is no valid cmda output delay for this phase
"""
if
not
"cmda_bspe"
in
self
.
adjustment_state
:
raise
Exception
(
"No cmda_odelay data is available. 'adjust_cmda_odelay 0 1 0.1 3' command should run first."
)
dly_steps
=
self
.
x393_mcntrl_timing
.
get_dly_steps
()
numPhaseSteps
=
int
(
dly_steps
[
'SDCLK_PERIOD'
]
/
dly_steps
[
'PHASE_STEP'
]
+
0.5
)
cmda_odly_data
=
self
.
adjustment_state
[
'cmda_bspe'
][
phase
%
numPhaseSteps
]
if
(
not
cmda_odly_data
):
# phase is invalid for CMDA
return
None
cmda_odly_lin
=
cmda_odly_data
[
'ldly'
]
self
.
x393_axi_tasks
.
enable_refresh
(
0
)
self
.
x393_mcntrl_timing
.
axi_set_phase
(
phase
,
quiet
=
quiet
)
self
.
x393_mcntrl_timing
.
axi_set_cmda_odelay
(
self
.
combine_delay
(
cmda_odly_lin
),
quiet
=
quiet
)
self
.
x393_axi_tasks
.
enable_refresh
(
1
)
return
cmda_odly_lin
def
scan_dqs
(
self
,
low_delay
,
...
...
@@ -1026,7 +1048,7 @@ class X393McntrlAdjust(object):
if
start_phase
>=
128
:
start_phase
-=
256
# -128..+127
recover_cmda_dly_step
=
0x20
# subtract/add from cmda_odelay (hardware!!!) and retry (same as 20 decimal)
max_lin_dly
=
159
max_lin_dly
=
NUM_DLY_STEPS
-
1
wlev_address_bit
=
7
wlev_max_bad
=
0.01
# <= OK, > bad
def
phase_step
(
phase
,
cmda_dly
):
...
...
@@ -1318,6 +1340,11 @@ class X393McntrlAdjust(object):
print
()
#TODO: Add 180 shift to get center, not marginal cmda_odelay
self
.
adjustment_state
.
update
(
rdict
)
if
(
quiet
<
3
):
print
(
"rdict={"
)
for
k
,
v
in
rdict
.
items
():
print
(
"'
%
s':
%
s,"
%
(
k
,
str
(
v
)))
print
(
"}"
)
return
rdict
def
adjust_write_levelling
(
self
,
...
...
@@ -1331,12 +1358,14 @@ class X393McntrlAdjust(object):
Find DQS output delay for each phase value
Depends on adjust_cmda_odelay results
"""
if
not
self
.
adjustment_state
[
'cmda_bspe'
]:
try
:
self
.
adjustment_state
[
'cmda_bspe'
]
except
:
raise
Exception
(
"Command/Address delay calibration data is not found - please run 'adjust_cmda_odelay' command first"
)
start_phase
&=
0xff
if
start_phase
>=
128
:
start_phase
-=
256
# -128..+127
max_lin_dly
=
159
max_lin_dly
=
NUM_DLY_STEPS
-
1
wlev_max_bad
=
0.01
# <= OK, > bad
numPhaseSteps
=
len
(
self
.
adjustment_state
[
'cmda_bspe'
])
if
quiet
<
2
:
...
...
@@ -1649,12 +1678,17 @@ class X393McntrlAdjust(object):
print
(
"
%
d
%
d
%
f"
%
(
bspe
[
'ldly'
],
10
*
bspe
[
'period'
],
10
*
bspe
[
'err'
]),
end
=
" "
)
else
:
print
(
"X X X"
,
end
=
" "
)
print
()
print
()
self
.
adjustment_state
.
update
(
rdict
)
# print (self.adjustment_state)
if
(
quiet
<
3
):
print
(
"rdict={"
)
for
k
,
v
in
rdict
.
items
():
print
(
"'
%
s':
%
s,"
%
(
k
,
str
(
v
)))
print
(
"}"
)
return
rdict
def
adjust
_pattern
(
self
,
def
measure
_pattern
(
self
,
compare_prim_steps
=
True
,
# while scanning, compare this delay with 1 less by primary(not fine) step,
# save None for fraction in unknown (previous -0.5, next +0.5)
limit_step
=
0.125
,
# initial delay step as a fraction of the period
...
...
@@ -1668,11 +1702,11 @@ class X393McntrlAdjust(object):
(late 0->1, early 1->0) for each of the DQ and DQS
"""
nrep
=
8
max_lin_dly
=
159
max_lin_dly
=
NUM_DLY_STEPS
-
1
#
159
timing
=
self
.
x393_mcntrl_timing
.
get_dly_steps
()
#steps={'DLY_FINE_STEP': 0.01, 'DLY_STEP': 0.078125, 'PHASE_STEP': 0.022321428571428572, 'SDCLK_PERIOD': 2.5}
dly_step
=
int
(
5
*
limit_step
*
timing
[
'SDCLK_PERIOD'
]
/
timing
[
'DLY_STEP'
]
+
0.5
)
step180
=
int
(
5
*
0.5
*
timing
[
'SDCLK_PERIOD'
]
/
timing
[
'DLY_STEP'
]
+
0.5
)
dly_step
=
int
(
NUM_FINE_STEPS
*
limit_step
*
timing
[
'SDCLK_PERIOD'
]
/
timing
[
'DLY_STEP'
]
+
0.5
)
step180
=
int
(
NUM_FINE_STEPS
*
0.5
*
timing
[
'SDCLK_PERIOD'
]
/
timing
[
'DLY_STEP'
]
+
0.5
)
if
quiet
<
2
:
print
(
"timing)=
%
s, dly_step=
%
d step180=
%
d"
%
(
str
(
timing
),
dly_step
,
step180
))
self
.
x393_pio_sequences
.
set_read_pattern
(
nrep
+
3
)
# set sequence once
...
...
@@ -1879,16 +1913,6 @@ class X393McntrlAdjust(object):
diffs_prev_this
=
(
patt_prev
[
b
]
-
0.5
,
patt
[
b
]
-
0.5
)
else
:
diffs_prev_this
=
(
0.5
-
patt_prev
[
b
],
0.5
-
patt
[
b
])
"""
if abs(patt_prev[b]-0.5) < abs(patt[b]-0.5): # store previos sample
best_dly[inPhase][b]=dly_prev # dly-1
best_diff[inPhase][b]=patt_prev[b]-0.5
else:
best_dly[inPhase][b]=dly
best_diff[inPhase][b]=patt[b]-0.5
if not positiveJump:
best_diff[inPhase][b] *= -1 # invert sign, so sign always means <0 - delay too low, >0 - too high
"""
if
abs
(
diffs_prev_this
[
0
])
<=
abs
(
diffs_prev_this
[
1
]):
# store previos sample
if
(
best_diff
[
inPhase
][
b
]
is
None
)
or
(
abs
(
diffs_prev_this
[
0
])
<
abs
(
best_diff
[
inPhase
][
b
])):
best_dly
[
inPhase
][
b
]
=
dly_prev
# dly-1
...
...
@@ -2024,40 +2048,350 @@ class X393McntrlAdjust(object):
print
(
"meas_data=["
)
for
d
in
meas_data
:
print
(
"
%
s,"
%
(
str
(
d
)))
print
(
"]"
)
print
(
"]"
)
rdict
=
{
"patt_prim_steps"
:
compare_prim_steps
,
"patt_meas_data"
:
meas_data
}
# TODO: May delete after LMA fitting
self
.
adjustment_state
.
update
(
rdict
)
def
measure_dqs_idly_phase
(
self
,
compare_prim_steps
=
True
,
# while scanning, compare this delay with 1 less by primary(not fine) step,
# save None for fraction in unknown (previous -0.5, next +0.5)
frac_step
=
0.125
,
sel
=
1
,
quiet
=
1
):
"""
Scan phase and find DQS input delay value to find when
the result changes (it is caused by crossing clock boundarty from extrenal memory device derived
to system-synchronous one
cmda_odelay should be already calibrated, refresh will be turned on.
Uses random/previously written pattern in one memory block (should have some varying data
"""
"""
TODO: write block of data: 0xffff, 0xffff, 0x0000, 0x0000, 0xffff, 0xffff, ...(dqs_odelay set by wlev)
All bits will alternate, even if the DQ_ODELAY vs DQS_ODELAY will be wrong
"""
try
:
dqi_dqsi
=
self
.
adjustment_state
[
'dqi_dqsi'
]
except
:
print
(
"No DQ IDELAY vs. DQS IDELAY data available, exiting"
)
return
# Mark DQS idelay values that have all DQ delays valid
dqsi_valid
=
{}
#[None]*NUM_DLY_STEPS
for
k
,
v
in
dqi_dqsi
.
items
():
if
v
:
dqsi_valid
[
k
]
=
[
False
]
*
NUM_DLY_STEPS
for
dly
in
range
(
NUM_DLY_STEPS
):
if
v
[
dly
]:
for
d
in
v
[
dly
]:
if
d
is
None
:
break
else
:
# All values are not None
dqsi_valid
[
k
][
dly
]
=
True
if
not
dqsi_valid
:
print
(
"No Valid DQ IDELAY vs. DQS IDELAY data is available, exiting"
)
return
if
quiet
<
1
:
print
(
'dqi_dqsi=
%
s'
%
(
str
(
dqi_dqsi
)))
print
(
"
\n\n
"
)
if
quiet
<
2
:
print
(
'dqsi_valid=
%
s'
%
(
str
(
dqsi_valid
)))
dqsi_lohi
=
{}
for
k
,
vdly
in
dqsi_valid
.
items
():
if
quiet
<
2
:
print
(
"k='
%
s', vdly=
%
s"
%
(
k
,
str
(
vdly
)))
for
i
,
v
in
enumerate
(
vdly
):
if
v
:
low
=
i
break
else
:
print
(
"Could not find valid data in dqsi_valid[
%
s]=
%
s"
%
(
k
,
str
(
vdly
)))
continue
for
i
in
range
(
low
+
1
,
NUM_DLY_STEPS
):
if
not
vdly
[
i
]:
high
=
i
break
else
:
high
=
NUM_DLY_STEPS
-
1
dqsi_lohi
[
k
]
=
(
low
,
high
)
if
quiet
<
2
:
print
(
'dqsi_valid=
%
s'
%
(
str
(
dqsi_valid
)))
if
quiet
<
3
:
print
(
'dqsi_lohi=
%
s'
%
(
str
(
dqsi_lohi
)))
brc
=
(
5
,
# 3'h5, # bank
0x1234
,
# 15'h1234, # row address
0x100
)
# 10'h100 # column address
nrep
=
8
# number of 8-bursts to compare (actual will have 3 more, first/last will be discarded
timing
=
self
.
x393_mcntrl_timing
.
get_dly_steps
()
#steps={'DLY_FINE_STEP': 0.01, 'DLY_STEP': 0.078125, 'PHASE_STEP': 0.022321428571428572, 'SDCLK_PERIOD': 2.5}
dly_step
=
int
(
NUM_FINE_STEPS
*
frac_step
*
timing
[
'SDCLK_PERIOD'
]
/
timing
[
'DLY_STEP'
]
+
0.5
)
numPhaseSteps
=
int
(
timing
[
'SDCLK_PERIOD'
]
/
timing
[
'PHASE_STEP'
]
+
0.5
)
step180
=
int
(
NUM_FINE_STEPS
*
0.5
*
timing
[
'SDCLK_PERIOD'
]
/
timing
[
'DLY_STEP'
]
+
0.5
)
if
quiet
<
2
:
print
(
"timing)=
%
s, dly_step=
%
d step180=
%
d"
%
(
str
(
timing
),
dly_step
,
step180
))
self
.
x393_pio_sequences
.
set_read_block
(
*
(
brc
+
(
nrep
+
3
,
sel
)))
# set sequence once
# def read_blk(): #return array of 16-bit words to compare for bit diffs
# pass
def
dqsi_phase_step
(
phase
):
dqsi_cache
=
[
None
]
*
NUM_DLY_STEPS
# cache for holding already measured delays. None - not measured, 0 - no data, [[]..[]]
def
measure_dqsi
(
dqs_idly
,
branch
,
force_meas
=
False
):
if
not
dqsi_valid
[
branch
]:
return
None
if
(
dqs_idly
>
len
(
dqsi_cache
))
or
(
dqs_idly
<
0
):
print
(
"dqs_idly=
%
d, dqsi_cache=
%
s"
%
(
dqs_idly
,
str
(
dqsi_cache
)))
try
:
dqsi_cache
[
dqs_idly
]
except
:
print
(
"dqs_idly=
%
d, dqsi_cache=
%
s"
%
(
dqs_idly
,
str
(
dqsi_cache
)))
if
(
dqsi_cache
[
dqs_idly
]
is
None
)
or
force_meas
:
self
.
x393_mcntrl_timing
.
axi_set_dqs_idelay
(
self
.
combine_delay
(
dqs_idly
),
quiet
=
quiet
)
self
.
x393_mcntrl_timing
.
axi_set_dq_idelay
(
self
.
combine_delay
(
dqi_dqsi
[
branch
][
dqs_idly
]),
quiet
=
quiet
)
buf
=
self
.
x393_pio_sequences
.
read_block
(
4
*
(
nrep
+
1
)
+
2
,
(
0
,
1
)[
quiet
<
1
],
#show_rslt,
1
)
# wait_complete=1)
buf
=
buf
[
4
:(
nrep
*
4
)
+
4
]
# discard first 4*32-bit words and the "tail" after nrep*4 words32
patt
=
self
.
convert_w32_to_mem16
(
buf
)
# will be nrep*8 items
dqsi_cache
[
dqs_idly
]
=
patt
if
quiet
<
1
:
print
(
'measure_phase(
%
d,
%
s) - new measurement'
%
(
phase
,
str
(
force_meas
)))
else
:
patt
=
dqsi_cache
[
dqs_idly
]
if
quiet
<
1
:
print
(
'measure_patt(
%
d,
%
s) - using cache'
%
(
phase
,
str
(
force_meas
)))
return
patt
def
get_bit_diffs
(
dqs_idly0
,
dqs_idly1
,
branch
):
patt0
=
measure_dqsi
(
dqs_idly0
,
branch
)
patt1
=
measure_dqsi
(
dqs_idly1
,
branch
)
if
(
patt0
is
None
)
or
(
patt1
is
None
):
raise
Exception
(
"Tried to compare invalid(s): dqs_idly0=
%
d, dqs_idly1=
%
d, branch=
%
s"
%
(
dqs_idly0
,
dqs_idly1
,
branch
))
rslt
=
[
0
]
*
16
for
i
in
range
(
nrep
*
8
):
# with 8 nursts - 64 x16-bit words
diffs
=
patt0
[
i
]
^
patt1
[
i
]
for
b
in
range
(
len
(
rslt
)):
rslt
[
b
]
+=
(
diffs
>>
b
)
&
1
return
rslt
def
get_lane_diffs
(
dqs_idly0
,
dqs_idly1
,
branch
):
diffs
=
get_bit_diffs
(
dqs_idly0
,
dqs_idly1
,
branch
)
# lane_diffs=[0]*(len(diffs)//8)
lane_diffs
=
[]
for
lane
in
range
(
len
(
diffs
)
//
8
):
num_diffs
=
0
for
b
in
range
(
8
):
num_diffs
+=
(
0
,
1
)[
diffs
[
8
*
lane
+
b
]
!=
0
]
lane_diffs
.
append
(
num_diffs
)
if
quiet
<
3
:
print
(
"
%
d ?
%
d :
%
s"
%
(
dqs_idly0
,
dqs_idly1
,
lane_diffs
))
return
lane_diffs
def
get_lane_adiffs
(
dqs_idly0
,
dqs_idly1
,
branch
):
# Assuming all 8 bits differ in the read data - check it in a single block? Write pattern?
diffs
=
get_lane_diffs
(
dqs_idly0
,
dqs_idly1
,
branch
)
return
((
diffs
[
0
]
-
4
)
/
4.0
,(
diffs
[
1
]
-
4
)
/
4.0
)
# Set phase
phase_ok
=
self
.
set_phase_with_refresh
(
# check result for not None
phase
,
quiet
)
if
not
phase_ok
:
return
None
# no vlaid CMDA ODELAY exists for this phase
# try branches (will exit on first match)
for
branch
in
dqsi_lohi
.
keys
():
low
=
dqsi_lohi
[
branch
][
0
]
high
=
dqsi_lohi
[
branch
][
1
]
# start with low dqs idelay and increase it by 1 primary step until getting 2 results with no bit differences
# (using both byte lanes now)
for
idly1
in
range
(
low
+
NUM_FINE_STEPS
,
high
,
NUM_FINE_STEPS
):
diffs
=
get_lane_diffs
(
idly1
-
NUM_FINE_STEPS
,
idly1
,
branch
)
if
diffs
==
[
0
,
0
]:
# no bit diffs in both byte lanes
low
=
idly1
break
else
:
#failed to find two delays to get the same read results (no bit differences in both lanes)
continue
# got both byte lanes with no difference, now try to find dqs_idelay delay where both bytes differ
for
idly
in
range
(
low
,
high
,
dly_step
):
idly1
=
min
(
idly
+
dly_step
,
high
)
diffs
=
get_lane_diffs
(
low
,
idly1
,
branch
)
if
(
diffs
[
0
]
!=
0
)
and
(
diffs
[
1
]
!=
0
):
high
=
idly1
break
elif
(
diffs
[
0
]
==
0
)
and
(
diffs
[
1
]
==
0
):
low
=
idly1
# move low higher
else
:
#failed to find another delay to get different read results (both myte lanes have bit differences
continue
if
quiet
<
3
:
print
(
"0: low=
%
d, high=
%
d"
%
(
low
,
high
))
low_safe
=
low
# safe low
# now find marginal dqs idelay for each byte lane by dividing (low,high) interval
#reduce low,high range for combined lanes
dly
=
high
while
low
<
dly
:
# first adjust low
dly_next
=
(
low
+
dly
)
//
2
diffs
=
get_lane_diffs
(
low
,
dly_next
,
branch
)
if
(
diffs
[
0
]
!=
0
)
and
(
diffs
[
1
]
!=
0
):
dly
=
dly_next
high
=
dly
elif
(
diffs
[
0
]
==
0
)
and
(
diffs
[
1
]
==
0
):
if
low
==
dly_next
:
break
low
=
dly_next
# move low higher
else
:
# one byte matches, other - not (uncertain)
dly
=
dly_next
dly
=
low
while
dly
<
high
:
# now adjust high
dly_next
=
(
high
+
dly
)
//
2
diffs
=
get_lane_diffs
(
low_safe
,
dly_next
,
branch
)
if
(
diffs
[
0
]
!=
0
)
and
(
diffs
[
1
]
!=
0
):
high
=
dly_next
else
:
if
dly
==
dly_next
:
break
dly
=
dly_next
# move low higher
#low, high are now closer, now scan and store (delay,num_bits) for each lane
#May be check maximal number of bits that mismatch for each lane? Now assuming that it can be up to all 8
# low -= NUM_FINE_STEPS
# low = max(dqsi_lohi[branch][0], low - NUM_FINE_STEPS ) # try to move lower by the fine steps interval, if possible
# high = min(dqsi_lohi[branch][1], high+ NUM_FINE_STEPS ) # try to move higher by the fine steps interval, if possible
if
quiet
<
3
:
print
(
"1: low=
%
d(
%
d), high=
%
d"
%
(
low
,
low_safe
,
high
))
high
=
min
(
dqsi_lohi
[
branch
][
1
],
high
+
NUM_FINE_STEPS
)
# try to move higher by the fine steps interval, if possible
if
quiet
<
3
:
print
(
"2: low=
%
d(
%
d), high=
%
d"
%
(
low
,
low_safe
,
high
))
rslt
=
[]
bestDly
=
[
None
]
*
2
# [low_safe]*2 # otherwise may fail - check it?
bestDiffs
=
[
None
]
*
2
comp_step
=
(
1
,
NUM_FINE_STEPS
)[
compare_prim_steps
]
for
dly
in
range
(
low
,
high
+
1
):
ref_dly
=
dly
-
comp_step
if
ref_dly
<
low_safe
:
continue
if
quiet
<
2
:
print
(
"dly=
%
d, ref_dly=
%
d"
%
(
dly
,
ref_dly
),
end
=
" "
)
adiffs
=
get_lane_adiffs
(
low_safe
,
dly
,
branch
)
adiffs_ref
=
get_lane_adiffs
(
low_safe
,
ref_dly
,
branch
)
for
lane
in
range
(
len
(
adiffs
)):
diffs_prev_this
=
(
adiffs_ref
[
lane
],
adiffs
[
lane
])
if
(
diffs_prev_this
[
0
]
<=
0
)
and
(
diffs_prev_this
[
1
]
>=
0
):
if
abs
(
diffs_prev_this
[
0
])
<=
abs
(
diffs_prev_this
[
1
]):
# store previos sample
if
(
bestDiffs
[
lane
]
is
None
)
or
(
abs
(
diffs_prev_this
[
0
])
<
abs
(
bestDiffs
[
lane
])):
bestDly
[
lane
]
=
ref_dly
# dly-1/dly-NUM_FINE_STEPS
bestDiffs
[
lane
]
=
diffs_prev_this
[
0
]
else
:
if
(
bestDiffs
[
lane
]
is
None
)
or
(
abs
(
diffs_prev_this
[
1
])
<
abs
(
bestDiffs
[
lane
])):
bestDly
[
lane
]
=
dly
# dly-1
bestDiffs
[
lane
]
=
diffs_prev_this
[
1
]
if
(
adiffs
[
0
]
>
0
)
and
(
adiffs
[
1
]
>
0
):
break
# no need to continue, data got already
for
lane
in
range
(
len
(
adiffs
)):
if
bestDiffs
[
lane
]
==
-
1.0
:
bestDiffs
[
lane
]
=
None
# single step jumps from none to all
rslt
.
append
((
bestDly
[
lane
],
bestDiffs
[
lane
],
branch
[
0
]))
# adding first letter of branch name
if
quiet
<
3
:
print
(
"bestDly[
%
d]=
%
s, bestDiffs[
%
d]=
%
s, branch=
%
s"
%
(
lane
,
str
(
bestDly
[
lane
]),
lane
,
str
(
bestDiffs
[
lane
]),
branch
))
if
quiet
<
3
:
print
(
'dly=
%
d rslt=
%
s'
%
(
dly
,
str
(
rslt
)))
if
quiet
<
2
:
for
i
,
d
in
enumerate
(
dqsi_cache
):
if
d
:
print
(
"
%
d
%
s
%
d:
%
s"
%
(
phase
,
branch
,
i
,
str
(
d
)))
return
rslt
return
None
# All Early/Nominal/Late variants were exhausted, did not find critical DQS inoput delay for this phase value
# body of the measure_dqs_idly_phase()
dqsi_vs_phase
=
[]
for
phase
in
range
(
numPhaseSteps
):
if
quiet
<
3
:
print
(
"====== PHASE=
%
d ======"
%
(
phase
))
elif
quiet
<
4
:
print
(
"
%
d:"
%
(
phase
),
end
=
" "
)
sys
.
stdout
.
flush
()
dqsi_vs_phase
.
append
(
dqsi_phase_step
(
phase
))
if
quiet
<
4
:
print
(
"dqsi_vs_phase=
%
s"
%
(
str
(
dqsi_vs_phase
)))
print
(
"Phase DQSI0 DQSI1 diff0 diff1 branch0 branch1"
)
for
phase
,
v
in
enumerate
(
dqsi_vs_phase
):
print
(
"
%
d"
%
(
phase
),
end
=
" "
)
if
v
:
print
(
"
%
s
%
s
%
s
%
s
%
s
%
s"
%
(
str
(
v
[
0
][
0
]),
str
(
v
[
1
][
0
]),
str
(
v
[
0
][
1
]),
str
(
v
[
1
][
1
]),
v
[
0
][
2
],
v
[
1
][
2
]))
else
:
print
()
self
.
adjustment_state
[
'dqsi_vs_phase'
]
=
dqsi_vs_phase
self
.
adjustment_state
[
'dqsi_vs_phase_steps'
]
=
compare_prim_steps
return
dqsi_vs_phase
#dly_step
# compare_prim_steps
#meas_data=[
'''
adjust_cmda_odelay 0 1 0.1 3
adjust_write_levelling 0 1 0 .1 3
adjust_pattern 0.125 0.1 1
'''
def
proc_test_data
(
self
,
lane
=
0
,
def
load_hardcoded_data
(
self
):
"""
Debug feature - load hard-coded previously acquired/processed data
to reduce debugging time for nest stages
"""
self
.
adjustment_state
[
"dqi_dqsi"
]
=
get_test_dq_dqs_data
.
get_dqi_dqsi
()
self
.
adjustment_state
[
"dqi_dqsi_parameters"
]
=
get_test_dq_dqs_data
.
get_dqi_dqsi_parameters
()
self
.
adjustment_state
.
update
(
get_test_dq_dqs_data
.
get_adjust_cmda_odelay
())
self
.
adjustment_state
.
update
(
get_test_dq_dqs_data
.
get_wlev_data
())
self
.
adjustment_state
.
update
(
get_test_dq_dqs_data
.
get_dqsi_phase
())
def
proc_dqi_dqsi
(
self
,
lane
=
"all"
,
bin_size
=
5
,
primary_set
=
2
,
# compare_prim_steps=True, # while scanning, compare this delay with 1 less by primary(not fine) step,
# # save None for fraction in unknown (previous -0.5, next +0.5)
data_set_number
=
2
,
scale_w
=
0.
2
,
# weight for "uncertain" values (where samples chane from all 0 to all 1 in one step)
data_set_number
=
2
,
# not number - use measured data
scale_w
=
0.
0
,
# weight for "uncertain" values (where samples chane from all 0 to all 1 in one step)
quiet
=
1
):
"""
Run DQ vs DQS fitting for one data lane (0 or 1) using earlier acquired hard-coded data
@lane byte lane to process
@lane byte lane to process
(or non-number - process all byte lanes of the device)
@bin_size bin size for the histograms (should be 5/10/20/40)
@primary_set which of the data edge series to use as leading (other will be trailing by 180)
@data_set_number select one of the hard-coded data sets (sets 0 and 1 use comparing with the data 1 fine step below
set #2 (default) used measurement with previous primary step measurement (will not suffer from
fine range wider than on primary step)
If not number or <0 - use measured data
@scale_w weight for "uncertain" values (where samples change from all 0 to all 1 in one step)
For sufficient data 0.0 is OK (and seems to work better)- only "analog" samples are considered
@return 3-element dictionary of ('early','nominal','late'), each being None or a 160-element list,
each element being either None, or a list of 3 best DQ delay values for the DQS delay (some mey be None too)
"""
if
quiet
<
3
:
print
(
"proc_test_data(): scale_w=
%
f"
%
(
scale_w
))
compare_prim_steps
=
get_test_dq_dqs_data
.
get_compare_prim_steps
(
data_set_number
)
meas_data
=
get_test_dq_dqs_data
.
get_data
(
data_set_number
)
print
(
"proc_dqi_dqsi(): scale_w=
%
f"
%
(
scale_w
))
if
isinstance
(
data_set_number
,(
int
,
long
))
and
(
data_set_number
>=
0
)
:
if
quiet
<
4
:
print
(
"Using hard-coded data set #
%
d"
%
data_set_number
)
compare_prim_steps
=
get_test_dq_dqs_data
.
get_compare_prim_steps
(
data_set_number
)
meas_data
=
get_test_dq_dqs_data
.
get_data
(
data_set_number
)
else
:
if
quiet
<
4
:
print
(
"Using measured data set"
)
try
:
compare_prim_steps
=
self
.
adjustment_state
[
"patt_prim_steps"
]
meas_data
=
self
.
adjustment_state
[
"patt_meas_data"
]
except
:
print
(
"Pattern-measured data is not available, exiting"
)
return
meas_delays
=
[]
for
data
in
meas_data
:
if
data
:
...
...
@@ -2074,13 +2408,80 @@ class X393McntrlAdjust(object):
if
quiet
<
1
:
x393_lma
.
test_data
(
meas_delays
,
compare_prim_steps
,
quiet
)
lma
=
x393_lma
.
X393LMA
()
return
lma
.
lma_fit
(
lane
,
bin_size
,
2500.0
,
# clk_period,
78.0
,
# dly_step_ds,
primary_set
,
meas_delays
,
compare_prim_steps
,
scale_w
,
quiet
)
\ No newline at end of file
rslt
=
lma
.
lma_fit_dqi_dqsi
(
lane
,
bin_size
,
1000.0
*
self
.
x393_mcntrl_timing
.
get_dly_steps
()[
'SDCLK_PERIOD'
],
# 2500.0, # clk_period,
78.0
,
# dly_step_ds,
primary_set
,
meas_delays
,
compare_prim_steps
,
scale_w
,
quiet
)
if
quiet
<
5
:
lma
.
showENLresults
(
rslt
)
if
quiet
<
5
:
print
(
"dqi_dqsi={"
)
for
k
,
v
in
rslt
.
items
():
print
(
"'
%
s':
%
s,"
%
(
k
,
str
(
v
)))
print
(
"}"
)
self
.
adjustment_state
[
"dqi_dqsi_parameters"
]
=
rslt
.
pop
(
'parameters'
)
self
.
adjustment_state
[
"dqi_dqsi"
]
=
rslt
return
rslt
def
proc_dqsi_phase
(
self
,
lane
=
0
,
# "all",
bin_size_ps
=
50
,
data_set_number
=
0
,
# not number - use measured data
scale_w
=
0.1
,
# weight for "uncertain" values (where samples chane from all 0 to all 1 in one step)
quiet
=
1
):
"""
Run DQSI vs PHASE fitting for one data lane (0 or 1) using earlier acquired hard-coded data
@lane byte lane to process (or non-number - process all byte lanes of the device)
@bin_size_ps histogram bin size (in ps)
@data_set_number select one of the hard-coded data sets (sets 0 and 1 use comparing with the data 1 fine step below
set #0 (default) used measurement with previous primary step measurement (will not suffer from
fine range wider than on primary step)
If not number or <0 - use measured data
@scale_w weight for "uncertain" values (where samples change from all 0 to all 1 in one step)
For sufficient data 0.0 is OK (and seems to work better)- only "analog" samples are considered
@return 3-element dictionary of ('early','nominal','late'), each being None or a 160-element list,
each element being either None, or a list of 3 best DQ delay values for the DQS delay (some mey be None too)
"""
if
quiet
<
3
:
print
(
"proc_dqsi_phase(): scale_w=
%
f"
%
(
scale_w
))
if
isinstance
(
data_set_number
,(
int
,
long
))
and
(
data_set_number
>=
0
)
:
self
.
load_hardcoded_data
()
if
quiet
<
4
:
print
(
"Using hard-coded data set #
%
d"
%
data_set_number
)
compare_prim_steps
=
get_test_dq_dqs_data
.
get_dqsi_vs_phase_prim_steps
(
data_set_number
)
dqsi_phase_data
=
get_test_dq_dqs_data
.
get_dqsi_vs_phase
(
data_set_number
)
dqsi_dqi_parameters
=
get_test_dq_dqs_data
.
get_dqi_dqsi_parameters
()
else
:
if
quiet
<
4
:
print
(
"Using measured data set"
)
try
:
compare_prim_steps
=
self
.
adjustment_state
[
"dqsi_vs_phase_steps"
]
dqsi_phase_data
=
self
.
adjustment_state
[
"dqsi_vs_phase"
]
dqsi_dqi_parameters
=
self
.
adjustment_state
[
"dqi_dqsi_parameters"
]
except
:
print
(
"DQS input delay vs. phase measured data is not available, exiting"
)
return
timing
=
self
.
x393_mcntrl_timing
.
get_dly_steps
()
numPhaseSteps
=
int
(
timing
[
'SDCLK_PERIOD'
]
/
timing
[
'PHASE_STEP'
]
+
0.5
)
lma
=
x393_lma
.
X393LMA
()
# use persistent one?
dqsi_phase
=
lma
.
lma_fit_dqsi_phase
(
lane
,
# byte lane
bin_size_ps
,
1000.0
*
self
.
x393_mcntrl_timing
.
get_dly_steps
()[
'SDCLK_PERIOD'
],
# 2500.0, # clk_period,
# 1000.0*self.x393_mcntrl_timing.get_dly_steps()['PHASE_STEP'],# phase_step,
# dly_step_ds,
# primary_set,
dqsi_dqi_parameters
,
dqsi_phase_data
,
# data_set,
compare_prim_steps
,
scale_w
,
numPhaseSteps
,
quiet
=
1
)
self
.
adjustment_state
.
update
(
dqsi_phase
)
return
dqsi_phase
py393/x393_pio_sequences.py
View file @
faaa504f
...
...
@@ -441,13 +441,17 @@ class X393PIOSequences(object):
ba
,
# input [ 2:0] ba;
ra
,
# input [14:0] ra;
ca
,
#input [ 9:0] ca;
num8
=
64
,
sel
=
1
,
verbose
=
0
):
"""
Setup read block sequence at parameter defined address in the sequencer memory
<ba> 3-bit memory bank address
<ra> 15-bit memory row address
<ca> 10-bit memory column address
<verbose> print data being written (default: False)
@ba 3-bit memory bank address
@ra 15-bit memory row address
@ca 10-bit memory column address
@num8 - number of 8-bursts to read (maximal 64, min- 2)
@sel - 0 - early, 1 - late read command
@verbose print data being written (default: False)
"""
cmd_addr
=
vrlg
.
MCONTR_CMD_WR_ADDR
+
vrlg
.
READ_BLOCK_OFFSET
...
...
@@ -464,34 +468,34 @@ class X393PIOSequences(object):
# first read
# read
# addr bank RCW ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD NOP, B_RST
data
=
self
.
func_encode_cmd
(
ca
&
0x3ff
,
ba
,
2
,
0
,
0
,
1
,
0
,
0
,
0
,
1
,
1
,
0
,
0
,
0
)
data
=
self
.
func_encode_cmd
(
ca
&
0x3ff
,
ba
,
2
,
0
,
0
,
sel
,
0
,
0
,
0
,
1
,
1
,
0
,
0
,
0
)
self
.
x393_mem
.
axi_write_single_w
(
cmd_addr
,
data
,
verbose
)
cmd_addr
+=
1
# nop
# skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
data
=
self
.
func_encode_skip
(
0
,
0
,
ba
,
0
,
0
,
1
,
0
,
0
,
0
,
1
,
1
,
0
,
0
)
data
=
self
.
func_encode_skip
(
0
,
0
,
ba
,
0
,
0
,
sel
,
0
,
0
,
0
,
1
,
1
,
0
,
0
)
self
.
x393_mem
.
axi_write_single_w
(
cmd_addr
,
data
,
verbose
)
cmd_addr
+=
1
#repeat remaining reads
for
i
in
range
(
1
,
64
):
for
i
in
range
(
1
,
num8
):
# read
# addr bank RCW ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD NOP, B_RST
data
=
self
.
func_encode_cmd
((
ca
&
0x3ff
)
+
(
i
<<
3
),
ba
,
2
,
0
,
0
,
1
,
0
,
0
,
0
,
1
,
1
,
0
,
1
,
0
)
data
=
self
.
func_encode_cmd
((
ca
&
0x3ff
)
+
(
i
<<
3
),
ba
,
2
,
0
,
0
,
sel
,
0
,
0
,
0
,
1
,
1
,
0
,
1
,
0
)
self
.
x393_mem
.
axi_write_single_w
(
cmd_addr
,
data
,
verbose
)
cmd_addr
+=
1
# nop - all 3 below are the same? - just repeat?
# skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
data
=
self
.
func_encode_skip
(
0
,
0
,
ba
,
0
,
0
,
1
,
0
,
0
,
0
,
1
,
0
,
0
,
0
)
data
=
self
.
func_encode_skip
(
0
,
0
,
ba
,
0
,
0
,
sel
,
0
,
0
,
0
,
1
,
0
,
0
,
0
)
self
.
x393_mem
.
axi_write_single_w
(
cmd_addr
,
data
,
verbose
)
cmd_addr
+=
1
# nop
# skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
data
=
self
.
func_encode_skip
(
0
,
0
,
ba
,
0
,
0
,
1
,
0
,
0
,
0
,
1
,
0
,
0
,
0
)
data
=
self
.
func_encode_skip
(
0
,
0
,
ba
,
0
,
0
,
sel
,
0
,
0
,
0
,
1
,
0
,
0
,
0
)
self
.
x393_mem
.
axi_write_single_w
(
cmd_addr
,
data
,
verbose
)
cmd_addr
+=
1
# nop
# skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
data
=
self
.
func_encode_skip
(
0
,
0
,
ba
,
0
,
0
,
1
,
0
,
0
,
0
,
1
,
0
,
0
,
0
)
data
=
self
.
func_encode_skip
(
0
,
0
,
ba
,
0
,
0
,
sel
,
0
,
0
,
0
,
1
,
0
,
0
,
0
)
self
.
x393_mem
.
axi_write_single_w
(
cmd_addr
,
data
,
verbose
)
cmd_addr
+=
1
# tRTP = 4*tCK is already satisfied, no skip here
...
...
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