fixed histograms_saxi, using 100MHz clock for both saxigp<0,1>, v 03931016 (f99260f2) · Commits · Elphel / x393

axi/histogram_saxi.v

+66 −10

Original line number	Original line	Diff line number	Diff line
	@@ -40,7 +40,11 @@
	// Number of histograms per sensor is now statically defined by NUM_FRAME_BITS		// Number of histograms per sensor is now statically defined by NUM_FRAME_BITS
	// It may be modified to both reduce this number (by masking) or increase ( by		// It may be modified to both reduce this number (by masking) or increase ( by
	// keeping pointer locally)		// keeping pointer locally)
			// move to system_defines, it slowes SAXI_AW and reduces requirements on the ready inputs

			`define MOD_SAXI 1
			///`define FAKE_WDATA 1
			///`define FAKE1_WDATA 1
	module histogram_saxi#(		module histogram_saxi#(
	parameter HIST_SAXI_ADDR = 'h380, // 16 locations to write 20 bits of a 4KB page for the histogram		parameter HIST_SAXI_ADDR = 'h380, // 16 locations to write 20 bits of a 4KB page for the histogram
	parameter HIST_SAXI_ADDR_MASK = 'h7f0,		parameter HIST_SAXI_ADDR_MASK = 'h7f0,
	@@ -60,7 +64,7 @@ module histogram_saxi#(
	)(		)(
	// input rst,		// input rst,
	input mclk, // for command/status		input mclk, // for command/status
	input aclk, // global clock to run s_axi (@150MHz?)		input aclk, // global clock to run s_axi (@150MHz?) saxi0_aclk
	input mrst, // @posedge mclk, sync reset		input mrst, // @posedge mclk, sync reset
	input arst, // @posedge aclk, sync reset		input arst, // @posedge aclk, sync reset

	@@ -206,7 +210,6 @@ module histogram_saxi#(
	reg [31:10] hist_start_addr; // higher bits of the system memory address of the histogram (1024 bytes) start		reg [31:10] hist_start_addr; // higher bits of the system memory address of the histogram (1024 bytes) start
	reg [31: 6] start_addr_r; // higher bits of the system memory address of the saxi burst start address		reg [31: 6] start_addr_r; // higher bits of the system memory address of the saxi burst start address

	wire saxi_start_burst_w;
	reg first_burst;		reg first_burst;
	wire [31:0] inter_buf_data; // data between bram buffer and a small FIFO		wire [31:0] inter_buf_data; // data between bram buffer and a small FIFO
	reg [3:0] wburst_cntr; // count words in output data burst (using max==16)		reg [3:0] wburst_cntr; // count words in output data burst (using max==16)
	@@ -215,10 +218,58 @@ module histogram_saxi#(
	wire fifo_nempty;		wire fifo_nempty;
	wire fifo_half_full;		wire fifo_half_full;
	reg [2:0] buf_re; // {fifo_we, buf_regen, buf_re}		reg [2:0] buf_re; // {fifo_we, buf_regen, buf_re}
			wire buf_re_last_w; // reading last word from the buffer
	wire buf_re_w;		wire buf_re_w;
	wire fifo_re;		wire fifo_re;
	reg saxi_bvalid_r;		reg saxi_bvalid_r;
	reg page_read_run; // reading buffer page until page_ra reads 'hff		reg page_read_run; // reading buffer page until page_ra reads 'hff
			`ifdef FAKE_WDATA
			reg [31:0] wdata_fake;
			reg [31:0] wdata_fake_r;
			reg wdata_fake_inc;
			`else
			wire [31:0] wdata;
			`endif

			`ifdef MOD_SAXI
			reg saxi_start_burst;
			reg saxi_awvalid_r;
			wire start_burst_w;
			assign start_burst_w = saxi_awvalid && saxi_awready;
			assign saxi_awvalid = saxi_awvalid_r; // ((\|start_addr_r[9:6]) \|\| first_burst) && !saxi_start_burst && !arst ; // TODO: make it a register
			always @(posedge aclk) begin
			saxi_start_burst <= start_burst_w;
			if (arst \|\| start_burst_w) saxi_awvalid_r <= 0;
			else saxi_awvalid_r <= first_burst \|\|
			(saxi_start_burst ? (start_addr_r[9:6] != 'hf) : (\|start_addr_r[9:6]));
			end
			`else
			wire saxi_start_burst;
			assign saxi_awvalid = ((\|start_addr_r[9:6]) \|\| first_burst) && !arst;
			assign saxi_start_burst = saxi_awvalid && saxi_awready;
			`endif

			`ifdef FAKE_WDATA
			assign saxi_wdata = wdata_fake_r;
			always @ (posedge aclk) begin

			// wdata_fake_inc <= en_aclk && saxi_awvalid && saxi_awready; // v 100b
			wdata_fake_inc <= en_aclk && saxi_wvalid && saxi_wready; // v 100c
			if (!en_aclk) wdata_fake[15:0] <= 0;
			else if (wdata_fake_inc) wdata_fake[15:0] <= wdata_fake[15:0] + 1;
			if (!en_aclk) wdata_fake[31:16] <= 0;
			else wdata_fake[31:16] <= wdata_fake[31:16] + 1;
			`ifdef FAKE1_WDATA
			wdata_fake_r[31:16] <= wdata_fake[31:16];
			wdata_fake_r[15:0] <= start_addr_r[21:6];
			`else
			wdata_fake_r <= wdata_fake;
			`endif
			end
			//start_addr_r[31:6]
			`else
			assign saxi_wdata = wdata;
			`endif

	// reg [9:0] buf_raddr; // nuffer read address {page[1:0], addr [7:0]}		// reg [9:0] buf_raddr; // nuffer read address {page[1:0], addr [7:0]}

	@@ -312,11 +363,11 @@ module histogram_saxi#(
	assign attrib_frame = attrib_r[2+:NUM_FRAME_BITS];		assign attrib_frame = attrib_r[2+:NUM_FRAME_BITS];
	assign attrib_color = attrib_r[1:0];		assign attrib_color = attrib_r[1:0];

	assign saxi_start_burst_w = saxi_awvalid && saxi_awready;		// assign saxi_start_burst = saxi_awvalid && saxi_awready;

	assign saxi_awaddr = {start_addr_r[31:6],6'b0};		assign saxi_awaddr = {start_addr_r[31:6],6'b0};

	assign saxi_awvalid = ((\|start_addr_r[9:6]) \|\| first_burst) && !arst;		// assign saxi_awvalid = ((\|start_addr_r[9:6]) \|\| first_burst) && !arst;
	//{enc_rq[1:0], sub_chn_r, frame_r, burst[1:0]}		//{enc_rq[1:0], sub_chn_r, frame_r, burst[1:0]}

	// assign block_end= ???;		// assign block_end= ???;
	@@ -340,7 +391,10 @@ module histogram_saxi#(


	// TODO: Maybe reduce pause between 16-burst pages? Allow some overlap?		// TODO: Maybe reduce pause between 16-burst pages? Allow some overlap?
	assign buf_re_w = en_aclk && (\|pages_in_buf_rd) && !fifo_half_full && !(&page_ra) && page_read_run; // will stay off until next page
			assign buf_re_last_w = &page_ra && buf_re[0];
			// assign buf_re_w = en_aclk && (\|pages_in_buf_rd) && !fifo_half_full && !(&page_ra) && page_read_run; // will stay off until next page
			assign buf_re_w = en_aclk && (\|pages_in_buf_rd) && !fifo_half_full && !buf_re_last_w && page_read_run; // will stay off until next page
	assign fifo_re= saxi_wvalid && saxi_wready;		assign fifo_re= saxi_wvalid && saxi_wready;
	// currently waiting for SAXI to get confirmnation of all data in the current page before proceeding to the next		// currently waiting for SAXI to get confirmnation of all data in the current page before proceeding to the next
	//		//
	@@ -417,7 +471,9 @@ module histogram_saxi#(
	else if (buf_re[0]) page_ra <= page_ra + 1;		else if (buf_re[0]) page_ra <= page_ra + 1;

	if (!en_aclk) page_read_run <= 0;		if (!en_aclk) page_read_run <= 0;
	else page_read_run <= block_start_r[1] \|\| (page_read_run && !(&page_ra)); // until page_ra is 8'hff		// else page_read_run <= block_start_r[1] \|\| (page_read_run && !(&page_ra)); // until page_ra is 8'hff
			else page_read_run <= block_start_r[1] \|\| (page_read_run && !buf_re_last_w); // until page_ra is 8'hff
			//

	if (!en_aclk) pages_in_buf_rd <= 0;		if (!en_aclk) pages_in_buf_rd <= 0;
	else if ( page_written_aclk && !page_sent_aclk) pages_in_buf_rd <= pages_in_buf_rd + 1;		else if ( page_written_aclk && !page_sent_aclk) pages_in_buf_rd <= pages_in_buf_rd + 1;
	@@ -437,11 +493,11 @@ module histogram_saxi#(
	if (block_start_r[2]) hist_start_addr[11:10] <= attrib_color;		if (block_start_r[2]) hist_start_addr[11:10] <= attrib_color;

	if (arst \|\| block_start_r[3]) start_addr_r[31:6] <= {hist_start_addr[31:10], 4'b0};		if (arst \|\| block_start_r[3]) start_addr_r[31:6] <= {hist_start_addr[31:10], 4'b0};
	else if (saxi_start_burst_w) start_addr_r[31:6] <= start_addr_r[31:6] + 1;		else if (saxi_start_burst) start_addr_r[31:6] <= start_addr_r[31:6] + 1;

	if (!nreset_aclk \|\| arst) first_burst <= 0;		if (!nreset_aclk \|\| arst) first_burst <= 0;
	else if (block_start_r[3]) first_burst <= 1; // block_start_r[3] - same as start_addr_r set		else if (block_start_r[3]) first_burst <= 1; // block_start_r[3] - same as start_addr_r set
	else if (saxi_start_burst_w) first_burst <= 0;		else if (saxi_start_burst) first_burst <= 0;

	if (block_start_r[0]) awcache_mode <= mode[HIST_SAXI_AWCACHE+:4];		if (block_start_r[0]) awcache_mode <= mode[HIST_SAXI_AWCACHE+:4];
	if (block_start_r[0]) confirm_write <= mode[HIST_CONFIRM_WRITE];		if (block_start_r[0]) confirm_write <= mode[HIST_CONFIRM_WRITE];
	@@ -531,8 +587,8 @@ module histogram_saxi#(
	.we (buf_re[2]), // input		.we (buf_re[2]), // input
	.re (fifo_re), // input		.re (fifo_re), // input
	.data_in (inter_buf_data), // input[31:0]		.data_in (inter_buf_data), // input[31:0]
	.data_out (saxi_wdata), // output[31:0]		.data_out (wdata), // output[31:0]
	.nempty (fifo_nempty), // output		.nempty (fifo_nempty), // output (fast register output)
	.half_full (fifo_half_full) // output reg		.half_full (fifo_half_full) // output reg
	);		);
	endmodule		endmodule

cocotb/x393_cocotb_lwir_07.sav

0 → 100644

+1763 −0

File added.

Preview size limit exceeded, changes collapsed.

fpga_version.vh

+19 −2

Original line number	Original line	Diff line number	Diff line
	@@ -35,7 +35,24 @@
	* contains all the components and scripts required to completely simulate it		* contains all the components and scripts required to completely simulate it
	* with at least one of the Free Software programs.		* with at least one of the Free Software programs.
	*/		*/
	parameter FPGA_VERSION = 32'h03931005; // parallel, converting from 32'h0393401a		parameter FPGA_VERSION = 32'h03931016; // debugging histograms - MOD_SAXI on, restore actual histogram data
			// parameter FPGA_VERSION = 32'h03931015; // debugging histograms - MOD_SAXI on, fixed some bugs related to inactive cycle with page_ra == 8'hff - works?
			// parameter FPGA_VERSION = 32'h03931014; // debugging histograms - MOD_SAXI on, updates sim_saxi to match hardware (wlast disables wready, smaller fifo)
			// parameter FPGA_VERSION = 32'h03931013; // debugging histograms - trying to re-enable FAKE_WDATA1 top word - timer, lower - page address - OK
			// parameter FPGA_VERSION = 32'h03931012; // debugging histograms - trying to re-enable FAKE_WDATA1 - failed
			// parameter FPGA_VERSION = 32'h03931011; // debugging histograms - disabled FAKE_WDATA1 - works
			// parameter FPGA_VERSION = 32'h03931010; // debugging histograms - define FAKE_WDATA1, wdata_fake_r <= {start_addr_r[21:6], wdata_fake[15:0]};
			// parameter FPGA_VERSION = 32'h0393100f; // debugging histograms - high 16 bits - always count with MOD_SAXI, getting stuck
			// parameter FPGA_VERSION = 32'h0393100e; // debugging histograms - high 16 bits - always count
			// parameter FPGA_VERSION = 32'h0393100d; // debugging histograms - counts aw saxi_wvalid && saxi_wready - extra buffer
			// parameter FPGA_VERSION = 32'h0393100c; // debugging histograms - counts aw saxi_wvalid && saxi_wready
			// parameter FPGA_VERSION = 32'h0393100b; // debugging histograms - counts aw saxi_awvalid && saxi_awready
			// parameter FPGA_VERSION = 32'h0393100a; // reducing saxi speed from 150 to 100 MHz (both histograms and the logger)
			// parameter FPGA_VERSION = 32'h03931009; // trying to boost SAXI (clock 190 instead of 150) with set_clock_uncertainty - got stuck (maybe my fault)
			// parameter FPGA_VERSION = 32'h03931008; // trying to boost SAXI (clock 200 instead of 150) seems OK
			// parameter FPGA_VERSION = 32'h03931007; // changed histogram_saxi - still fails
			// parameter FPGA_VERSION = 32'h03931006; // parallel 03931006A - good, 03931006 - bad. will investigate
			// parameter FPGA_VERSION = 32'h03931005; // parallel, converting from 32'h0393401a
	// parameter FPGA_VERSION = 32'h0393401a; // adding strobe output for IMX-5 on ext-5		// parameter FPGA_VERSION = 32'h0393401a; // adding strobe output for IMX-5 on ext-5
	// parameter FPGA_VERSION = 32'h03934019; // Boson640, logger debug disabled		// parameter FPGA_VERSION = 32'h03934019; // Boson640, logger debug disabled
	// parameter FPGA_VERSION = 32'h03934018; // Boson640, debugging logger 02		// parameter FPGA_VERSION = 32'h03934018; // Boson640, debugging logger 02

sensor/sensors393.v

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -596,7 +596,7 @@ module sensors393 #(

	// S_AXI interface write only (histograms out)		// S_AXI interface write only (histograms out)
	// write address		// write address
	input aclk, // global clock for S_AXI0 (150 MHz)		input aclk, // global clock for S_AXI0 (150 MHz) saxi0_aclk
	output [31:0] saxi_awaddr, // AXI PS Slave GP0 AWADDR[31:0], input		output [31:0] saxi_awaddr, // AXI PS Slave GP0 AWADDR[31:0], input
	output saxi_awvalid, // AXI PS Slave GP0 AWVALID, input		output saxi_awvalid, // AXI PS Slave GP0 AWVALID, input
	input saxi_awready, // AXI PS Slave GP0 AWREADY, output		input saxi_awready, // AXI PS Slave GP0 AWREADY, output

simulation_modules/simul_saxi_gp_wr.v

+20 −7

Original line number	Original line	Diff line number	Diff line
	@@ -79,10 +79,14 @@ module simul_saxi_gp_wr(
	input [ 3:0] sim_bresp_latency, // latency in writing data outside of the module		input [ 3:0] sim_bresp_latency, // latency in writing data outside of the module
	output [ 3:0] sim_wr_qos		output [ 3:0] sim_wr_qos
	);		);
	localparam AW_FIFO_DEPTH = 3; // FIFO number of address bits to fit AW_FIFO_NUM (number is one bit wider)		// TODO change these localparam to parameters
	localparam W_FIFO_DEPTH = 3; // FIFO number of address bits to fit W_FIFO_NUM		localparam AW_FIFO_DEPTH = 2; // 7; //3; // FIFO number of address bits to fit AW_FIFO_NUM (number is one bit wider)
	localparam [AW_FIFO_DEPTH:0] AW_FIFO_NUM = 8; // Maximal number of words in AW FIFO 8-words		localparam W_FIFO_DEPTH = 3; // 2; // 7; //3; // FIFO number of address bits to fit W_FIFO_NUM
	localparam [W_FIFO_DEPTH:0] W_FIFO_NUM = 8; // Maximal number of words in AW 8-words		localparam WREADY_DELAY_AFTER_LAST = 3; // negate wready for these number of clocks after wlast (0..7)


			localparam [AW_FIFO_DEPTH:0] AW_FIFO_NUM = 1 << AW_FIFO_DEPTH; // 128; // 8; // Maximal number of words in AW FIFO 8-words
			localparam [W_FIFO_DEPTH:0] W_FIFO_NUM = 1 << W_FIFO_DEPTH; // 8; // Maximal number of words in AW 8-words


	localparam VALID_AWLOCK = 2'b0; // TODO		localparam VALID_AWLOCK = 2'b0; // TODO
	@@ -98,7 +102,8 @@ To make it work, I set the (AR/AW)CACHE=0x11 and (AR/AW)PROT=0x00. In the CDMA d
	The default values set by VHLS were 0x00 and 0x10 respectively, which is also the case in the last post.		The default values set by VHLS were 0x00 and 0x10 respectively, which is also the case in the last post.
	Alex		Alex
	*/		*/
			reg [WREADY_DELAY_AFTER_LAST : 0] wlast_d = 0; // [3:0] extra bit, but should work with WREADY_DELAY_AFTER_LAST == 0
			wire wlast_nready;
	wire aw_nempty;		wire aw_nempty;
	wire w_nempty;		wire w_nempty;
	reg [11:0] next_wr_address_w; // bits that are incremented in 32-bit mode (higher are kept according to AXI 4KB inc. limit)		reg [11:0] next_wr_address_w; // bits that are incremented in 32-bit mode (higher are kept according to AXI 4KB inc. limit)
	@@ -140,10 +145,18 @@ Alex
	// priority transactions are backed up behind it." Whqt about demotion? Assuming it is not demoted		// priority transactions are backed up behind it." Whqt about demotion? Assuming it is not demoted
	assign aresetn= ~rst; // probably not needed at all - docs say "do not use"		assign aresetn= ~rst; // probably not needed at all - docs say "do not use"

			assign wlast_nready = (((1 << WREADY_DELAY_AFTER_LAST) -1) & wlast_d) != 0;
	// generate ready signals for address and data		// generate ready signals for address and data
	// assign wready= !wcount[7] && (!(&wcount[6:0]) \|\| !fifo_data_we_d);		// assign wready= !wcount[7] && (!(&wcount[6:0]) \|\| !fifo_data_we_d);
	assign wready = (wcount < W_FIFO_NUM) && ((wcount < (W_FIFO_NUM-1)) \|\| !fifo_data_we_d);		assign wready = ((wcount < W_FIFO_NUM) && ((wcount < (W_FIFO_NUM-1)) \|\| !fifo_data_we_d)) && !wlast_nready;

			always @ (posedge rst or posedge aclk) begin
			if (rst) wlast_d<=0;
			else wlast_d <= (wlast_d << 1) \| {{WREADY_DELAY_AFTER_LAST{1'b0}}, (wlast & wready & wvalid)};
			end



	always @ (posedge rst or posedge aclk) begin		always @ (posedge rst or posedge aclk) begin
	if (rst) fifo_data_we_d<=0;		if (rst) fifo_data_we_d<=0;
	else fifo_data_we_d <= wready && wvalid;		else fifo_data_we_d <= wready && wvalid;

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