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Commit f69ec863 authored by Andrey Filippov's avatar Andrey Filippov
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Bug fixing while comparing special cases

parent 358f3d9c
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Showing with 280 additions and 98 deletions
dsp/mclt16x16.v
View file @ f69ec863
...@@ -532,7 +532,7 @@ D11 - negate for mode 3 (SS) ...@@ -532,7 +532,7 @@ D11 - negate for mode 3 (SS)
.rclk (clk), // input .rclk (clk), // input
.raddr (dtt_rd_ra), // input[8:0] .raddr (dtt_rd_ra), // input[8:0]
.ren (dtt_rd_regen_dv[0]), // input .ren (dtt_rd_regen_dv[0]), // input
.regen (dtt_rd_regen_dv[0]), // input .regen (dtt_rd_regen_dv[1]), // input
.data_out (dtt_rd_data_w), // output[35:0] .data_out (dtt_rd_data_w), // output[35:0]
.wclk (clk), // input .wclk (clk), // input
.waddr (dtt_out_ram_wa), // input[8:0] .waddr (dtt_out_ram_wa), // input[8:0]
......
dsp/mclt_test_01.tf
View file @ f69ec863
...@@ -109,6 +109,7 @@ module mclt_test_01 (); ...@@ -109,6 +109,7 @@ module mclt_test_01 ();
$readmemh("input_data/clt_fold_index.dat", java_fold_index); $readmemh("input_data/clt_fold_index.dat", java_fold_index);
// $readmemh("input_data/tile_01.dat",tile_shift); // $readmemh("input_data/tile_01.dat",tile_shift);
//============ tile 0
$readmemh("input_data/clt_tile_00_2_x1489_y951.dat",tile_shift); $readmemh("input_data/clt_tile_00_2_x1489_y951.dat",tile_shift);
shifts_x[0] = tile_shift[0][SHIFT_WIDTH-1:0]; shifts_x[0] = tile_shift[0][SHIFT_WIDTH-1:0];
shifts_y[0] = tile_shift[1][SHIFT_WIDTH-1:0]; shifts_y[0] = tile_shift[1][SHIFT_WIDTH-1:0];
...@@ -136,27 +137,95 @@ module mclt_test_01 (); ...@@ -136,27 +137,95 @@ module mclt_test_01 ();
java_dtt_rot['h000 + i] = java_dtt_rot0[i]; java_dtt_rot['h000 + i] = java_dtt_rot0[i];
end end
$readmemh("input_data/tile_02.dat",tile_shift); //============ tile 1
$readmemh("input_data/clt_tile_01_2_x1489_y951.dat",tile_shift);
shifts_x[1] = tile_shift[0][SHIFT_WIDTH-1:0]; shifts_x[1] = tile_shift[0][SHIFT_WIDTH-1:0];
shifts_y[1] = tile_shift[1][SHIFT_WIDTH-1:0]; shifts_y[1] = tile_shift[1][SHIFT_WIDTH-1:0];
bayer[1] = tile_shift[2][3:0]; bayer[1] = tile_shift[2][3:0];
for (i=0; i<256; i=i+1) begin for (i=0; i<256; i=i+1) begin
tiles['h100 + i] = tile_shift[i+3]; tiles['h100 + i] = tile_shift[i+3];
end end
$readmemh("input_data/tile_03.dat",tile_shift);
$readmemh("input_data/clt_wnd_01_2_x1489_y951.dat",java_tiles_wnd);
for (i=0; i<256; i=i+1) begin
tiles_wnd['h100 + i] = java_tiles_wnd[i];
end
$readmemh("input_data/clt_dtt_in_01_2_x1489_y951.dat",java_dtt_in0);
for (i=0; i<256; i=i+1) begin
java_dtt_in['h100 + i] = java_dtt_in0[i];
end
$readmemh("input_data/clt_dtt_out_01_2_x1489_y951.dat",java_dtt_out0);
for (i=0; i<256; i=i+1) begin
java_dtt_out['h100 + i] = java_dtt_out0[i];
end
$readmemh("input_data/clt_dtt_rot_01_2_x1489_y951.dat",java_dtt_rot0);
for (i=0; i<256; i=i+1) begin
java_dtt_rot['h100 + i] = java_dtt_rot0[i];
end
//============ tile 2
$readmemh("input_data/clt_tile_02_2_x1489_y951.dat",tile_shift);
shifts_x[2] = tile_shift[0][SHIFT_WIDTH-1:0]; shifts_x[2] = tile_shift[0][SHIFT_WIDTH-1:0];
shifts_y[2] = tile_shift[1][SHIFT_WIDTH-1:0]; shifts_y[2] = tile_shift[1][SHIFT_WIDTH-1:0];
bayer[2] = tile_shift[2][3:0]; bayer[2] = tile_shift[2][3:0];
for (i=0; i<256; i=i+1) begin for (i=0; i<256; i=i+1) begin
tiles['h200 + i] = tile_shift[i+3]; tiles['h200 + i] = tile_shift[i+3];
end end
$readmemh("input_data/tile_04.dat",tile_shift);
$readmemh("input_data/clt_wnd_02_2_x1489_y951.dat",java_tiles_wnd);
for (i=0; i<256; i=i+1) begin
tiles_wnd['h200 + i] = java_tiles_wnd[i];
end
$readmemh("input_data/clt_dtt_in_02_2_x1489_y951.dat",java_dtt_in0);
for (i=0; i<256; i=i+1) begin
java_dtt_in['h200 + i] = java_dtt_in0[i];
end
$readmemh("input_data/clt_dtt_out_02_2_x1489_y951.dat",java_dtt_out0);
for (i=0; i<256; i=i+1) begin
java_dtt_out['h200 + i] = java_dtt_out0[i];
end
$readmemh("input_data/clt_dtt_rot_02_2_x1489_y951.dat",java_dtt_rot0);
for (i=0; i<256; i=i+1) begin
java_dtt_rot['h200 + i] = java_dtt_rot0[i];
end
//============ tile 3
$readmemh("input_data/clt_tile_00_2_x1489_y951.dat",tile_shift);
shifts_x[3] = tile_shift[0][SHIFT_WIDTH-1:0]; shifts_x[3] = tile_shift[0][SHIFT_WIDTH-1:0];
shifts_y[3] = tile_shift[1][SHIFT_WIDTH-1:0]; shifts_y[3] = tile_shift[1][SHIFT_WIDTH-1:0];
bayer[3] = tile_shift[2][3:0]; bayer[3] = tile_shift[2][3:0];
for (i=0; i<256; i=i+1) begin for (i=0; i<256; i=i+1) begin
tiles['h300 + i] = tile_shift[i+3]; tiles['h300 + i] = tile_shift[i+3];
end end
$readmemh("input_data/clt_wnd_00_2_x1489_y951.dat",java_tiles_wnd);
for (i=0; i<256; i=i+1) begin
tiles_wnd['h300 + i] = java_tiles_wnd[i];
end
$readmemh("input_data/clt_dtt_in_00_2_x1489_y951.dat",java_dtt_in0);
for (i=0; i<256; i=i+1) begin
java_dtt_in['h300 + i] = java_dtt_in0[i];
end
$readmemh("input_data/clt_dtt_out_00_2_x1489_y951.dat",java_dtt_out0);
for (i=0; i<256; i=i+1) begin
java_dtt_out['h300 + i] = java_dtt_out0[i];
end
$readmemh("input_data/clt_dtt_rot_00_2_x1489_y951.dat",java_dtt_rot0);
for (i=0; i<256; i=i+1) begin
java_dtt_rot['h300 + i] = java_dtt_rot0[i];
end
for (n=0;n<4;n=n+1) begin for (n=0;n<4;n=n+1) begin
$display("Tile %d: shift x = %h, shift_y = %h, bayer = %h", 0, shifts_x[n], shifts_y[n], bayer[n]); $display("Tile %d: shift x = %h, shift_y = %h, bayer = %h", 0, shifts_x[n], shifts_y[n], bayer[n]);
for (i = 256 * n; i < 256 * (n + 1); i = i + 16) begin for (i = 256 * n; i < 256 * (n + 1); i = i + 16) begin
...@@ -273,7 +342,7 @@ module mclt_test_01 (); ...@@ -273,7 +342,7 @@ module mclt_test_01 ();
integer n2, cntr2, diff2, diff2a; // SuppressThisWarning VEditor : assigned in $readmem() system task integer n2, cntr2, diff2, diff2a; // SuppressThisWarning VEditor : assigned in $readmem() system task
wire [WND_WIDTH-1:0] window_r = mclt16x16_i.window_r; wire [WND_WIDTH-1:0] window_r = mclt16x16_i.window_r;
// reg [7:0] java_fi_r; // reg [7:0] java_fi_r;
wire [WND_WIDTH-1:0] java_window_w = java_tiles_wnd[cntr2]; // tiles_wnd[n2 * 256 + cntr2]; wire [WND_WIDTH-1:0] java_window_w = tiles_wnd[n2 * 256 + cntr2]; // java_tiles_wnd[cntr2];
initial begin initial begin
while (RST) @(negedge CLK); while (RST) @(negedge CLK);
for (n2 = 0; n2 < 4; n2 = n2+1) begin for (n2 = 0; n2 < 4; n2 = n2+1) begin
...@@ -291,9 +360,6 @@ module mclt_test_01 (); ...@@ -291,9 +360,6 @@ module mclt_test_01 ();
//Compare window signs //Compare window signs
integer n3, cntr3, diff3; // SuppressThisWarning VEditor : assigned in $readmem() system task integer n3, cntr3, diff3; // SuppressThisWarning VEditor : assigned in $readmem() system task
wire [3:0] mpix_sgn_w = mclt16x16_i.mpix_sgn_w; // SuppressThisWarning VEditor : assigned in $readmem() system task wire [3:0] mpix_sgn_w = mclt16x16_i.mpix_sgn_w; // SuppressThisWarning VEditor : assigned in $readmem() system task
// wire [3:0] java_sgn_w = java_wnd_signs[java_fold_index[cntr3]]; // SuppressThisWarning VEditor : assigned in $readmem() system task
// wire [3:0] java_sgn_w1 = java_wnd_signs[java_fold_index[cntr3]]; // SuppressThisWarning VEditor : assigned in $readmem() system task
wire [3:0] java_sgn_w = { //java_wnd_signs[java_fold_index[cntr3]]; // SuppressThisWarning VEditor : assigned in $readmem() system task wire [3:0] java_sgn_w = { //java_wnd_signs[java_fold_index[cntr3]]; // SuppressThisWarning VEditor : assigned in $readmem() system task
java_wnd_signs[{2'b11,cntr3[7:2]}][cntr3[1:0]], java_wnd_signs[{2'b11,cntr3[7:2]}][cntr3[1:0]],
java_wnd_signs[{2'b10,cntr3[7:2]}][cntr3[1:0]], java_wnd_signs[{2'b10,cntr3[7:2]}][cntr3[1:0]],
...@@ -318,7 +384,7 @@ module mclt_test_01 (); ...@@ -318,7 +384,7 @@ module mclt_test_01 ();
integer n4, cntr4, diff4, diff4a; // SuppressThisWarning VEditor : assigned in $readmem() system task integer n4, cntr4, diff4, diff4a; // SuppressThisWarning VEditor : assigned in $readmem() system task
wire [DTT_IN_WIDTH-1:0] data_dtt_in = mclt16x16_i.data_dtt_in; wire [DTT_IN_WIDTH-1:0] data_dtt_in = mclt16x16_i.data_dtt_in;
wire [DTT_IN_WIDTH-1:0] java_data_dtt_in = java_dtt_in0[{cntr4[1:0],cntr4[7:2]}]; // java_dtt_in[n2 * 256 + cntr2]; wire [DTT_IN_WIDTH-1:0] java_data_dtt_in = java_dtt_in[{n4[1:0], cntr4[1:0],cntr4[7:2]}]; // java_dtt_in0[{cntr4[1:0],cntr4[7:2]}]
initial begin initial begin
while (RST) @(negedge CLK); while (RST) @(negedge CLK);
for (n4 = 0; n4 < 4; n4 = n4+1) begin for (n4 = 0; n4 < 4; n4 = n4+1) begin
...@@ -336,7 +402,7 @@ module mclt_test_01 (); ...@@ -336,7 +402,7 @@ module mclt_test_01 ();
integer n5, cntr5, diff5, diff5a; // SuppressThisWarning VEditor : assigned in $readmem() system task integer n5, cntr5, diff5, diff5a; // SuppressThisWarning VEditor : assigned in $readmem() system task
wire [DTT_IN_WIDTH-1:0] dtt_r_data = mclt16x16_i.dtt_r_data; wire [DTT_IN_WIDTH-1:0] dtt_r_data = mclt16x16_i.dtt_r_data;
wire [DTT_IN_WIDTH-1:0] java_dtt_r_data = java_dtt_in0[cntr5[7:0]]; // java_dtt_in[n2 * 256 + cntr2]; wire [DTT_IN_WIDTH-1:0] java_dtt_r_data = java_dtt_in[{n5[1:0], cntr5[7:0]}]; // java_dtt_in0[cntr5[7:0]];
wire dtt_r_regen = mclt16x16_i.dtt_r_regen; wire dtt_r_regen = mclt16x16_i.dtt_r_regen;
reg dtt_r_dv; // SuppressThisWarning VEditor just for simulation reg dtt_r_dv; // SuppressThisWarning VEditor just for simulation
...@@ -367,7 +433,7 @@ module mclt_test_01 (); ...@@ -367,7 +433,7 @@ module mclt_test_01 ();
integer n6, cntr6, diff6, diff6a; // SuppressThisWarning VEditor : assigned in $readmem() system task integer n6, cntr6, diff6, diff6a; // SuppressThisWarning VEditor : assigned in $readmem() system task
wire [DTT_IN_WIDTH-1:0] data_dtt_out = mclt16x16_i.dtt_rd_data; wire [DTT_IN_WIDTH-1:0] data_dtt_out = mclt16x16_i.dtt_rd_data;
// wire [DTT_IN_WIDTH-1:0] java_data_dtt_out = java_dtt_out0[{cntr6[1:0],cntr6[7:2]}]; // java_dtt_in[n2 * 256 + cntr2]; // wire [DTT_IN_WIDTH-1:0] java_data_dtt_out = java_dtt_out0[{cntr6[1:0],cntr6[7:2]}]; // java_dtt_in[n2 * 256 + cntr2];
wire [DTT_IN_WIDTH-1:0] java_data_dtt_out = java_dtt_out0[{cntr6[0],cntr6[1],cntr6[7:2]}]; // java_dtt_in[n2 * 256 + cntr2]; wire [DTT_IN_WIDTH-1:0] java_data_dtt_out = java_dtt_out[{n6[1:0], cntr6[0],cntr6[1], cntr6[7:2]}]; //java_dtt_out0[{cntr6[0],cntr6[1],cntr6[7:2]}];
initial begin initial begin
while (RST) @(negedge CLK); while (RST) @(negedge CLK);
for (n6 = 0; n6 < 4; n6 = n6+1) begin for (n6 = 0; n6 < 4; n6 = n6+1) begin
...@@ -387,7 +453,7 @@ module mclt_test_01 (); ...@@ -387,7 +453,7 @@ module mclt_test_01 ();
always @(posedge CLK) FIRST_OUT <= mclt16x16_i.pre_first_out; always @(posedge CLK) FIRST_OUT <= mclt16x16_i.pre_first_out;
integer n7, cntr7, diff7, diff7a; // SuppressThisWarning VEditor : assigned in $readmem() system task integer n7, cntr7, diff7, diff7a; // SuppressThisWarning VEditor : assigned in $readmem() system task
wire [OUT_WIDTH-1:0] java_data_dtt_rot = java_dtt_rot0[{cntr7[1],cntr7[0],cntr7[7:2]}]; // java_dtt_in[n2 * 256 + cntr2]; wire [OUT_WIDTH-1:0] java_data_dtt_rot = java_dtt_rot[{n7[1:0], cntr7[1],cntr7[0],cntr7[7:2]}]; //java_dtt_rot0[{cntr7[1],cntr7[0],cntr7[7:2]}];
initial begin initial begin
while (RST) @(negedge CLK); while (RST) @(negedge CLK);
for (n7 = 0; n7 < 4; n7 = n7+1) begin for (n7 = 0; n7 < 4; n7 = n7+1) begin
......
mclt_test_01.sav
View file @ f69ec863
[*] [*]
[*] GTKWave Analyzer v3.3.78 (w)1999-2016 BSI [*] GTKWave Analyzer v3.3.78 (w)1999-2016 BSI
[*] Wed Dec 20 18:03:31 2017 [*] Thu Dec 21 01:31:38 2017
[*] [*]
[dumpfile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/simulation/mclt_test_01-20171220105946700.fst" [dumpfile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/simulation/mclt_test_01-20171220181811365.fst"
[dumpfile_mtime] "Wed Dec 20 17:59:49 2017" [dumpfile_mtime] "Thu Dec 21 01:18:14 2017"
[dumpfile_size] 1336550 [dumpfile_size] 1057823
[savefile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/mclt_test_01.sav" [savefile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/mclt_test_01.sav"
[timestart] 0 [timestart] 13247200
[size] 1814 1171 [size] 1814 1171
[pos] 0 0 [pos] 0 0
*-21.371767 6140000 2715000 3535000 3355000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 *-15.481516 13285000 355000 2885000 325000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] mclt_test_01. [treeopen] mclt_test_01.
[treeopen] mclt_test_01.mclt16x16_i. [treeopen] mclt_test_01.mclt16x16_i.
[treeopen] mclt_test_01.mclt16x16_i.dtt_iv_8x8_ad_i.dct_iv8_1d_pass1_0_i. [treeopen] mclt_test_01.mclt16x16_i.dtt_iv_8x8_ad_i.dct_iv8_1d_pass1_0_i.
[treeopen] mclt_test_01.mclt16x16_i.dtt_iv_8x8_ad_i.dct_iv8_1d_pass2_0_i. [treeopen] mclt_test_01.mclt16x16_i.dtt_iv_8x8_ad_i.dct_iv8_1d_pass2_0_i.
[treeopen] mclt_test_01.mclt16x16_i.mclt_wnd_i.
[treeopen] mclt_test_01.mclt16x16_i.mclt_wnd_i.i_wnd_rom.
[treeopen] mclt_test_01.mclt16x16_i.mclt_wnd_i.mclt_full_shift_x_i.
[treeopen] mclt_test_01.mclt16x16_i.phase_rotator_i. [treeopen] mclt_test_01.mclt16x16_i.phase_rotator_i.
[treeopen] mclt_test_01.mclt16x16_i.phase_rotator_i.dsp_2_i. [treeopen] mclt_test_01.mclt16x16_i.phase_rotator_i.dsp_2_i.
[treeopen] mclt_test_01.mclt16x16_i.phase_rotator_i.dsp_2_i.DSP48E1_i. [treeopen] mclt_test_01.mclt16x16_i.phase_rotator_i.dsp_2_i.DSP48E1_i.
[sst_width] 204 [sst_width] 210
[signals_width] 341 [signals_width] 281
[sst_expanded] 1 [sst_expanded] 1
[sst_vpaned_height] 344 [sst_vpaned_height] 344
@800200 @800200
...@@ -65,8 +68,15 @@ mclt_test_01.cntr2 ...@@ -65,8 +68,15 @@ mclt_test_01.cntr2
[color] 6 [color] 6
mclt_test_01.window_r[17:0] mclt_test_01.window_r[17:0]
mclt_test_01.java_window_w[17:0] mclt_test_01.java_window_w[17:0]
@8420
[color] 6
mclt_test_01.window_r[17:0]
mclt_test_01.java_window_w[17:0]
@420 @420
mclt_test_01.diff2 mclt_test_01.diff2
@8420
mclt_test_01.diff2
@420
mclt_test_01.diff2a mclt_test_01.diff2a
@8420 @8420
[color] 2 [color] 2
...@@ -89,9 +99,76 @@ mclt_test_01.java_sgn_w[3:0] ...@@ -89,9 +99,76 @@ mclt_test_01.java_sgn_w[3:0]
[color] 2 [color] 2
mclt_test_01.diff3 mclt_test_01.diff3
mclt_test_01.n4 mclt_test_01.n4
@24 @c00024
[color] 3 [color] 3
mclt_test_01.cntr4 mclt_test_01.cntr4
@28
[color] 3
(0)mclt_test_01.cntr4
[color] 3
(1)mclt_test_01.cntr4
[color] 3
(2)mclt_test_01.cntr4
[color] 3
(3)mclt_test_01.cntr4
[color] 3
(4)mclt_test_01.cntr4
[color] 3
(5)mclt_test_01.cntr4
[color] 3
(6)mclt_test_01.cntr4
[color] 3
(7)mclt_test_01.cntr4
[color] 3
(8)mclt_test_01.cntr4
[color] 3
(9)mclt_test_01.cntr4
[color] 3
(10)mclt_test_01.cntr4
[color] 3
(11)mclt_test_01.cntr4
[color] 3
(12)mclt_test_01.cntr4
[color] 3
(13)mclt_test_01.cntr4
[color] 3
(14)mclt_test_01.cntr4
[color] 3
(15)mclt_test_01.cntr4
[color] 3
(16)mclt_test_01.cntr4
[color] 3
(17)mclt_test_01.cntr4
[color] 3
(18)mclt_test_01.cntr4
[color] 3
(19)mclt_test_01.cntr4
[color] 3
(20)mclt_test_01.cntr4
[color] 3
(21)mclt_test_01.cntr4
[color] 3
(22)mclt_test_01.cntr4
[color] 3
(23)mclt_test_01.cntr4
[color] 3
(24)mclt_test_01.cntr4
[color] 3
(25)mclt_test_01.cntr4
[color] 3
(26)mclt_test_01.cntr4
[color] 3
(27)mclt_test_01.cntr4
[color] 3
(28)mclt_test_01.cntr4
[color] 3
(29)mclt_test_01.cntr4
[color] 3
(30)mclt_test_01.cntr4
[color] 3
(31)mclt_test_01.cntr4
@1401200
-group_end
@22 @22
[color] 6 [color] 6
mclt_test_01.data_dtt_in[24:0] mclt_test_01.data_dtt_in[24:0]
...@@ -101,6 +178,9 @@ mclt_test_01.data_dtt_in[24:0] ...@@ -101,6 +178,9 @@ mclt_test_01.data_dtt_in[24:0]
mclt_test_01.java_data_dtt_in[24:0] mclt_test_01.java_data_dtt_in[24:0]
@420 @420
mclt_test_01.diff4 mclt_test_01.diff4
@8420
mclt_test_01.diff4
@420
mclt_test_01.diff4a mclt_test_01.diff4a
@8420 @8420
mclt_test_01.diff4a mclt_test_01.diff4a
...@@ -151,12 +231,124 @@ mclt_test_01.java_data_dtt_rot[24:0] ...@@ -151,12 +231,124 @@ mclt_test_01.java_data_dtt_rot[24:0]
@8420 @8420
mclt_test_01.dout[24:0] mclt_test_01.dout[24:0]
mclt_test_01.java_data_dtt_rot[24:0] mclt_test_01.java_data_dtt_rot[24:0]
@8421
mclt_test_01.diff7 mclt_test_01.diff7
mclt_test_01.diff7a mclt_test_01.diff7a
@1000200 @1000200
-top -top
@800200 @800200
-dtt_out
@23
mclt_test_01.mclt16x16_i.dtt_rd_data[24:0]
@22
mclt_test_01.mclt16x16_i.dtt_rd_data_w[35:0]
@200
-
@1000200
-dtt_out
@c00200
-mclt_wnd_mul
@28
mclt_test_01.mclt16x16_i.mclt_wnd_i.en
@22
mclt_test_01.mclt16x16_i.mclt_wnd_i.x_shft[6:0]
mclt_test_01.mclt16x16_i.mclt_wnd_i.y_shft[6:0]
mclt_test_01.mclt16x16_i.mclt_wnd_i.x_in[3:0]
mclt_test_01.mclt16x16_i.mclt_wnd_i.y_in[3:0]
mclt_test_01.mclt16x16_i.mclt_wnd_i.x_full[9:0]
@28
mclt_test_01.mclt16x16_i.mclt_wnd_i.x_zero
@22
mclt_test_01.mclt16x16_i.mclt_wnd_i.y_full[9:0]
@28
mclt_test_01.mclt16x16_i.mclt_wnd_i.zero
@c00022
mclt_test_01.mclt16x16_i.mclt_wnd_i.regen[2:0]
@28
(0)mclt_test_01.mclt16x16_i.mclt_wnd_i.regen[2:0]
(1)mclt_test_01.mclt16x16_i.mclt_wnd_i.regen[2:0]
(2)mclt_test_01.mclt16x16_i.mclt_wnd_i.regen[2:0]
@1401200
-group_end
@c00022
mclt_test_01.mclt16x16_i.mclt_wnd_i.wnd_out_x[17:0]
@28
(0)mclt_test_01.mclt16x16_i.mclt_wnd_i.wnd_out_x[17:0]
(1)mclt_test_01.mclt16x16_i.mclt_wnd_i.wnd_out_x[17:0]
(2)mclt_test_01.mclt16x16_i.mclt_wnd_i.wnd_out_x[17:0]
(3)mclt_test_01.mclt16x16_i.mclt_wnd_i.wnd_out_x[17:0]
(4)mclt_test_01.mclt16x16_i.mclt_wnd_i.wnd_out_x[17:0]
(5)mclt_test_01.mclt16x16_i.mclt_wnd_i.wnd_out_x[17:0]
(6)mclt_test_01.mclt16x16_i.mclt_wnd_i.wnd_out_x[17:0]
(7)mclt_test_01.mclt16x16_i.mclt_wnd_i.wnd_out_x[17:0]
(8)mclt_test_01.mclt16x16_i.mclt_wnd_i.wnd_out_x[17:0]
(9)mclt_test_01.mclt16x16_i.mclt_wnd_i.wnd_out_x[17:0]
(10)mclt_test_01.mclt16x16_i.mclt_wnd_i.wnd_out_x[17:0]
(11)mclt_test_01.mclt16x16_i.mclt_wnd_i.wnd_out_x[17:0]
(12)mclt_test_01.mclt16x16_i.mclt_wnd_i.wnd_out_x[17:0]
(13)mclt_test_01.mclt16x16_i.mclt_wnd_i.wnd_out_x[17:0]
(14)mclt_test_01.mclt16x16_i.mclt_wnd_i.wnd_out_x[17:0]
(15)mclt_test_01.mclt16x16_i.mclt_wnd_i.wnd_out_x[17:0]
(16)mclt_test_01.mclt16x16_i.mclt_wnd_i.wnd_out_x[17:0]
(17)mclt_test_01.mclt16x16_i.mclt_wnd_i.wnd_out_x[17:0]
@1401200
-group_end
@22
mclt_test_01.mclt16x16_i.mclt_wnd_i.wnd_out_y[17:0]
mclt_test_01.mclt16x16_i.mclt_wnd_i.wnd_out[17:0]
@800200
-wnd_rom
@22
mclt_test_01.mclt16x16_i.mclt_wnd_i.i_wnd_rom.addr_a[9:0]
@28
mclt_test_01.mclt16x16_i.mclt_wnd_i.i_wnd_rom.en_a
mclt_test_01.mclt16x16_i.mclt_wnd_i.i_wnd_rom.regen_a
mclt_test_01.mclt16x16_i.mclt_wnd_i.i_wnd_rom.regrst_a
@22
mclt_test_01.mclt16x16_i.mclt_wnd_i.i_wnd_rom.data_out_a[17:0]
@28
mclt_test_01.mclt16x16_i.mclt_wnd_i.i_wnd_rom.regrst_b
@22
mclt_test_01.mclt16x16_i.mclt_wnd_i.i_wnd_rom.data_out_b[17:0]
mclt_test_01.mclt16x16_i.mclt_wnd_i.wnd_out_x_r[17:0]
mclt_test_01.mclt16x16_i.mclt_wnd_i.wnd_out_y_r[17:0]
mclt_test_01.mclt16x16_i.mclt_wnd_i.wnd_out_full[35:0]
mclt_test_01.mclt16x16_i.mclt_wnd_i.wnd_out_w[17:0]
mclt_test_01.mclt16x16_i.mclt_wnd_i.wnd_out_r[17:0]
@200
-
@1000200
-wnd_rom
@800200
-mclt_full_shift_x
@22
mclt_test_01.mclt16x16_i.mclt_wnd_i.mclt_full_shift_x_i.coord[3:0]
mclt_test_01.mclt16x16_i.mclt_wnd_i.mclt_full_shift_x_i.shift[6:0]
mclt_test_01.mclt16x16_i.mclt_wnd_i.mclt_full_shift_x_i.mod_coord_w[11:0]
mclt_test_01.mclt16x16_i.mclt_wnd_i.mclt_full_shift_x_i.mod_coord_r[11:0]
mclt_test_01.mclt16x16_i.mclt_wnd_i.mclt_full_shift_x_i.coord_out[9:0]
@28
mclt_test_01.mclt16x16_i.mclt_wnd_i.mclt_full_shift_x_i.zero
@200
-
@1000200
-mclt_full_shift_x
@800200
-mult_full_shift_y
@22
mclt_test_01.mclt16x16_i.mclt_wnd_i.mclt_full_shift_y_i.coord[3:0]
mclt_test_01.mclt16x16_i.mclt_wnd_i.mclt_full_shift_y_i.shift[6:0]
mclt_test_01.mclt16x16_i.mclt_wnd_i.mclt_full_shift_y_i.mod_coord_w[11:0]
mclt_test_01.mclt16x16_i.mclt_wnd_i.mclt_full_shift_y_i.mod_coord_r[11:0]
mclt_test_01.mclt16x16_i.mclt_wnd_i.mclt_full_shift_y_i.coord_out[9:0]
@28
mclt_test_01.mclt16x16_i.mclt_wnd_i.mclt_full_shift_y_i.zero
@200
-
@1000200
-mult_full_shift_y
@1401200
-mclt_wnd_mul
@800200
-rotator -rotator
@c00200 @c00200
-main -main
...@@ -548,82 +740,6 @@ mclt_test_01.mclt16x16_i.i_mclt_fold_rom.data_out_a[17:0] ...@@ -548,82 +740,6 @@ mclt_test_01.mclt16x16_i.i_mclt_fold_rom.data_out_a[17:0]
- -
@1401200 @1401200
-fold_rom -fold_rom
@800200
-mclt_wnd_mul
@28
mclt_test_01.mclt16x16_i.mclt_wnd_i.en
@22
mclt_test_01.mclt16x16_i.mclt_wnd_i.x_shft[6:0]
mclt_test_01.mclt16x16_i.mclt_wnd_i.y_shft[6:0]
mclt_test_01.mclt16x16_i.mclt_wnd_i.x_in[3:0]
mclt_test_01.mclt16x16_i.mclt_wnd_i.y_in[3:0]
mclt_test_01.mclt16x16_i.mclt_wnd_i.x_full[9:0]
@28
mclt_test_01.mclt16x16_i.mclt_wnd_i.x_zero
@22
mclt_test_01.mclt16x16_i.mclt_wnd_i.y_full[9:0]
@28
mclt_test_01.mclt16x16_i.mclt_wnd_i.zero
@c00022
mclt_test_01.mclt16x16_i.mclt_wnd_i.regen[2:0]
@28
(0)mclt_test_01.mclt16x16_i.mclt_wnd_i.regen[2:0]
(1)mclt_test_01.mclt16x16_i.mclt_wnd_i.regen[2:0]
(2)mclt_test_01.mclt16x16_i.mclt_wnd_i.regen[2:0]
@1401200
-group_end
@c00022
mclt_test_01.mclt16x16_i.mclt_wnd_i.wnd_out_x[17:0]
@28
(0)mclt_test_01.mclt16x16_i.mclt_wnd_i.wnd_out_x[17:0]
(1)mclt_test_01.mclt16x16_i.mclt_wnd_i.wnd_out_x[17:0]
(2)mclt_test_01.mclt16x16_i.mclt_wnd_i.wnd_out_x[17:0]
(3)mclt_test_01.mclt16x16_i.mclt_wnd_i.wnd_out_x[17:0]
(4)mclt_test_01.mclt16x16_i.mclt_wnd_i.wnd_out_x[17:0]
(5)mclt_test_01.mclt16x16_i.mclt_wnd_i.wnd_out_x[17:0]
(6)mclt_test_01.mclt16x16_i.mclt_wnd_i.wnd_out_x[17:0]
(7)mclt_test_01.mclt16x16_i.mclt_wnd_i.wnd_out_x[17:0]
(8)mclt_test_01.mclt16x16_i.mclt_wnd_i.wnd_out_x[17:0]
(9)mclt_test_01.mclt16x16_i.mclt_wnd_i.wnd_out_x[17:0]
(10)mclt_test_01.mclt16x16_i.mclt_wnd_i.wnd_out_x[17:0]
(11)mclt_test_01.mclt16x16_i.mclt_wnd_i.wnd_out_x[17:0]
(12)mclt_test_01.mclt16x16_i.mclt_wnd_i.wnd_out_x[17:0]
(13)mclt_test_01.mclt16x16_i.mclt_wnd_i.wnd_out_x[17:0]
(14)mclt_test_01.mclt16x16_i.mclt_wnd_i.wnd_out_x[17:0]
(15)mclt_test_01.mclt16x16_i.mclt_wnd_i.wnd_out_x[17:0]
(16)mclt_test_01.mclt16x16_i.mclt_wnd_i.wnd_out_x[17:0]
(17)mclt_test_01.mclt16x16_i.mclt_wnd_i.wnd_out_x[17:0]
@1401200
-group_end
@22
mclt_test_01.mclt16x16_i.mclt_wnd_i.wnd_out_y[17:0]
mclt_test_01.mclt16x16_i.mclt_wnd_i.wnd_out[17:0]
@c00200
-wnd_rom
@22
mclt_test_01.mclt16x16_i.mclt_wnd_i.i_wnd_rom.addr_a[9:0]
@28
mclt_test_01.mclt16x16_i.mclt_wnd_i.i_wnd_rom.en_a
mclt_test_01.mclt16x16_i.mclt_wnd_i.i_wnd_rom.regen_a
mclt_test_01.mclt16x16_i.mclt_wnd_i.i_wnd_rom.regrst_a
@200
-
@1401200
-wnd_rom
@c00200
-mclt_full_shift_x
@22
mclt_test_01.mclt16x16_i.mclt_wnd_i.mclt_full_shift_x_i.coord[3:0]
mclt_test_01.mclt16x16_i.mclt_wnd_i.mclt_full_shift_x_i.shift[6:0]
mclt_test_01.mclt16x16_i.mclt_wnd_i.mclt_full_shift_x_i.mod_coord_w[11:0]
mclt_test_01.mclt16x16_i.mclt_wnd_i.mclt_full_shift_x_i.mod_coord_r[11:0]
mclt_test_01.mclt16x16_i.mclt_wnd_i.mclt_full_shift_x_i.coord_out[9:0]
@200
-
@1401200
-mclt_full_shift_x
@1000200
-mclt_wnd_mul
@c08022 @c08022
mclt_test_01.mclt16x16_i.window_r[17:0] mclt_test_01.mclt16x16_i.window_r[17:0]
@28 @28
......
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