Commit f5cc4edf authored by Andrey Filippov's avatar Andrey Filippov

Compared through all srages, including phase rotator/fractional pixel

shift
parent 63d2b1b1
......@@ -383,6 +383,26 @@ module mclt_test_01 ();
end
end
reg FIRST_OUT;
always @(posedge CLK) FIRST_OUT <= mclt16x16_i.pre_first_out;
integer n7, cntr7, diff7, diff7a; // SuppressThisWarning VEditor : assigned in $readmem() system task
wire [OUT_WIDTH-1:0] java_data_dtt_rot = java_dtt_rot0[{cntr7[1],cntr7[0],cntr7[7:2]}]; // java_dtt_in[n2 * 256 + cntr2];
initial begin
while (RST) @(negedge CLK);
for (n7 = 0; n7 < 4; n7 = n7+1) begin
while (!FIRST_OUT) begin
@(negedge CLK);
end
for (cntr7 = 0; cntr7 < 256; cntr7 = cntr7 + 1) begin
#1;
diff7 = dout - java_data_dtt_rot;
if (n7 < 1) diff7a = dout - java_data_dtt_rot; // TEMPORARY, while no other data
@(negedge CLK);
end
end
end
mclt16x16 #(
......
......@@ -117,9 +117,6 @@ module phase_rotator#(
if (!run_h) cntr_h <= 0;
else cntr_h <= cntr_h + 1;
// if (!run_hv) hv_phase <= 0;
// else hv_phase <= hv_phase + 1;
// combine horizontal and vertical counters and shifts to feed to ROM
hv_index <= mux_v ? cntr_v[4:2] : cntr_h[7:5]; // input data "down first" (transposed)
hv_sin <= mux_v ? cntr_v[0] : cntr_h[0];
......@@ -131,8 +128,6 @@ module phase_rotator#(
rom_a_shift <= shift_hv[SHIFT_WIDTH-1] ? -shift_hv[SHIFT_WIDTH-2:0] : shift_hv[SHIFT_WIDTH-2:0];
rom_a_sin <= shift_ends_0 ? shift_hv[SHIFT_WIDTH-1] : hv_sin;
// sign_cs <= shift_hv[SHIFT_WIDTH-1] & ( hv_sin | (shift_ends_0 & hv_index[2]));
// sign_cs <= shift_hv[SHIFT_WIDTH-1] & hv_sin;
sign_cs <= {sign_cs[3:0], shift_hv[SHIFT_WIDTH-1] & hv_sin};
rom_re_regen <= {rom_re_regen[1:0],run_hv};
......@@ -212,7 +207,6 @@ module phase_rotator#(
always @(posedge clk) begin
if (rst) ph <= 0;
// else ph <= {ph[15:0], run_h & ~cntr_h[0] & cntr_h[1]};
else ph <= {ph[15:0], run_h & ~cntr_h[0] & ~cntr_h[1]};
cea1_1 <= ph[0]; cea2_1 <= ph[2]; cea1_2 <= ph[1]; cea2_2 <= ph[3];
ceb1_1 <= ph[3]; ceb2_1 <= ph[2]; ceb1_2 <= ph[2] | ph[3]; ceb2_2 <= ph[3];
......@@ -221,10 +215,6 @@ module phase_rotator#(
sela_1 <= ph[2] | ph[4]; sela_2 <= ph[3] | ph[5];
selb_1 <= ph[2] | ph[5]; selb_2 <= ph[3] | ph[6];
// 0 1 0 0
// negm_1 <= (ph[3] ^ sign_cs_d) | (~ph[4] ^ sign_cs_d) | (ph[5] ^ sign_cs_r[1]) | (ph[6] ^ sign_cs_r[1]);
// negm_2 <= (ph[4] ^ sign_cs_d) | (~ph[5] ^ sign_cs_d) | (ph[6] ^ sign_cs_r[1]) | (ph[7] ^ sign_cs_r[1]);
/// negm_1 <= (ph[4] & ~sign_cs[0]) | (ph[5] & sign_cs[1]);
/// negm_2 <= (ph[5] & ~sign_cs[1]) | (ph[6] & sign_cs[2]);
negm_1 <= (ph[4] & ~sign_cs[2]) | (ph[5] & sign_cs[3]);
negm_2 <= (ph[5] & ~sign_cs[3]) | (ph[6] & sign_cs[4]);
......@@ -237,10 +227,6 @@ module phase_rotator#(
end_3 <= ph[10] | ph[8]; end_4 <= ph[11] | ph[9];
selb_3 <= ph[8] | ph[11]; selb_4 <= ph[9] | ph[12];
// negm_4 <= (ph[ 9] ^ sign_cs_d) | (~ph[10] ^ sign_cs_d) | (ph[11] ^ sign_cs_r[1]) | (ph[12] ^ sign_cs_r[1]);
// negm_3 <= (ph[10] ^ sign_cs_d) | (~ph[11] ^ sign_cs_d) | (ph[12] ^ sign_cs_r[1]) | (ph[13] ^ sign_cs_r[1]);
/// negm_3 <= (ph[10] & ~sign_cs[0]) | (ph[11] & sign_cs[1]);
/// negm_4 <= (ph[11] & ~sign_cs[1]) | (ph[12] & sign_cs[2]);
negm_3 <= (ph[10] & ~sign_cs[2]) | (ph[11] & sign_cs[3]);
negm_4 <= (ph[11] & ~sign_cs[3]) | (ph[12] & sign_cs[4]);
......@@ -250,15 +236,10 @@ module phase_rotator#(
fd_dv <= pre_dv;
if (pre_dv) fd_out <= omux_sel ? pout_4[COEFF_WIDTH +: DSP_A_WIDTH] : pout_3[COEFF_WIDTH +: DSP_A_WIDTH];
// pre_first_out <= ph[12];
pre_first_out <= cntr_h[7:0] == 8'hf;
pre_first_out <= cntr_h[7:0] == 8'hd;
end
/*
output reg signed [FD_WIDTH-1:0] fd_out, //!< frequency domain data in
*/
// horizontal shift stage
dsp_ma_preadd #(
......
[*]
[*] GTKWave Analyzer v3.3.78 (w)1999-2016 BSI
[*] Wed Dec 20 07:04:05 2017
[*] Wed Dec 20 18:03:31 2017
[*]
[dumpfile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/simulation/mclt_test_01-20171219235955852.fst"
[dumpfile_mtime] "Wed Dec 20 06:59:58 2017"
[dumpfile_size] 1334335
[dumpfile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/simulation/mclt_test_01-20171220105946700.fst"
[dumpfile_mtime] "Wed Dec 20 17:59:49 2017"
[dumpfile_size] 1336550
[savefile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/mclt_test_01.sav"
[timestart] 5698200
[timestart] 0
[size] 1814 1171
[pos] 0 0
*-14.519981 5777900 2715000 3535000 3355000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
*-21.371767 6140000 2715000 3535000 3355000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] mclt_test_01.
[treeopen] mclt_test_01.mclt16x16_i.
[treeopen] mclt_test_01.mclt16x16_i.dtt_iv_8x8_ad_i.dct_iv8_1d_pass1_0_i.
......@@ -142,6 +142,18 @@ mclt_test_01.data_dtt_out[24:0]
mclt_test_01.java_data_dtt_out[24:0]
mclt_test_01.diff6
mclt_test_01.diff6a
@420
mclt_test_01.n7
mclt_test_01.cntr7
@22
mclt_test_01.dout[24:0]
mclt_test_01.java_data_dtt_rot[24:0]
@8420
mclt_test_01.dout[24:0]
mclt_test_01.java_data_dtt_rot[24:0]
@8421
mclt_test_01.diff7
mclt_test_01.diff7a
@1000200
-top
@800200
......@@ -289,17 +301,17 @@ mclt_test_01.mclt16x16_i.phase_rotator_i.din_34[24:0]
mclt_test_01.mclt16x16_i.phase_rotator_i.pout_3[47:0]
mclt_test_01.mclt16x16_i.phase_rotator_i.pout_4[47:0]
@28
mclt_test_01.mclt16x16_i.phase_rotator_i.pre_first_out
mclt_test_01.mclt16x16_i.phase_rotator_i.fd_dv
@22
[color] 6
mclt_test_01.mclt16x16_i.phase_rotator_i.fd_out[24:0]
@800200
-dsps
@22
[color] 3
mclt_test_01.mclt16x16_i.phase_rotator_i.fd_out[24:0]
@28
mclt_test_01.mclt16x16_i.phase_rotator_i.pre_first_out
mclt_test_01.mclt16x16_i.phase_rotator_i.fd_dv
mclt_test_01.mclt16x16_i.phase_rotator_i.pre_dv
@22
mclt_test_01.mclt16x16_i.phase_rotator_i.cntr_h[7:0]
@c00200
-dsps
@c00022
mclt_test_01.mclt16x16_i.phase_rotator_i.ph[16:0]
@28
......@@ -383,15 +395,8 @@ mclt_test_01.mclt16x16_i.phase_rotator_i.selb_3
mclt_test_01.mclt16x16_i.phase_rotator_i.hv_sin
@22
mclt_test_01.mclt16x16_i.phase_rotator_i.shift_hv[6:0]
@800022
mclt_test_01.mclt16x16_i.phase_rotator_i.sign_cs[5:0]
@28
(0)mclt_test_01.mclt16x16_i.phase_rotator_i.sign_cs[5:0]
(1)mclt_test_01.mclt16x16_i.phase_rotator_i.sign_cs[5:0]
(2)mclt_test_01.mclt16x16_i.phase_rotator_i.sign_cs[5:0]
(3)mclt_test_01.mclt16x16_i.phase_rotator_i.sign_cs[5:0]
(4)mclt_test_01.mclt16x16_i.phase_rotator_i.sign_cs[5:0]
(5)mclt_test_01.mclt16x16_i.phase_rotator_i.sign_cs[5:0]
@800200
-mclt_test_01.mclt16x16_i.phase_rotator_i.sign_cs
@1001200
-group_end
@28
......@@ -447,9 +452,11 @@ mclt_test_01.mclt16x16_i.phase_rotator_i.dsp_2_i.DSP48E1_i.qb_o_reg2[17:0]
-dsp48
@1401200
-dsp2
@1000200
-dsps
@1000200
-rotator
@22
mclt_test_01.mclt16x16_i.out_addr[7:0]
@800200
-mclt16x16
@c00022
......
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