Commit f3df44ab authored by Alexey Grebenkin's avatar Alexey Grebenkin
Browse files

Simulator-dependent defines added

parent dc5c25e2

system_defines.vh

+12 −0
Original line number Original line Diff line number Diff line 
  // This file may be used to define same pre-processor macros to be included into each parsed file

  // This file may be used to define same pre-processor macros to be included into each parsed file

`ifndef SYSTEM_DEFINES

`ifndef SYSTEM_DEFINES

  `define SYSTEM_DEFINES

  `define SYSTEM_DEFINES



// Enviroment-dependent options

  `ifdef IVERILOG

    `define SIMULATION

    `define OPEN_SOURCE_ONLY

  `else

  `ifdef CVC

    `define SIMULATION

    `define OPEN_SOURCE_ONLY

  `endif // CVC

  `endif // IVERILOG



//`define MEMBRIDGE_DEBUG_READ 1

//`define MEMBRIDGE_DEBUG_READ 1

  `define use200Mhz 1

  `define use200Mhz 1

  `define USE_CMD_ENCOD_TILED_32_RD 1  

  `define USE_CMD_ENCOD_TILED_32_RD 1

wrap/idelay_fine_pipe.v

+2 −8
Original line number Original line Diff line number Diff line
@@ -43,17 +43,11 @@ module idelay_fine_pipe 
        if (rst)      fdly <= DELAY_VALUE[2:0];

        if (rst)      fdly <= DELAY_VALUE[2:0];

        else if (set) fdly <= fdly_pre;

        else if (set) fdly <= fdly_pre;

    end

    end

    `ifdef IVERILOG

    `ifdef SIMULATION

        always @ (fdly_pre) begin

        always @ (fdly_pre) begin

            if (fdly_pre > 3'h4) $display ("ERROR: fine idelay value should be <5, specified %d @ %t", fdly_pre,$time);  

            if (fdly_pre > 3'h4) $display ("ERROR: fine idelay value should be <5, specified %d @ %t", fdly_pre,$time);  

        end

        end

    `else // IVERILOG

    `endif // SIMULATION

    `ifdef CVC

        always @ (fdly_pre) begin

            if (fdly_pre > 3'h4) $display ("ERROR: fine idelay value should be <5, specified %d @ %t", fdly_pre,$time);  

        end

    `endif //CVC

    `endif //IVERILOG

`ifndef IGNORE_ATTR

`ifndef IGNORE_ATTR

  (* IODELAY_GROUP = IODELAY_GRP *) 

  (* IODELAY_GROUP = IODELAY_GRP *) 

`endif

`endif

wrap/iserdes_mem.v

+1 −8
Original line number Original line Diff line number Diff line
@@ -20,13 +20,6 @@ 
 *******************************************************************************/

 *******************************************************************************/

`timescale 1ns/1ps

`timescale 1ns/1ps

//`define IVERILOG // uncomment just to chenck syntax (by the editor) in the corresponding branch

//`define IVERILOG // uncomment just to chenck syntax (by the editor) in the corresponding branch

`ifdef IVERILOG

    `define IVERILOGorCVC

`else

`ifdef CVC

    `define IVERILOGorCVC

`endif

`endif

module  iserdes_mem #

module  iserdes_mem #

(

(

    parameter DYN_CLKDIV_INV_EN="FALSE",

    parameter DYN_CLKDIV_INV_EN="FALSE",
@@ -42,7 +35,7 @@ module iserdes_mem # 
    output [3:0] dout

    output [3:0] dout

);

);





`ifndef IVERILOGorCVC  // Not using simulator - instantiate actual ISERDESE2 (can not be simulated because of encrypted )           

`ifndef OPEN_SOURCE_ONLY  // Not using simulator - instantiate actual ISERDESE2 (can not be simulated because of encrypted )           

     ISERDESE2 #(

     ISERDESE2 #(

         .DATA_RATE                  ("DDR"),

         .DATA_RATE                  ("DDR"),

         .DATA_WIDTH                 (4),

         .DATA_WIDTH                 (4),

wrap/odelay_fine_pipe.v

+2 −8
Original line number Original line Diff line number Diff line
@@ -42,17 +42,11 @@ module odelay_fine_pipe 
        if (rst)      fdly <= DELAY_VALUE[2:0];

        if (rst)      fdly <= DELAY_VALUE[2:0];

        else if (set) fdly <= fdly_pre;

        else if (set) fdly <= fdly_pre;

    end

    end

    `ifdef IVERILOG

    `ifdef SIMULATION

        always @ (fdly_pre) begin

        always @ (fdly_pre) begin

            if (fdly_pre > 3'h4) $display ("ERROR: fine odelay value should be <5, specified %d @ %t", fdly_pre,$time);  

            if (fdly_pre > 3'h4) $display ("ERROR: fine odelay value should be <5, specified %d @ %t", fdly_pre,$time);  

        end

        end

    `else // IVERILOG

    `endif // SIMULATION

    `ifdef CVC

        always @ (fdly_pre) begin

            if (fdly_pre > 3'h4) $display ("ERROR: fine odelay value should be <5, specified %d @ %t", fdly_pre,$time);  

        end

    `endif // CVC

    `endif // IVERILOG

 

 

`ifndef IGNORE_ATTR

`ifndef IGNORE_ATTR

  (* IODELAY_GROUP = IODELAY_GRP *) 

  (* IODELAY_GROUP = IODELAY_GRP *)

wrap/oserdes_mem.v

+1 −8
Original line number Original line Diff line number Diff line
@@ -20,13 +20,6 @@ 
 *******************************************************************************/

 *******************************************************************************/

`timescale 1ns/1ps

`timescale 1ns/1ps

//`define IVERILOG // uncomment just to chenck syntax (by the editor) in the corresponding branch

//`define IVERILOG // uncomment just to chenck syntax (by the editor) in the corresponding branch

`ifdef IVERILOG

    `define IVERILOGorCVC

`else

`ifdef CVC

    `define IVERILOGorCVC

`endif

`endif

module  oserdes_mem #(

module  oserdes_mem #(

    parameter MODE_DDR="TRUE"

    parameter MODE_DDR="TRUE"

) (

) (
@@ -53,7 +46,7 @@ localparam integer DATA_WIDTH_TRI= (MODE_DDR=="TRUE")?4:1; 
    seems to be OK.

    seems to be OK.

*/

*/





`ifndef IVERILOGorCVC  // Not using simulator - instantiate actual ISERDESE2 (can not be simulated because of encrypted ) 

`ifndef OPEN_SOURCE_ONLY  // Not using simulator - instantiate actual ISERDESE2 (can not be simulated because of encrypted ) 

           OSERDESE2 #(

           OSERDESE2 #(

               .DATA_RATE_OQ         (DATA_RATE),

               .DATA_RATE_OQ         (DATA_RATE),

               .DATA_RATE_TQ         (DATA_RATE),

               .DATA_RATE_TQ         (DATA_RATE),