Simulator-dependent defines added

system_defines.vh

   // This file may be used to define same pre-processor macros to be included into each parsed file
 `ifndef SYSTEM_DEFINES
   `define SYSTEM_DEFINES
+
+// Enviroment-dependent options
+  `ifdef IVERILOG
+    `define SIMULATION
+    `define OPEN_SOURCE_ONLY
+  `else
+  `ifdef CVC
+    `define SIMULATION
+    `define OPEN_SOURCE_ONLY
+  `endif // CVC
+  `endif // IVERILOG
+
 //`define MEMBRIDGE_DEBUG_READ 1
   `define use200Mhz 1
   `define USE_CMD_ENCOD_TILED_32_RD 1  

wrap/idelay_fine_pipe.v

@@ -43,17 +43,11 @@ module  idelay_fine_pipe
         if (rst)      fdly <= DELAY_VALUE[2:0];
         else if (set) fdly <= fdly_pre;
     end
-    `ifdef IVERILOG
+    `ifdef SIMULATION
         always @ (fdly_pre) begin
             if (fdly_pre > 3'h4) $display ("ERROR: fine idelay value should be <5, specified %d @ %t", fdly_pre,$time);  
         end
-    `else // IVERILOG
-    `ifdef CVC
-        always @ (fdly_pre) begin
-            if (fdly_pre > 3'h4) $display ("ERROR: fine idelay value should be <5, specified %d @ %t", fdly_pre,$time);  
-        end
-    `endif //CVC
-    `endif //IVERILOG
+    `endif // SIMULATION
 `ifndef IGNORE_ATTR
   (* IODELAY_GROUP = IODELAY_GRP *) 
 `endif

wrap/iserdes_mem.v

@@ -20,13 +20,6 @@
  *******************************************************************************/
 `timescale 1ns/1ps
 //`define IVERILOG // uncomment just to chenck syntax (by the editor) in the corresponding branch
-`ifdef IVERILOG
-    `define IVERILOGorCVC
-`else
-`ifdef CVC
-    `define IVERILOGorCVC
-`endif
-`endif
 module  iserdes_mem #
 (
     parameter DYN_CLKDIV_INV_EN="FALSE",
@@ -42,7 +35,7 @@ module  iserdes_mem #
     output [3:0] dout
 );
 
-`ifndef IVERILOGorCVC  // Not using simulator - instantiate actual ISERDESE2 (can not be simulated because of encrypted )           
+`ifndef OPEN_SOURCE_ONLY  // Not using simulator - instantiate actual ISERDESE2 (can not be simulated because of encrypted )           
      ISERDESE2 #(
          .DATA_RATE                  ("DDR"),
          .DATA_WIDTH                 (4),

wrap/odelay_fine_pipe.v

@@ -42,17 +42,11 @@ module  odelay_fine_pipe
         if (rst)      fdly <= DELAY_VALUE[2:0];
         else if (set) fdly <= fdly_pre;
     end
-    `ifdef IVERILOG
+    `ifdef SIMULATION
         always @ (fdly_pre) begin
             if (fdly_pre > 3'h4) $display ("ERROR: fine odelay value should be <5, specified %d @ %t", fdly_pre,$time);  
         end
-    `else // IVERILOG
-    `ifdef CVC
-        always @ (fdly_pre) begin
-            if (fdly_pre > 3'h4) $display ("ERROR: fine odelay value should be <5, specified %d @ %t", fdly_pre,$time);  
-        end
-    `endif // CVC
-    `endif // IVERILOG
+    `endif // SIMULATION
  
 `ifndef IGNORE_ATTR
   (* IODELAY_GROUP = IODELAY_GRP *) 

wrap/oserdes_mem.v

@@ -20,13 +20,6 @@
  *******************************************************************************/
 `timescale 1ns/1ps
 //`define IVERILOG // uncomment just to chenck syntax (by the editor) in the corresponding branch
-`ifdef IVERILOG
-    `define IVERILOGorCVC
-`else
-`ifdef CVC
-    `define IVERILOGorCVC
-`endif
-`endif
 module  oserdes_mem #(
     parameter MODE_DDR="TRUE"
 ) (
@@ -53,7 +46,7 @@ localparam integer DATA_WIDTH_TRI=  (MODE_DDR=="TRUE")?4:1;
     seems to be OK.
 */
 
-`ifndef IVERILOGorCVC  // Not using simulator - instantiate actual ISERDESE2 (can not be simulated because of encrypted ) 
+`ifndef OPEN_SOURCE_ONLY  // Not using simulator - instantiate actual ISERDESE2 (can not be simulated because of encrypted ) 
            OSERDESE2 #(
                .DATA_RATE_OQ         (DATA_RATE),
                .DATA_RATE_TQ         (DATA_RATE),