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Commit f35c087d authored by Andrey Filippov's avatar Andrey Filippov
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simulating/debugging LWIR sensor FPGA code

parent 654584f3
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cocotb/x393_cocotb_lwir_04.sav
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cocotb/x393_dut.v
View file @ f35c087d
...@@ -1746,8 +1746,7 @@ simul_axi_hp_wr #( ...@@ -1746,8 +1746,7 @@ simul_axi_hp_wr #(
); );
/*
/* Instance template for module simul_lwir160x120_vospi */
wire lwir1_miso; wire lwir1_miso;
simul_lwir160x120_vospi #( simul_lwir160x120_vospi #(
.DATA_FILE ("/data_ssd/nc393/elphel393/fpga-elphel/x393/input_data/pattern_160_120_14.dat"), .DATA_FILE ("/data_ssd/nc393/elphel393/fpga-elphel/x393/input_data/pattern_160_120_14.dat"),
...@@ -1791,7 +1790,7 @@ simul_axi_hp_wr #( ...@@ -1791,7 +1790,7 @@ simul_axi_hp_wr #(
.telemetry_agc_low ( 16'd200), // input[15:0] .telemetry_agc_low ( 16'd200), // input[15:0]
.telemetry_video_format (32'haaaa5555) // input[31:0] .telemetry_video_format (32'haaaa5555) // input[31:0]
); );
*/
`ifdef LWIR `ifdef LWIR
simul_lwir160x120_vospi #( simul_lwir160x120_vospi #(
.DATA_FILE (LWIR_DATA_FILE1), .DATA_FILE (LWIR_DATA_FILE1),
...@@ -1967,9 +1966,7 @@ simul_axi_hp_wr #( ...@@ -1967,9 +1966,7 @@ simul_axi_hp_wr #(
`endif `else
simul_sensor12bits #( simul_sensor12bits #(
...@@ -2133,6 +2130,7 @@ simul_axi_hp_wr #( ...@@ -2133,6 +2130,7 @@ simul_axi_hp_wr #(
.VACT (PX4_VACT), // output .VACT (PX4_VACT), // output
.VACT1 () // output .VACT1 () // output
); );
`endif
/* /*
sim_soc_interrupts #( sim_soc_interrupts #(
.NUM_INTERRUPTS (NUM_INTERRUPTS) .NUM_INTERRUPTS (NUM_INTERRUPTS)
......
compressor_jp/cmprs_cmd_decode.v
View file @ f35c087d
...@@ -318,7 +318,7 @@ module cmprs_cmd_decode#( ...@@ -318,7 +318,7 @@ module cmprs_cmd_decode#(
if (mrst) cmprs_fmode_mclk <= 0; if (mrst) cmprs_fmode_mclk <= 0;
else if (ctrl_we_r && di_r[CMPRS_CBIT_FOCUS]) cmprs_fmode_mclk <= di_r[CMPRS_CBIT_FOCUS-1 -:CMPRS_CBIT_FOCUS_BITS]; else if (ctrl_we_r && di_r[CMPRS_CBIT_FOCUS]) cmprs_fmode_mclk <= di_r[CMPRS_CBIT_FOCUS-1 -:CMPRS_CBIT_FOCUS_BITS];
if (mrst) rows_lsb_mclk <= 4'h0f; if (mrst) rows_lsb_mclk <= 4'hf;
else if (ctrl_we_r && di_r[CMPRS_CBIT_ROWS_LSB]) rows_lsb_mclk <= di_r[CMPRS_CBIT_ROWS_LSB-1 -:CMPRS_CBIT_ROWS_LSB_BITS]; else if (ctrl_we_r && di_r[CMPRS_CBIT_ROWS_LSB]) rows_lsb_mclk <= di_r[CMPRS_CBIT_ROWS_LSB-1 -:CMPRS_CBIT_ROWS_LSB_BITS];
if (mrst) bayer_shift_mclk <= 0; if (mrst) bayer_shift_mclk <= 0;
......
compressor_jp/jp_channel.v
View file @ f35c087d
...@@ -247,7 +247,7 @@ module jp_channel#( ...@@ -247,7 +247,7 @@ module jp_channel#(
wire jp4_dc_improved; // in JP4 mode, compare DC coefficients to the same color ones wire jp4_dc_improved; // in JP4 mode, compare DC coefficients to the same color ones
// wire [ 1:0] tile_margin; // margins around 16x16 tiles (0/1/2) // wire [ 1:0] tile_margin; // margins around 16x16 tiles (0/1/2)
// wire [ 2:0] tile_shift; // tile shift from top left corner // wire [ 2:0] tile_shift; // tile shift from top left corner
wire [ 2:0] converter_type; // 0 - color18, 1 - color20, 2 - mono, 3 - jp4, 4 - jp4-diff, 7 - mono8 (not yet implemented) wire [ 2:0] converter_type; // 0 - color18, 1 - color20, 2 - mono, 3 - jp4, 4 - jp4-diff, 6 - raw, 7 - mono8 (not yet implemented)
wire scale_diff; // divide differences by 2 (to fit in 8-bit range) wire scale_diff; // divide differences by 2 (to fit in 8-bit range)
wire hdr; // second green absolute, not difference wire hdr; // second green absolute, not difference
wire subtract_dc; // subtract/restore DC components wire subtract_dc; // subtract/restore DC components
......
includes/x393_parameters.vh
View file @ f35c087d
...@@ -305,8 +305,16 @@ ...@@ -305,8 +305,16 @@
parameter MCONTR_LINTILE_ABORT_LATE = 14, // abort frame if not finished by the new frame sync (wait pending memory) parameter MCONTR_LINTILE_ABORT_LATE = 14, // abort frame if not finished by the new frame sync (wait pending memory)
parameter MCNTRL_SCANLINE_DLY_WIDTH = 12, // delay start pulse by 1..64 mclk parameter MCNTRL_SCANLINE_DLY_WIDTH = 12, // delay start pulse by 1..64 mclk
`ifdef SIMULATION
`ifdef LWIR
parameter MCNTRL_SCANLINE_DLY_DEFAULT = 100, // initial delay value for start pulse
`else
parameter MCNTRL_SCANLINE_DLY_DEFAULT = 1024, // initial delay value for start pulse
`endif
`else
parameter MCNTRL_SCANLINE_DLY_DEFAULT = 1024, // initial delay value for start pulse parameter MCNTRL_SCANLINE_DLY_DEFAULT = 1024, // initial delay value for start pulse
`endif
// Channel test module parameters // Channel test module parameters
parameter MCNTRL_TEST01_ADDR= 'h0f0, parameter MCNTRL_TEST01_ADDR= 'h0f0,
parameter MCNTRL_TEST01_MASK= 'h7f0, parameter MCNTRL_TEST01_MASK= 'h7f0,
...@@ -566,8 +574,13 @@ ...@@ -566,8 +574,13 @@
parameter VOSPI_PACKET_FIRST = 0, parameter VOSPI_PACKET_FIRST = 0,
parameter VOSPI_PACKET_LAST = 60, parameter VOSPI_PACKET_LAST = 60,
parameter VOSPI_PACKET_TTT = 20, // line number where segment number is provided parameter VOSPI_PACKET_TTT = 20, // line number where segment number is provided
parameter VOSPI_SOF_TO_HACT = 2, // clock cycles from SOF to HACT `ifdef SIMULATION
parameter VOSPI_SOF_TO_HACT = 1000, // clock cycles from SOF to HACT
parameter VOSPI_HACT_TO_HACT_EOF = 1000, // pixel clock is 480 MHz, need to slow down for memory
`else
parameter VOSPI_SOF_TO_HACT = 10, // clock cycles from SOF to HACT
parameter VOSPI_HACT_TO_HACT_EOF = 2, // minimal clock cycles from HACT to HACT or to EOF parameter VOSPI_HACT_TO_HACT_EOF = 2, // minimal clock cycles from HACT to HACT or to EOF
`endif
parameter VOSPI_MCLK_HALFDIV = 4, // divide mclk (200Hhz) to get 50 MHz, then divide by 2 and use for sensor 25MHz clock parameter VOSPI_MCLK_HALFDIV = 4, // divide mclk (200Hhz) to get 50 MHz, then divide by 2 and use for sensor 25MHz clock
//`else //`else
//sensor_fifo parameters (for parallel12) //sensor_fifo parameters (for parallel12)
...@@ -1000,8 +1013,14 @@ ...@@ -1000,8 +1013,14 @@
parameter CLKIN_PERIOD_PCLK = 42, // 24MHz parameter CLKIN_PERIOD_PCLK = 42, // 24MHz
parameter DIVCLK_DIVIDE_PCLK = 1, parameter DIVCLK_DIVIDE_PCLK = 1,
parameter CLKFBOUT_MULT_PCLK = 40, // 960 MHz parameter CLKFBOUT_MULT_PCLK = 40, // 960 MHz
parameter CLKOUT_DIV_PCLK = 48, // 20 MHz `ifdef SIMULATION
parameter CLKOUT_DIV_PCLK2X = 24, // 40 MHz parameter CLKOUT_DIV_PCLK = 2, //480 MHz // 4, // 240 MHz
parameter CLKOUT_DIV_PCLK2X = 1, //9060 MHz // 2, // 480 MHz
`else
parameter CLKOUT_DIV_PCLK = 48, // 20 MHz
parameter CLKOUT_DIV_PCLK2X = 24, // 40 MHz
`endif
`else `else
parameter CLKIN_PERIOD_PCLK = 42, // 24MHz parameter CLKIN_PERIOD_PCLK = 42, // 24MHz
parameter DIVCLK_DIVIDE_PCLK = 1, parameter DIVCLK_DIVIDE_PCLK = 1,
......
py393/x393_cmprs.py
View file @ f35c087d
...@@ -528,7 +528,7 @@ class X393Cmprs(object): ...@@ -528,7 +528,7 @@ class X393Cmprs(object):
qbank, qbank,
dc_sub, dc_sub,
cmode, cmode,
bit16, bits16,
multi_frame, multi_frame,
bayer, bayer,
focus_mode, focus_mode,
...@@ -559,7 +559,7 @@ class X393Cmprs(object): ...@@ -559,7 +559,7 @@ class X393Cmprs(object):
CMPRS_CBIT_CMODE_MONO1 = 11 - mono JPEG (not yet implemented) CMPRS_CBIT_CMODE_MONO1 = 11 - mono JPEG (not yet implemented)
CMPRS_CBIT_CMODE_MONO4 = 14 - mono 4 blocks CMPRS_CBIT_CMODE_MONO4 = 14 - mono 4 blocks
CMPRS_CBIT_CMODE_RAW = 15 - raw (uncompressed) mode CMPRS_CBIT_CMODE_RAW = 15 - raw (uncompressed) mode
@param bit16 - 16-bit (2 bytes per pixel) mode @param bits16 - 16-bit (2 bytes per pixel) mode
@param multi_frame - False - single-frame buffer, True - multi-frame video memory buffer, @param multi_frame - False - single-frame buffer, True - multi-frame video memory buffer,
@param bayer - Bayer shift (0..3) @param bayer - Bayer shift (0..3)
@param focus_mode - focus mode - how to combine image with "focus quality" in the result image @param focus_mode - focus mode - how to combine image with "focus quality" in the result image
...@@ -584,13 +584,15 @@ class X393Cmprs(object): ...@@ -584,13 +584,15 @@ class X393Cmprs(object):
print ( "row_lsb_raw = ", row_lsb_raw) print ( "row_lsb_raw = ", row_lsb_raw)
self.compressor_control( self.compressor_control(
chn = chn, # compressor channel number (0..3) chn = chn, # compressor channel number (0..3)
run_mode = None, # no change
qbank = qbank, # [6:3] quantization table page qbank = qbank, # [6:3] quantization table page
dc_sub = dc_sub, # [8:7] subtract DC dc_sub = dc_sub, # [8:7] subtract DC
cmode = cmode, # [13:9] color mode: cmode = cmode, # [13:9] color mode:
multi_frame = multi_frame, # [15:14] 0 - single-frame buffer, 1 - multiframe video memory buffer multi_frame = multi_frame, # [15:14] 0 - single-frame buffer, 1 - multiframe video memory buffer
bayer = bayer, # [20:18] # Bayer shift bayer = bayer, # [20:18] # Bayer shift
focus_mode = focus_mode) # [23:21] Set focus mode focus_mode = focus_mode, # [23:21] Set focus mode
row_lsb_raw = row_lsb_raw) # [3:0] LSBs of the window height that do not fit into compressor format
self.compressor_format( self.compressor_format(
chn = chn, # compressor channel number (0..3) chn = chn, # compressor channel number (0..3)
num_macro_cols_m1 = num_macro_cols_m1, # number of macroblock colums minus 1 num_macro_cols_m1 = num_macro_cols_m1, # number of macroblock colums minus 1
......
py393/x393_sens_cmprs.py
View file @ f35c087d
...@@ -176,10 +176,11 @@ class X393SensCmprs(object): ...@@ -176,10 +176,11 @@ class X393SensCmprs(object):
SENSOR_DEFAULTS[x393_sensor.SENSOR_INTERFACE_HISPI]["height"]= vrlg.WOI_HEIGHT + 4 SENSOR_DEFAULTS[x393_sensor.SENSOR_INTERFACE_HISPI]["height"]= vrlg.WOI_HEIGHT + 4
SENSOR_DEFAULTS[x393_sensor.SENSOR_INTERFACE_HISPI]["top"]= 0 SENSOR_DEFAULTS[x393_sensor.SENSOR_INTERFACE_HISPI]["top"]= 0
SENSOR_DEFAULTS[x393_sensor.SENSOR_INTERFACE_HISPI]["left"]= 0 SENSOR_DEFAULTS[x393_sensor.SENSOR_INTERFACE_HISPI]["left"]= 0
SENSOR_DEFAULTS[x393_sensor.SENSOR_INTERFACE_LWIR]["width"]= vrlg.WOI_WIDTH #4 # keep settings from Python program
SENSOR_DEFAULTS[x393_sensor.SENSOR_INTERFACE_LWIR]["height"]= vrlg.WOI_HEIGHT #SENSOR_DEFAULTS[x393_sensor.SENSOR_INTERFACE_LWIR]["width"]= vrlg.WOI_WIDTH #4
SENSOR_DEFAULTS[x393_sensor.SENSOR_INTERFACE_LWIR]["top"]= 0 #SENSOR_DEFAULTS[x393_sensor.SENSOR_INTERFACE_LWIR]["height"]= vrlg.WOI_HEIGHT
SENSOR_DEFAULTS[x393_sensor.SENSOR_INTERFACE_LWIR]["left"]= 0 #SENSOR_DEFAULTS[x393_sensor.SENSOR_INTERFACE_LWIR]["top"]= 0
#SENSOR_DEFAULTS[x393_sensor.SENSOR_INTERFACE_LWIR]["left"]= 0
# do not update LWIR defaults !!! # do not update LWIR defaults !!!
if nomargins: if nomargins:
SENSOR_DEFAULTS[x393_sensor.SENSOR_INTERFACE_PARALLEL]["width"]= vrlg.WOI_WIDTH + 0 # 4 SENSOR_DEFAULTS[x393_sensor.SENSOR_INTERFACE_PARALLEL]["width"]= vrlg.WOI_WIDTH + 0 # 4
...@@ -526,6 +527,8 @@ class X393SensCmprs(object): ...@@ -526,6 +527,8 @@ class X393SensCmprs(object):
sensorType = self.x393Sensor.getSensorInterfaceType() sensorType = self.x393Sensor.getSensorInterfaceType()
if verbose > 0 : if verbose > 0 :
print ("Sensor port %d interface type: %s"%(num_sensor, sensorType)) print ("Sensor port %d interface type: %s"%(num_sensor, sensorType))
# print ("setup_sensor_channel(): window_width['width']=",window_width)
window = self.specify_window (window_width = window_width, window = self.specify_window (window_width = window_width,
window_height = window_height, window_height = window_height,
window_left = window_left, window_left = window_left,
...@@ -604,7 +607,7 @@ class X393SensCmprs(object): ...@@ -604,7 +607,7 @@ class X393SensCmprs(object):
histogram_start_phys_page = self.get_histogram_byte_start() // 4096 histogram_start_phys_page = self.get_histogram_byte_start() // 4096
if verbose >0 : if verbose >0 :
print ("setup_sensor_channel:") print ("setup_sensor_channel, type=",sensorType)
print ("num_sensor = ", num_sensor) print ("num_sensor = ", num_sensor)
print ("frame_full_width = ", frame_full_width) print ("frame_full_width = ", frame_full_width)
print ("window_width = ", window_width) print ("window_width = ", window_width)
...@@ -623,6 +626,7 @@ class X393SensCmprs(object): ...@@ -623,6 +626,7 @@ class X393SensCmprs(object):
print ("num_macro_cols_m1 = ", num_macro_cols_m1) print ("num_macro_cols_m1 = ", num_macro_cols_m1)
print ("num_macro_rows_m1 = ", num_macro_rows_m1) print ("num_macro_rows_m1 = ", num_macro_rows_m1)
print ("cmode = ", cmode) print ("cmode = ", cmode)
print ("bits16 = ", bits16)
print ("verbose = ", verbose) print ("verbose = ", verbose)
if exit_step == 10: return False if exit_step == 10: return False
...@@ -655,6 +659,10 @@ class X393SensCmprs(object): ...@@ -655,6 +659,10 @@ class X393SensCmprs(object):
else: else:
# print ("===================== Mode is neither JP4 nor raw =========================") # print ("===================== Mode is neither JP4 nor raw =========================")
print ("===================== Mode is not JP4 =========================") print ("===================== Mode is not JP4 =========================")
if (bits16):
num_burst_in_line *= 2
if verbose >0 :
print ("Doubling line width for 16-bit mode")
self.x393Sensor.setup_sensor_memory ( self.x393Sensor.setup_sensor_memory (
num_sensor = num_sensor, # input [1:0] num_sensor; num_sensor = num_sensor, # input [1:0] num_sensor;
...@@ -679,7 +687,7 @@ class X393SensCmprs(object): ...@@ -679,7 +687,7 @@ class X393SensCmprs(object):
# replacing with setup compressor: # replacing with setup compressor:
self.setup_compressor(chn = num_sensor, self.setup_compressor(chn = num_sensor,
cmode = cmode, cmode = cmode,
bit16 = bit16, bits16 = bits16,
qbank = 0, qbank = 0,
dc_sub = True, dc_sub = True,
multi_frame = True, multi_frame = True,
...@@ -720,36 +728,72 @@ class X393SensCmprs(object): ...@@ -720,36 +728,72 @@ class X393SensCmprs(object):
""" """
if verbose >0 : if verbose >0 :
print ("===================== IO_SETUP =========================") print ("===================== IO_SETUP, sensorType=",sensorType," =========================")
self.x393Sensor.set_sensor_io_width( if sensorType == x393_sensor.SENSOR_INTERFACE_PARALLEL:
num_sensor = num_sensor, # input [1:0] num_sensor; self.x393Sensor.set_sensor_io_width(
width = 0) # Or use 0 for sensor-generated HACT input [15:0] width; # 0 - use HACT, >0 - generate HACT from start to specified width num_sensor = num_sensor, # input [1:0] num_sensor;
self.x393Sensor.set_sensor_io_ctl ( width = 0) # Or use 0 for sensor-generated HACT input [15:0] width; # 0 - use HACT, >0 - generate HACT from start to specified width
num_sensor = num_sensor, self.x393Sensor.set_sensor_io_ctl (
mrst = False, num_sensor = num_sensor,
arst = False, mrst = False,
aro = False, arst = False,
mmcm_rst = True, #reset mmcm aro = False,
clk_sel = None, #Dealing with Unisims bug: "Error: [Unisim MMCME2_ADV-4] Input clock can only be switched when..." mmcm_rst = True, #reset mmcm
set_delays = False, clk_sel = None, #Dealing with Unisims bug: "Error: [Unisim MMCME2_ADV-4] Input clock can only be switched when..."
quadrants = None) set_delays = False,
quadrants = None)
self.x393Sensor.set_sensor_io_ctl ( #Wait 200 us in real system
num_sensor = num_sensor, self.x393Sensor.set_sensor_io_ctl (
mrst = False, num_sensor = num_sensor,
arst = False, mrst = False,
aro = False, arst = False,
mmcm_rst = True, #reset mmcm aro = False,
clk_sel = clk_sel, mmcm_rst = True, #reset mmcm
set_delays = False, clk_sel = clk_sel,
quadrants = None) set_delays = False,
quadrants = None)
self.x393Sensor.set_sensor_io_ctl (
num_sensor = num_sensor, self.x393Sensor.set_sensor_io_ctl (
mmcm_rst = False, # release MMCM reset (maybe wait longer? num_sensor = num_sensor,
clk_sel = clk_sel, mmcm_rst = False, # release MMCM reset (maybe wait longer?
set_delays = False, clk_sel = clk_sel,
quadrants = None) set_delays = False,
quadrants = None)
elif sensorType == x393_sensor.SENSOR_INTERFACE_LWIR:
self.x393Sensor.set_sensor_io_ctl_lwir (
num_sensor = num_sensor,
mrst = True,
pwdn = False,
mclk = True, # None,
spi_en = 1, #None, # 1 - reset+disable, 2 - noreset, disable, 3 - noreset, enable
segm_zero = True, #None,
out_en = None,
out_single = False,
reset_crc = True,
spi_clk = False) #None)
print ("self.DRY_MODE=",self.DRY_MODE, " resetting LWIR sensor")
if self.DRY_MODE:
self.x393Sensor.set_sensor_io_ctl_lwir (
num_sensor = num_sensor,
mrst = False)
self.x393Sensor.set_sensor_io_ctl_lwir (
num_sensor = num_sensor,
spi_en = 2) #None, # 1 - reset+disable, 2 - noreset, disable, 3 - noreset, enable
# self.x393Sensor.set_sensor_io_ctl_lwir (
# num_sensor = num_sensor,
# spi_en = 2) #None, # 1 - reset+disable, 2 - noreset, disable, 3 - noreset, enable
self.x393Sensor.set_sensor_io_ctl_lwir (
num_sensor = num_sensor,
spi_en = 3, #None, # 1 - reset+disable, 2 - noreset, disable, 3 - noreset, enable
out_en = True)
else:
self.sleep_ms(0.2) # 1 ms. TODO: For real camera turn off all channels simultaneously ***
self.x393Sensor.set_sensor_io_ctl_lwir (
num_sensor = num_sensor,
mrst = False,
spi_en = 3, #None, # 1 - reset+disable, 2 - noreset, disable, 3 - noreset, enable
out_en = True)
if exit_step == 17: return False if exit_step == 17: return False
...@@ -858,7 +902,9 @@ class X393SensCmprs(object): ...@@ -858,7 +902,9 @@ class X393SensCmprs(object):
colorsat_red = None, # colorsat_red, #0x16c, # 0xb6 for x1 colorsat_red = None, # colorsat_red, #0x16c, # 0xb6 for x1
verbose = 1 verbose = 1
): ):
global GLBL_WINDOW global GLBL_WINDOW
if GLBL_WINDOW is None: if GLBL_WINDOW is None:
GLBL_WINDOW = {} GLBL_WINDOW = {}
...@@ -870,6 +916,7 @@ class X393SensCmprs(object): ...@@ -870,6 +916,7 @@ class X393SensCmprs(object):
window_width = GLBL_WINDOW["width"] window_width = GLBL_WINDOW["width"]
except: except:
window_width = SENSOR_DEFAULTS[sensorType]["width"] window_width = SENSOR_DEFAULTS[sensorType]["width"]
# print ("specify_window()1.: window_width['width']=",window_width) #256
if window_height is None: if window_height is None:
try: try:
window_height = GLBL_WINDOW["height"] window_height = GLBL_WINDOW["height"]
...@@ -1110,7 +1157,7 @@ class X393SensCmprs(object): ...@@ -1110,7 +1157,7 @@ class X393SensCmprs(object):
def setup_compressor(self, def setup_compressor(self,
chn, chn,
cmode = 0, # vrlg.CMPRS_CBIT_CMODE_JPEG18, cmode = 0, # vrlg.CMPRS_CBIT_CMODE_JPEG18,
bit16 = bit16, bits16 = 0,
bayer = 0, bayer = 0,
qbank = 0, qbank = 0,
dc_sub = 1, dc_sub = 1,
...@@ -1142,7 +1189,7 @@ class X393SensCmprs(object): ...@@ -1142,7 +1189,7 @@ class X393SensCmprs(object):
CMPRS_CBIT_CMODE_MONO1 = 11 - mono JPEG (not yet implemented) CMPRS_CBIT_CMODE_MONO1 = 11 - mono JPEG (not yet implemented)
CMPRS_CBIT_CMODE_MONO4 = 14 - mono 4 blocks CMPRS_CBIT_CMODE_MONO4 = 14 - mono 4 blocks
CMPRS_CBIT_CMODE_RAW = 15 - raw (uncompressed) mode CMPRS_CBIT_CMODE_RAW = 15 - raw (uncompressed) mode
@param bit16 - 16-bit (2 bytes per pixel) mode @param bits16 - 16-bit (2 bytes per pixel) mode
@param qbank - quantization table page (0..15) @param qbank - quantization table page (0..15)
@param dc_sub - True - subtract DC before running DCT, False - no subtraction, convert as is, @param dc_sub - True - subtract DC before running DCT, False - no subtraction, convert as is,
@param multi_frame - False - single-frame buffer, True - multi-frame video memory buffer, @param multi_frame - False - single-frame buffer, True - multi-frame video memory buffer,
...@@ -1167,7 +1214,7 @@ class X393SensCmprs(object): ...@@ -1167,7 +1214,7 @@ class X393SensCmprs(object):
self. setup_compressor( #self, self. setup_compressor( #self,
chn = chn, chn = chn,
cmode = cmode, cmode = cmode,
bit16 = bit16, bits16 = bits16,
qbank = qbank, qbank = qbank,
dc_sub = dc_sub, dc_sub = dc_sub,
multi_frame = multi_frame, multi_frame = multi_frame,
...@@ -1227,17 +1274,22 @@ class X393SensCmprs(object): ...@@ -1227,17 +1274,22 @@ class X393SensCmprs(object):
num_macro_cols_m1 = (window_width >> 4) - 1 num_macro_cols_m1 = (window_width >> 4) - 1
if (cmode == vrlg.CMPRS_CBIT_CMODE_RAW) and (bit16): if (cmode == vrlg.CMPRS_CBIT_CMODE_RAW) and (bits16):
num_macro_cols_m1 = ((window_width >> 4) << 1) - 1 num_macro_cols_m1 = ((window_width >> 4) << 1) - 1
else: else:
num_macro_cols_m1 = (window_width >> 4) - 1 num_macro_cols_m1 = (window_width >> 4) - 1
if (cmode == vrlg.CMPRS_CBIT_CMODE_RAW): if (cmode == vrlg.CMPRS_CBIT_CMODE_RAW):
num_macro_rows_m1 = (window_height >> 4) - 1 num_macro_rows_m1 = (window_height -1) >> 4
cmprs_mem_height = window_height cmprs_mem_height = window_height
if (verbose > 0) :
print ("num_macro_rows_m1 = ", num_macro_rows_m1, " (raw mode, cmode=",cmode,")")
else: else:
num_macro_rows_m1 = (window_height -1) >> 4 num_macro_rows_m1 = (window_height >> 4) - 1
cmprs_mem_height = window_height & 0xfff0 cmprs_mem_height = window_height & 0xfff0
if (verbose > 0) :
print ("num_macro_rows_m1 = ", num_macro_rows_m1, " (not raw mode, cmode=",cmode,")")
frame_start_address = (last_buf_frame + 1) * frame_start_address_inc * num_sensor frame_start_address = (last_buf_frame + 1) * frame_start_address_inc * num_sensor
...@@ -1246,7 +1298,7 @@ class X393SensCmprs(object): ...@@ -1246,7 +1298,7 @@ class X393SensCmprs(object):
qbank = qbank, qbank = qbank,
dc_sub = dc_sub, dc_sub = dc_sub,
cmode = cmode, # vrlg.CMPRS_CBIT_CMODE_JPEG18, cmode = cmode, # vrlg.CMPRS_CBIT_CMODE_JPEG18,
bit16 = bit16, bits16 = bits16,
multi_frame = True, multi_frame = True,
bayer = bayer, bayer = bayer,
focus_mode = focus_mode, focus_mode = focus_mode,
...@@ -1275,6 +1327,11 @@ class X393SensCmprs(object): ...@@ -1275,6 +1327,11 @@ class X393SensCmprs(object):
left_tiles32 = window_left // 32 left_tiles32 = window_left // 32
last_tile32 = (window_left + ((num_macro_cols_m1 + 1) * 16) + tile_margin - 1) // 32 last_tile32 = (window_left + ((num_macro_cols_m1 + 1) * 16) + tile_margin - 1) // 32
width32 = last_tile32 - left_tiles32 + 1 # number of 32-wide tiles needed in each row width32 = last_tile32 - left_tiles32 + 1 # number of 32-wide tiles needed in each row
# Already done
# if (bits16):
# width32 *= 2
# if verbose >0 :
# print ("Doubling line width for 16-bit mode")
if (verbose > 0) : if (verbose > 0) :
print ("setup_compressor_memory:") print ("setup_compressor_memory:")
...@@ -1452,6 +1509,8 @@ class X393SensCmprs(object): ...@@ -1452,6 +1509,8 @@ class X393SensCmprs(object):
sensorType = self.x393Sensor.getSensorInterfaceType() sensorType = self.x393Sensor.getSensorInterfaceType()
if verbose > 0 : if verbose > 0 :
print ("Sensor interface type: %s"%(sensorType)) print ("Sensor interface type: %s"%(sensorType))
# print ("setup_all_sensors(): window_width['width']=",window_width) # None here
window = self.specify_window (window_width = window_width, window = self.specify_window (window_width = window_width,
window_height = window_height, window_height = window_height,
window_left = window_left, window_left = window_left,
...@@ -1482,8 +1541,10 @@ class X393SensCmprs(object): ...@@ -1482,8 +1541,10 @@ class X393SensCmprs(object):
histogram_width_m1 = window_width - 1 # 33 histogram_width_m1 = window_width - 1 # 33
if histogram_height_m1 is None: if histogram_height_m1 is None:
histogram_height_m1 = window_height - 1 # 1145 histogram_height_m1 = window_height - 1 # 1145
# print ("setup_all_sensors().2: window_width['width']=",window_width) #256 here
self.specify_phys_memory(circbuf_chn_size = circbuf_chn_size) self.specify_phys_memory(circbuf_chn_size = circbuf_chn_size)
# print ("setup_all_sensors().3: window_width['width']=",window_width)
""" """
self.specify_window (window_width = window_width, self.specify_window (window_width = window_width,
window_height = window_height, window_height = window_height,
...@@ -1527,6 +1588,7 @@ class X393SensCmprs(object): ...@@ -1527,6 +1588,7 @@ class X393SensCmprs(object):
print ("membridge d2h end = 0x%x"%(GLBL_MEMBRIDGE_D2H_END)) print ("membridge d2h end = 0x%x"%(GLBL_MEMBRIDGE_D2H_END))
print ("membridge d2h size = %d bytes"%(GLBL_MEMBRIDGE_D2H_END - GLBL_MEMBRIDGE_D2H_START)) print ("membridge d2h size = %d bytes"%(GLBL_MEMBRIDGE_D2H_END - GLBL_MEMBRIDGE_D2H_START))
print ("memory buffer end = 0x%x"%(GLBL_BUFFER_END)) print ("memory buffer end = 0x%x"%(GLBL_BUFFER_END))
self.program_status_debug (3,0) self.program_status_debug (3,0)
if setup_membridge: if setup_membridge:
...@@ -2502,7 +2564,7 @@ jpeg_write "img.jpeg" 0 100 None False 0 "/www/pages/" 3 ...@@ -2502,7 +2564,7 @@ jpeg_write "img.jpeg" 0 100 None False 0 "/www/pages/" 3
y_quality = None, y_quality = None,
c_quality = None, # use "same" to save None c_quality = None, # use "same" to save None
cmode = 0, # vrlg.CMPRS_CBIT_CMODE_JPEG18, cmode = 0, # vrlg.CMPRS_CBIT_CMODE_JPEG18,
bit16 = 0, bits16 = 0,
bayer = 3, #0, as in simulator bayer = 3, #0, as in simulator
window_width = 66, window_width = 66,
window_height = 36, window_height = 36,
...@@ -2534,7 +2596,7 @@ jpeg_write "img.jpeg" 0 100 None False 0 "/www/pages/" 3 ...@@ -2534,7 +2596,7 @@ jpeg_write "img.jpeg" 0 100 None False 0 "/www/pages/" 3
CMPRS_CBIT_CMODE_MONO1 = 11 - mono JPEG (not yet implemented) CMPRS_CBIT_CMODE_MONO1 = 11 - mono JPEG (not yet implemented)
CMPRS_CBIT_CMODE_MONO4 = 14 - mono 4 blocks CMPRS_CBIT_CMODE_MONO4 = 14 - mono 4 blocks
CMPRS_CBIT_CMODE_RAW = 15 - raw (unclmpressed) mode CMPRS_CBIT_CMODE_RAW = 15 - raw (unclmpressed) mode
@param bit16 - 16 bit (2-byte per pixel) mode @param bits16 - 16 bit (2-byte per pixel) mode
@param bayer - Bayer shift (0..3) @param bayer - Bayer shift (0..3)
@param window_width - window width in pixels (bytes) (TODO: add 16-bit mode) @param window_width - window width in pixels (bytes) (TODO: add 16-bit mode)
@param window_height - window height in lines @param window_height - window height in lines
...@@ -2633,7 +2695,7 @@ jpeg_write "img.jpeg" 0 100 None False 0 "/www/pages/" 3 ...@@ -2633,7 +2695,7 @@ jpeg_write "img.jpeg" 0 100 None False 0 "/www/pages/" 3
# setup compressor memory and mode # setup compressor memory and mode
self. setup_compressor(chn = chn, self. setup_compressor(chn = chn,
cmode = cmode, cmode = cmode,
bit16 = bit16, bits16 = bits16,
qbank = qbank, qbank = qbank,
dc_sub = True, dc_sub = True,
multi_frame = False, multi_frame = False,
......
py393/x393_sensor.py
View file @ f35c087d
...@@ -505,7 +505,7 @@ class X393Sensor(object): ...@@ -505,7 +505,7 @@ class X393Sensor(object):
rslt |= 1 << vrlg.VOSPI_OUT_EN_SINGL rslt |= 1 << vrlg.VOSPI_OUT_EN_SINGL
if reset_crc: if reset_crc:
rslt |= 1 << vrlg.VOSPI_RESET_CRC rslt |= 1 << vrlg.VOSPI_RESET_CRC
if not out_en is None: if not spi_clk is None:
rslt |= (2,3)[spi_clk] << vrlg.VOSPI_SPI_CLK rslt |= (2,3)[spi_clk] << vrlg.VOSPI_SPI_CLK
if not gpio0 is None: if not gpio0 is None:
rslt |= (gpio0 & 3) << (vrlg.VOSPI_GPIO + 0) rslt |= (gpio0 & 3) << (vrlg.VOSPI_GPIO + 0)
...@@ -1042,6 +1042,7 @@ class X393Sensor(object): ...@@ -1042,6 +1042,7 @@ class X393Sensor(object):
# TODO: Make one for HiSPi (it is different) # TODO: Make one for HiSPi (it is different)
def set_sensor_io_ctl_lwir (self, def set_sensor_io_ctl_lwir (self,
num_sensor,
mrst = None, mrst = None,
pwdn = None, pwdn = None,
mclk = None, mclk = None,
......
sensor/sens_lepton3.v
View file @ f35c087d
...@@ -259,7 +259,7 @@ module sens_lepton3 #( ...@@ -259,7 +259,7 @@ module sens_lepton3 #(
assign fake_out = set_ctrl_r && data_r[VOSPI_FAKE_OUT]; assign fake_out = set_ctrl_r && data_r[VOSPI_FAKE_OUT];
assign spi_mosi_int = set_ctrl_r && data_r[VOSPI_MOSI]; // not used assign spi_mosi_int = set_ctrl_r && data_r[VOSPI_MOSI]; // not used
assign prsts = prst | lwir_mrst_pclk[1]; assign prsts = prst | !lwir_mrst_pclk[1];
always @(posedge mclk) begin always @(posedge mclk) begin
if (mrst) data_r <= 0; if (mrst) data_r <= 0;
...@@ -346,6 +346,10 @@ module sens_lepton3 #( ...@@ -346,6 +346,10 @@ module sens_lepton3 #(
// implement I/O ports, including fake ones, to be able to assign them I/O pads // implement I/O ports, including fake ones, to be able to assign them I/O pads
// generate clocka to sesnor output, controlled by control word bits // generate clocka to sesnor output, controlled by control word bits
// SPI clock (10..20MHz) // SPI clock (10..20MHz)
reg prst_r;
always @ (posedge pclk) begin
prst_r <= prst;
end
oddr_ss #( // spi_clk oddr_ss #( // spi_clk
.IOSTANDARD (PXD_IOSTANDARD), .IOSTANDARD (PXD_IOSTANDARD),
.SLEW (PXD_SLEW), .SLEW (PXD_SLEW),
...@@ -353,13 +357,13 @@ module sens_lepton3 #( ...@@ -353,13 +357,13 @@ module sens_lepton3 #(
.INIT (1'b0), .INIT (1'b0),
.SRTYPE ("SYNC") .SRTYPE ("SYNC")
) spi_clk_i ( ) spi_clk_i (
.clk (pclk), // input .clk (pclk), // input
.ce (spi_clk_en_pclk[1] | spi_clken), // input .ce (spi_clk_en_pclk[1] | spi_clken | prst_r), // input
.rst (prst), // input .rst (prst), // input
.set (1'b0), // input .set (1'b0), // input
.din (2'b01), // input[1:0] .din (2'b01), // input[1:0]
.tin (1'b0), // input .tin (1'b0), // input
.dq (spi_clk) // output .dq (spi_clk) // output
); );
// sensor master clock (25MHz) // sensor master clock (25MHz)
iobuf #( // lwir_mclk iobuf #( // lwir_mclk
...@@ -430,7 +434,7 @@ module sens_lepton3 #( ...@@ -430,7 +434,7 @@ module sens_lepton3 #(
generate // gpio[3:0] generate // gpio[3:0]
genvar i; genvar i;
for (i=0; i < (VOSPI_GPIO_BITS / 2); i=i+1) begin: gpio_block for (i=0; i < (VOSPI_GPIO_BITS / 2); i=i+1) begin: gpio_block
gpio_bit gpio_bit_i ( gpio393_bit gpio_bit_i (
.clk (mclk), // input .clk (mclk), // input
.srst (mrst), // input .srst (mrst), // input
.we (set_ctrl_r), // input .we (set_ctrl_r), // input
......
sensor/sensor_channel.v
View file @ f35c087d
...@@ -362,8 +362,8 @@ module sensor_channel#( ...@@ -362,8 +362,8 @@ module sensor_channel#(
input sns_clkp, input sns_clkp,
input sns_clkn, input sns_clkn,
`elsif LWIR `elsif LWIR
input [ 4:0] sns_dp40, inout [ 4:0] sns_dp40,
input [ 4:0] sns_dn40, inout [ 4:0] sns_dn40,
inout sns_dp5, // diff MIPI signals (not yet implemented) inout sns_dp5, // diff MIPI signals (not yet implemented)
inout sns_dn5, // diff MIPI signals (not yet implemented) inout sns_dn5, // diff MIPI signals (not yet implemented)
inout [ 7:6] sns_dp76, inout [ 7:6] sns_dp76,
...@@ -1069,12 +1069,12 @@ module sensor_channel#( ...@@ -1069,12 +1069,12 @@ module sensor_channel#(
// .sns_mclk(), // input // .sns_mclk(), // input
.spi_miso (sns_dp40[0]), // inout .spi_miso (sns_dp40[0]), // inout
.spi_mosi (sns_dn40[0]), // inout .spi_mosi (sns_dn40[0]), // inout
.spi_cs (sns_dp40[1]), // inout .spi_cs (sns_dp40[1]), // output
.spi_clk (sns_dn40[1]), // inout .spi_clk (sns_dn40[1]), // output
.gpio ({sns_dp40[4], sns_dn40[4], sns_dp40[3], sns_dn40[3]}), // inout [3:0] .gpio ({sns_dp40[4], sns_dn40[4], sns_dp40[3], sns_dn40[3]}), // inout [3:0]
.lwir_mclk (sns_dp76[6]), // inout .lwir_mclk (sns_dp76[6]), // output
.lwir_mrst (sns_dp76[7]), // inout .lwir_mrst (sns_dp76[7]), // output
.lwir_pwdn (sns_dn76[7]), // inout .lwir_pwdn (sns_dn76[7]), // output
.mipi_dp (sns_dp5), // inout .mipi_dp (sns_dp5), // inout
.mipi_dn (sns_dn5), // inout .mipi_dn (sns_dn5), // inout
.mipi_clkp (sns_clkp), // inout .mipi_clkp (sns_clkp), // inout
......
sensor/sensors393.v
View file @ f35c087d
...@@ -398,8 +398,8 @@ module sensors393 #( ...@@ -398,8 +398,8 @@ module sensors393 #(
input [3:0] sns_clkp, // SuppressThisWarning all - input-only in HiSPi mode input [3:0] sns_clkp, // SuppressThisWarning all - input-only in HiSPi mode
input [3:0] sns_clkn, // SuppressThisWarning all - input-only in HiSPi mode input [3:0] sns_clkn, // SuppressThisWarning all - input-only in HiSPi mode
`elsif LWIR `elsif LWIR
input [19:0] sns_dp40, inout [19:0] sns_dp40,
input [19:0] sns_dn40, inout [19:0] sns_dn40,
inout [ 3:0] sns_dp5, // diff MIPI signals (not yet implemented) inout [ 3:0] sns_dp5, // diff MIPI signals (not yet implemented)
inout [ 3:0] sns_dn5, // diff MIPI signals (not yet implemented) inout [ 3:0] sns_dn5, // diff MIPI signals (not yet implemented)
inout [ 7:0] sns_dp76, inout [ 7:0] sns_dp76,
......
sensor/vospi_packet_80.v
View file @ f35c087d
...@@ -71,6 +71,7 @@ module vospi_packet_80#( ...@@ -71,6 +71,7 @@ module vospi_packet_80#(
reg set_crc_r; reg set_crc_r;
reg set_d_r; reg set_d_r;
reg den_r; reg den_r;
reg [1:0] packet_header = 2'b11;
reg [15:0] d_sr; reg [15:0] d_sr;
reg [ 1:0] start_r; reg [ 1:0] start_r;
...@@ -88,7 +89,9 @@ module vospi_packet_80#( ...@@ -88,7 +89,9 @@ module vospi_packet_80#(
assign pre_last_w = pre_lsb_w && (wcntr == (VOSPI_PACKET_WORDS + 1)); assign pre_last_w = pre_lsb_w && (wcntr == (VOSPI_PACKET_WORDS + 1));
assign packet_done = packet_end[2]; assign packet_done = packet_end[2];
assign id = id_r; assign id = id_r;
assign dmask = den_r ? 16'hffff: (wcntr[0]?16'h0: 16'h0fff); // assign dmask = den_r ? 16'hffff: (wcntr[0]?16'h0: 16'h0fff);
assign dmask = packet_header[1] ? (packet_header[0] ? 16'h0fff: 16'h0) : 16'hffff ;
assign crc_err = packet_end[2] && (crc_r != crc_w); assign crc_err = packet_end[2] && (crc_r != crc_w);
assign dv = dv_r; assign dv = dv_r;
assign dout = d_r; assign dout = d_r;
...@@ -96,7 +99,7 @@ module vospi_packet_80#( ...@@ -96,7 +99,7 @@ module vospi_packet_80#(
always @ (posedge clk) begin always @ (posedge clk) begin
if (rst || packet_end[0]) cs_r[0] <= 0; if (rst || packet_end[0]) cs_r[0] <= 0;
else if (start) cs_r[1] <= 1; else if (start) cs_r[0] <= 1;
cs_r[1] <= cs_r[0]; cs_r[1] <= cs_r[0];
...@@ -111,8 +114,11 @@ module vospi_packet_80#( ...@@ -111,8 +114,11 @@ module vospi_packet_80#(
if (rst || !cs_r[0] || packet_end[0]) wcntr <= 0; if (rst || !cs_r[0] || packet_end[0]) wcntr <= 0;
else if (lsb_r) wcntr <= wcntr + 1; else if (lsb_r) wcntr <= wcntr + 1;
if (rst || !cs_r[0] ) packet_end <= 0; if (rst || !cs_r[0] ) packet_end[1:0] <= 0;
else packet_end <= {packet_end[1:0], pre_last_w}; else packet_end[1:0] <= {packet_end[0], pre_last_w};
if (rst) packet_end[2] <= 0;
else packet_end[2] <= packet_end[1];
if (rst) start_r <= 0; if (rst) start_r <= 0;
else start_r <= {start_r[0],start}; else start_r <= {start_r[0],start};
...@@ -121,10 +127,11 @@ module vospi_packet_80#( ...@@ -121,10 +127,11 @@ module vospi_packet_80#(
set_crc_r <= !rst && (wcntr == 1) && lsb_r; set_crc_r <= !rst && (wcntr == 1) && lsb_r;
set_d_r <= !rst && den_r && lsb_r; set_d_r <= !rst && den_r && lsb_r;
if (rst || !cs_r[1]) den_r <= 0; if (rst || !cs_r[1] || packet_done) den_r <= 0;
else if (set_crc_r) den_r <= 1; else if (set_crc_r) den_r <= 1;
if (cs_r[0]) d_sr <= {miso, d_sr[15:1]}; // if (cs_r[0]) d_sr <= {miso, d_sr[15:1]};
if (cs_r[0]) d_sr <= {d_sr[14:0],miso};
if (set_id_r) id_r <= d_sr; if (set_id_r) id_r <= d_sr;
if (set_crc_r) crc_r <= d_sr; if (set_crc_r) crc_r <= d_sr;
if (set_d_r) d_r <= d_sr; if (set_d_r) d_r <= d_sr;
...@@ -135,6 +142,9 @@ module vospi_packet_80#( ...@@ -135,6 +142,9 @@ module vospi_packet_80#(
else if (set_id_r) packet_invalid_r <= (d_sr[11:8] == 4'hf); else if (set_id_r) packet_invalid_r <= (d_sr[11:8] == 4'hf);
id_stb <= set_id_r; id_stb <= set_id_r;
if (rst || start || packet_done) packet_header <= 2'b11;
else if (copy_word) packet_header <= {packet_header[0], 1'b0};
end end
crc16_x16x12x5x0 crc16_x16x12x5x0_i ( crc16_x16x12x5x0 crc16_x16x12x5x0_i (
......
sensor/vospi_segment_61.v
View file @ f35c087d
...@@ -101,6 +101,8 @@ module vospi_segment_61#( ...@@ -101,6 +101,8 @@ module vospi_segment_61#(
wire packet_dv; // read full packet wire packet_dv; // read full packet
wire [15:0] packet_dout; // read full packet wire [15:0] packet_dout; // read full packet
wire [15:0] packet_id; wire [15:0] packet_id;
wire [ 3:0] segment_id;
wire packet_invalid;
wire id_stb; wire id_stb;
wire is_first_segment_w; wire is_first_segment_w;
wire is_last_segment_w; wire is_last_segment_w;
...@@ -119,7 +121,9 @@ module vospi_segment_61#( ...@@ -119,7 +121,9 @@ module vospi_segment_61#(
assign is_first_segment_w = (exp_segment == VOSPI_SEGMENT_FIRST); assign is_first_segment_w = (exp_segment == VOSPI_SEGMENT_FIRST);
assign is_last_segment_w = (exp_segment == VOSPI_SEGMENT_LAST); assign is_last_segment_w = (exp_segment == VOSPI_SEGMENT_LAST);
assign segment_good_w = (packet_id[15:12] == exp_segment) || ((packet_id[15:12] == 0) && segm0_ok); assign segment_id = packet_id[15:12];
// assign segment_good_w = (packet_id[15:12] == exp_segment) || ((packet_id[15:12] == 0) && segm0_ok);
assign segment_good_w = (segment_id == exp_segment) || ((packet_id[15:12] == 0) && segm0_ok);
assign segment_stb = id_stb && (packet_id[11:0] == VOSPI_PACKET_TTT); assign segment_stb = id_stb && (packet_id[11:0] == VOSPI_PACKET_TTT);
assign we = segment_running && !discard_segment_r && packet_dv; assign we = segment_running && !discard_segment_r && packet_dv;
assign crc_err = packet_done && packet_crc_err; // crc_err_r; assign crc_err = packet_done && packet_crc_err; // crc_err_r;
...@@ -160,9 +164,9 @@ module vospi_segment_61#( ...@@ -160,9 +164,9 @@ module vospi_segment_61#(
if (start_d) segment_start_packet <= full_packet; if (start_d) segment_start_packet <= full_packet;
if (start_d) segment_start_waddr <= waddr; if (start_d) segment_start_waddr <= waddr;
if (rst || (start && is_first_segment_w)) full_packet <= 0; if (rst || (start && is_first_segment_w)) full_packet <= 0;
else if (discard_set) full_packet <= segment_start_packet; else if (discard_set) full_packet <= segment_start_packet;
else if (!discard_segment_r && packet_done) full_packet <= full_packet + 1; else if (!discard_segment_r && !packet_invalid && packet_done) full_packet <= full_packet + 1;
// if (rst || start) crc_err_r <= 0; // if (rst || start) crc_err_r <= 0;
// else if (packet_done && packet_crc_err) crc_err_r <= 0; // else if (packet_done && packet_crc_err) crc_err_r <= 0;
...@@ -176,7 +180,8 @@ module vospi_segment_61#( ...@@ -176,7 +180,8 @@ module vospi_segment_61#(
if (!segment_busy_r || start) segment_running <= 0; if (!segment_busy_r || start) segment_running <= 0;
else if (id_stb && (packet_id[11:0] == VOSPI_PACKET_FIRST)) segment_running <= 1; else if (id_stb && (packet_id[11:0] == VOSPI_PACKET_FIRST)) segment_running <= 1;
packet_start <= !rst && !packet_busy && segment_busy_r; // packet_start <= !rst && !packet_busy && segment_busy_r;
packet_start <= !rst && !packet_busy && segment_busy_r && !packet_start;
if (rst) waddr <= 0; if (rst) waddr <= 0;
else if (discard_set) waddr <= segment_start_waddr; else if (discard_set) waddr <= segment_start_waddr;
...@@ -201,7 +206,11 @@ module vospi_segment_61#( ...@@ -201,7 +206,11 @@ module vospi_segment_61#(
wire frame_dav; wire frame_dav;
wire hact_start_w; // (hact will start next cycle wire hact_start_w; // (hact will start next cycle
wire hact_end_w; wire hact_end_w;
`ifdef SIMULATION
reg [15:0] duration_cntr;
`else
reg [ 7:0] duration_cntr; reg [ 7:0] duration_cntr;
`endif
reg [2:0] hact_r; reg [2:0] hact_r;
reg pend_eof_r; reg pend_eof_r;
reg [10:0] raddr; reg [10:0] raddr;
...@@ -211,13 +220,13 @@ module vospi_segment_61#( ...@@ -211,13 +220,13 @@ module vospi_segment_61#(
assign start_out_frame_w = segment_good && is_first_segment_w && out_request; assign start_out_frame_w = segment_good && is_first_segment_w && out_request;
assign packets_avail = {1'b0,full_packet_verified} - {1'b0,full_packet_out} - VOSPI_PACKETS_PER_LINE; assign packets_avail = {1'b0,full_packet_verified} - {1'b0,full_packet_out} - VOSPI_PACKETS_PER_LINE;
// assign frame_out_done_w = packet_out_done && (full_packet_out == (VOSPI_PACKETS_FRAME - 1)); // assign frame_out_done_w = packet_out_done && (full_packet_out == (VOSPI_PACKETS_FRAME - 1));
assign frame_out_done_w = hact_end_w && (full_packet_out == (VOSPI_PACKETS_FRAME - 1)); assign frame_out_done_w = hact_end_w && (full_packet_out == (VOSPI_PACKETS_FRAME - VOSPI_PACKETS_PER_LINE));
assign frame_dav = !packets_avail[8] || out_pending; assign frame_dav = !packets_avail[8] || out_pending;
assign hact_start_w = out_frame && (duration_cntr == 0) && !hact_r[0] && frame_dav; assign hact_start_w = out_frame && (duration_cntr == 0) && !hact_r[0] && frame_dav;
assign hact_end_w = (duration_cntr == 0) && hact_r[0]; assign hact_end_w = (duration_cntr == 0) && hact_r[0];
assign eof_w = out_frame && (duration_cntr == 0) && pend_eof_r; assign eof_w = out_frame && (duration_cntr == 0) && pend_eof_r;
assign sof_w = rst && start_out_frame_w; assign sof_w = !rst && start_out_frame_w;
assign hact = hact_r[2]; assign hact = hact_r[2];
assign eof = eof_r[2]; assign eof = eof_r[2];
assign sof = sof_r; assign sof = sof_r;
...@@ -249,7 +258,8 @@ module vospi_segment_61#( ...@@ -249,7 +258,8 @@ module vospi_segment_61#(
if (rst) pend_eof_r <= 0; // not needed? if (rst) pend_eof_r <= 0; // not needed?
else if (frame_out_done_w) pend_eof_r <= 1; else if (frame_out_done_w) pend_eof_r <= 1;
else if (eof_r[0]) pend_eof_r <= 0; // else if (eof_r[0]) pend_eof_r <= 0;
else if (eof_w) pend_eof_r <= 0;
if (rst) duration_cntr <= 0; if (rst) duration_cntr <= 0;
else if (start_out_frame_w) duration_cntr <= VOSPI_SOF_TO_HACT; else if (start_out_frame_w) duration_cntr <= VOSPI_SOF_TO_HACT;
...@@ -278,7 +288,7 @@ module vospi_segment_61#( ...@@ -278,7 +288,7 @@ module vospi_segment_61#(
.packet_busy (packet_busy), // output .packet_busy (packet_busy), // output
.crc_err (packet_crc_err), // output .crc_err (packet_crc_err), // output
.id (packet_id), // output[15:0] .id (packet_id), // output[15:0]
.packet_invalid (), // output - not used, processed internally, no dv generated .packet_invalid (packet_invalid), // output - not used, processed internally, no dv generated
.id_stb (id_stb) // output reg .id_stb (id_stb) // output reg
); );
......
simulation_modules/simul_lwir160x120_vospi.v
View file @ f35c087d
...@@ -46,7 +46,7 @@ module simul_lwir160x120_vospi # ( ...@@ -46,7 +46,7 @@ module simul_lwir160x120_vospi # (
parameter TELEMETRY = 1, // 0 - disabled, 1 - as header, 2 - as footer parameter TELEMETRY = 1, // 0 - disabled, 1 - as header, 2 - as footer
parameter FRAME_PERIOD = 946969, // 26.4 fps @25 MHz parameter FRAME_PERIOD = 946969, // 26.4 fps @25 MHz
parameter SEGMENT_PERIOD = 10000, // 236742, // 26.4 fps @25 MHz parameter SEGMENT_PERIOD = 5100, // min 05063? // 10000, // 236742, // 26.4 fps @25 MHz
parameter SEGMENTS_SEQ = 8, // 12 With ITAR parameter SEGMENTS_SEQ = 8, // 12 With ITAR
parameter FRAME_DELAY = 100, // mclk period to start first frame 1 parameter FRAME_DELAY = 100, // mclk period to start first frame 1
...@@ -115,7 +115,7 @@ module simul_lwir160x120_vospi # ( ...@@ -115,7 +115,7 @@ module simul_lwir160x120_vospi # (
// registers for copiing data to packet array // registers for copiing data to packet array
//'0xe7319' //'0xe7319'
reg [19:0] frame_dly_cntr; // delay till next frame start // reg [19:0] frame_dly_cntr; // delay till next frame start
reg [19:0] segment_dly_cntr; // delay till next frame segment reg [19:0] segment_dly_cntr; // delay till next frame segment
reg frame_start; reg frame_start;
reg segment_start; reg segment_start;
...@@ -123,8 +123,9 @@ module simul_lwir160x120_vospi # ( ...@@ -123,8 +123,9 @@ module simul_lwir160x120_vospi # (
wire [ 3:0] segment_id; wire [ 3:0] segment_id;
reg copy_page; reg copy_page;
reg copy_run; // reg copy_run;
wire copy_done; // wire copy_done;
wire frame_done;
reg segment_run; reg segment_run;
wire segment_done; wire segment_done;
...@@ -134,6 +135,7 @@ module simul_lwir160x120_vospi # ( ...@@ -134,6 +135,7 @@ module simul_lwir160x120_vospi # (
reg [6:0] copy_word; // word number to copy in a packet (0..82), last one copies CRC to word 1 reg [6:0] copy_word; // word number to copy in a packet (0..82), last one copies CRC to word 1
reg copy_crc; reg copy_crc;
wire copy_crc_w;
wire [7:0] copy_packet_full; wire [7:0] copy_packet_full;
wire [7:0] copy_telemetry_packet; // only 2 LSB wire [7:0] copy_telemetry_packet; // only 2 LSB
// wire [7:0] copy_packet_segment; // wire [7:0] copy_packet_segment;
...@@ -172,9 +174,11 @@ module simul_lwir160x120_vospi # ( ...@@ -172,9 +174,11 @@ module simul_lwir160x120_vospi # (
reg [ 6:0] readout_word_indx; // number of word in a readout packet reg [ 6:0] readout_word_indx; // number of word in a readout packet
reg [ 3:0] readout_bit; // 0 - msb, 15 - lsb reg [ 3:0] readout_bit; // 0 - msb, 15 - lsb
reg [15:0] readout_sr_good; reg [15:0] readout_sr_good;
reg [15:0] readout_sr_good_dbg; // no shift, just memory read
reg [15:0] readout_sr_bad; reg [15:0] readout_sr_bad;
reg [ 3:0] segments_ready; reg [ 3:0] segments_ready;
reg segment_av; // segments avalable for readout reg segment_av_mclk; // segments avalable for readout
// reg segment_av; // segments avalable for readout
reg sync_lost; reg sync_lost;
reg packet_sent; reg packet_sent;
// reg packet_skipped; // sent invalid packet // reg packet_skipped; // sent invalid packet
...@@ -188,25 +192,29 @@ module simul_lwir160x120_vospi # ( ...@@ -188,25 +192,29 @@ module simul_lwir160x120_vospi # (
reg readout_last_bit; reg readout_last_bit;
reg readout_first_bit = 1; reg readout_first_bit = 1;
wire [15:0] readout_address; // buffer readout address wire [15:0] readout_address; // buffer readout address
wire readout_good_w ; // should be valid at first negative transition of the spi_clk // wire readout_good_w ; // should be valid at first negative transition of the spi_clk
reg readout_good; // reading out/sending valid packet reg readout_good; // reading out/sending valid packet
wire readout_segment_done_w;
reg readout_segment_done;
assign readout_last_segment = readout_segment == (FRAME_SEGMENTS - 1); assign readout_last_segment = readout_segment == (FRAME_SEGMENTS - 1);
assign readout_last_packet = readout_packet == (SEGMENT_PACKETS_TELEMETRY -1); assign readout_last_packet = readout_packet == (SEGMENT_PACKETS_TELEMETRY -1);
assign readout_last_word = readout_word_indx == (PACKET_WORDS -1); assign readout_last_word = readout_word_indx == (PACKET_WORDS -1);
assign readout_pre_last_bit = readout_bit[3:0] == 14; assign readout_pre_last_bit = readout_bit[3:0] == 14;
assign readout_pre_first_bit = readout_bit[3:0] == 15; assign readout_pre_first_bit = readout_bit[3:0] == 15;
// assign readout_segment_done_w = readout_last_packet && readout_last_word && readout_pre_last_bit;
assign readout_segment_done_w = readout_last_packet && readout_last_word && readout_last_bit;
assign readout_address = readout_word_indx + assign readout_address = readout_word_indx +
(PACKET_WORDS * readout_packet) + (PACKET_WORDS * readout_packet) +
(SEGMENT_WORDS * readout_segment) + (SEGMENT_WORDS * readout_segment) +
(FRAME_WORDS * readout_page); (FRAME_WORDS * readout_page);
assign readout_good_w = segment_av; // assign readout_good_w = segment_av_mclk;
assign spi_miso = readout_good ? readout_sr_good[15] : readout_sr_bad[15]; assign spi_miso = readout_good ? readout_sr_good[15] : readout_sr_bad[15];
assign start_segm_rd = (readout_word_indx == 0) && readout_last_bit && !spi_cs; // assign start_segm_rd = (readout_word_indx == 0) && readout_last_bit && !spi_cs;
assign start_segm_rd = readout_last_bit && (readout_word_indx == 0) && readout_last_packet && !spi_cs && readout_good;
// wire [ 2:0] copy_segment; // wire [ 2:0] copy_segment;
...@@ -223,14 +231,21 @@ module simul_lwir160x120_vospi # ( ...@@ -223,14 +231,21 @@ module simul_lwir160x120_vospi # (
assign i2c_sda = 'bz; assign i2c_sda = 'bz;
assign copy_done = copy_run && copy_crc && (copy_packet== (FRAME_PACKETS_FULL -1)); // assign copy_done = copy_run && copy_crc && (copy_packet== (FRAME_PACKETS_FULL -1));
assign segment_done = copy_run && copy_crc && (segment_packet== (SEGMENT_PACKETS_FULL -1)); // assign segment_done = copy_run && copy_crc && (segment_packet== (SEGMENT_PACKETS_FULL -1));
// assign copy_done = segment_run && copy_crc && (copy_packet== (FRAME_PACKETS_FULL -1));
assign frame_done = segment_run && copy_crc && (copy_packet== (FRAME_PACKETS_FULL -1));
assign segment_done = segment_run && copy_crc && (segment_packet== (SEGMENT_PACKETS_FULL -1));
assign segment_id = (segments_cntr < 4) ? (segments_cntr +1) : 4'b0; assign segment_id = (segments_cntr < 4) ? (segments_cntr +1) : 4'b0;
assign copy_packet_full = (copy_packet < FRAME_PACKETS)?(copy_packet + ((TELEMETRY == 1) ? 4 : 0)):(copy_packet - ((TELEMETRY == 1)?FRAME_PACKETS: 0)) ; assign copy_packet_full = (copy_packet < FRAME_PACKETS)?(copy_packet + ((TELEMETRY == 1) ? 4 : 0)):(copy_packet - ((TELEMETRY == 1)?FRAME_PACKETS: 0)) ;
assign copy_telemetry_packet = copy_packet - FRAME_PACKETS; assign copy_telemetry_packet = copy_packet - FRAME_PACKETS;
assign copy_pix_or_tel = copy_run && (copy_word < PACKET_PIXELS); // && (copy_packet < FRAME_PACKETS); // assign copy_pix_or_tel = copy_run && (copy_word < PACKET_PIXELS); // && (copy_packet < FRAME_PACKETS);
assign copy_pix_or_tel = segment_run && (copy_word < PACKET_PIXELS); // && (copy_packet < FRAME_PACKETS);
assign copy_pix_only = copy_pix_or_tel && (copy_packet < FRAME_PACKETS); assign copy_pix_only = copy_pix_or_tel && (copy_packet < FRAME_PACKETS);
assign copy_tel_only = copy_pix_or_tel && (copy_packet >= FRAME_PACKETS); assign copy_tel_only = copy_pix_or_tel && (copy_packet >= FRAME_PACKETS);
// assign copy_packet_segment = copy_packet_full / SEGMENT_PACKETS_TELEMETRY; /// // assign copy_packet_segment = copy_packet_full / SEGMENT_PACKETS_TELEMETRY; ///
...@@ -248,6 +263,8 @@ module simul_lwir160x120_vospi # ( ...@@ -248,6 +263,8 @@ module simul_lwir160x120_vospi # (
assign copy_wa_full = copy_wa + (PACKET_WORDS * copy_packet_full) + (FRAME_WORDS * copy_page); assign copy_wa_full = copy_wa + (PACKET_WORDS * copy_packet_full) + (FRAME_WORDS * copy_page);
assign copy_crc_w = copy_word == (PACKET_WORDS - 1);
assign frame_average32 = (frame_sum / (WINDOW_WIDTH * WINDOW_HEIGHT)); assign frame_average32 = (frame_sum / (WINDOW_WIDTH * WINDOW_HEIGHT));
assign frame_average = frame_average32[15:0]; assign frame_average = frame_average32[15:0];
...@@ -262,11 +279,12 @@ initial begin ...@@ -262,11 +279,12 @@ initial begin
// $readmemh({`ROOTPATH,"/input_data/sensor_16.dat"},sensor_data); // $readmemh({`ROOTPATH,"/input_data/sensor_16.dat"},sensor_data);
$readmemh(DATA_FILE,sensor_data,0); $readmemh(DATA_FILE,sensor_data,0);
// reg [OUT_BITS-1:0] packet_bad [0: PACKET_WORDS-1]; // reg [OUT_BITS-1:0] packet_bad [0: PACKET_WORDS-1];
packet_bad[0] <= 'h0f00; packet_bad[0] = 'h0f00;
packet_bad[1] <= 'h0000; // calculate and put crc? packet_bad[1] = 'h5220; // calculate and put crc?
for (i = 2; i < PACKET_WORDS; i = i+1) begin for (i = 2; i < PACKET_WORDS; i = i+1) begin
packet_bad[i] <= 0; packet_bad[i] = 0;
end end
packet_bad[1] = 'h5220; // calculate and put crc?
end end
always @ (posedge mclk) begin always @ (posedge mclk) begin
if (rst || (ms_cntr == 0)) ms_cntr <= MS_PERIOD -1; if (rst || (ms_cntr == 0)) ms_cntr <= MS_PERIOD -1;
...@@ -279,6 +297,7 @@ always @ (posedge mclk) begin ...@@ -279,6 +297,7 @@ always @ (posedge mclk) begin
if (rst) segment_dly_cntr <= FRAME_DELAY; if (rst) segment_dly_cntr <= FRAME_DELAY;
else if (segment_start) segment_dly_cntr <= SEGMENT_PERIOD; else if (segment_start) segment_dly_cntr <= SEGMENT_PERIOD;
else segment_dly_cntr <= segment_dly_cntr - 1; else segment_dly_cntr <= segment_dly_cntr - 1;
segment_start <= !rst && (segment_dly_cntr == 0); segment_start <= !rst && (segment_dly_cntr == 0);
if (rst || segment_done) segment_run <= 0; if (rst || segment_done) segment_run <= 0;
...@@ -286,28 +305,40 @@ always @ (posedge mclk) begin ...@@ -286,28 +305,40 @@ always @ (posedge mclk) begin
if (rst) frame_dly_cntr <= FRAME_DELAY; // if (rst) frame_dly_cntr <= FRAME_DELAY;
else if (frame_start) frame_dly_cntr <= FRAME_PERIOD; // else if (frame_start) frame_dly_cntr <= FRAME_PERIOD;
else frame_dly_cntr <= frame_dly_cntr - 1; // else frame_dly_cntr <= frame_dly_cntr - 1;
frame_start <= !rst && (frame_dly_cntr == 0); // frame_start <= !rst && (frame_dly_cntr == 0);
frame_start <= !rst && (segment_dly_cntr == 0) && (segments_cntr[1:0] == 0);
if (rst) frame_num <= 0; if (rst) frame_num <= 0;
else if (frame_start) frame_num <= frame_num + 1; else if (frame_start) frame_num <= frame_num + 1;
if (rst) copy_page <= 0; if (rst) copy_page <= 0;
else if (frame_start) copy_page <= !copy_page; // else if (frame_start) copy_page <= !copy_page;
else if (frame_done) copy_page <= !copy_page;
if (rst || copy_done) copy_run <= 0; // remove copy_run completely?
else if (frame_start) copy_run <= 1; // if (rst || copy_done) copy_run <= 0;
// if (rst || frame_done) copy_run <= 0;
// else if (frame_start) copy_run <= 1;
copy_crc <= copy_word == (PACKET_WORDS - 1); copy_crc <= copy_word == (PACKET_WORDS - 1);
if (!copy_run || copy_crc) copy_word <= 0;
else copy_word <= copy_word + 1; // if (!copy_run || copy_crc) copy_word <= 0;
if (!segment_run || copy_crc) copy_word <= 0;
else copy_word <= copy_word + 1;
if (!copy_run) copy_packet <= 0; // if (!copy_run) copy_packet <= 0;
else if (copy_crc) copy_packet <= copy_packet + 1; // else if (copy_crc) copy_packet <= copy_packet + 1;
// else if (copy_crc && segment_run) copy_packet <= copy_packet + 1;
if (rst || frame_done) copy_packet <= 0;
else if (copy_crc && segment_run) copy_packet <= copy_packet + 1;
// if (rst || frame_start) segment_packet <= 0; // if (rst || frame_start) segment_packet <= 0;
// else if (copy_run && copy_crc) segment_packet <= (copy_packet== (FRAME_PACKETS_FULL -1))? 0: (segment_packet + 1); // else if (copy_run && copy_crc) segment_packet <= (copy_packet== (FRAME_PACKETS_FULL -1))? 0: (segment_packet + 1);
...@@ -315,6 +346,9 @@ always @ (posedge mclk) begin ...@@ -315,6 +346,9 @@ always @ (posedge mclk) begin
if (rst || segment_start) segment_packet <= 0; if (rst || segment_start) segment_packet <= 0;
else if (segment_run && copy_crc) segment_packet <= segment_packet + 1; else if (segment_run && copy_crc) segment_packet <= segment_packet + 1;
// if (copy_run) packed_data[copy_wa_full] <= copy_din; // copy_d;
if (segment_run) packed_data[copy_wa_full] <= copy_din; // copy_d;
if (rst) segments_cntr <= 0; if (rst) segments_cntr <= 0;
else if (segment_done) segments_cntr <= (segments_cntr == (SEGMENTS_SEQ - 1)) ? 0: (segments_cntr + 1); else if (segment_done) segments_cntr <= (segments_cntr == (SEGMENTS_SEQ - 1)) ? 0: (segments_cntr + 1);
...@@ -332,12 +366,13 @@ always @ (posedge mclk) begin ...@@ -332,12 +366,13 @@ always @ (posedge mclk) begin
copy_pixels_pix <= copy_pix_or_tel && (copy_packet < FRAME_PACKETS); copy_pixels_pix <= copy_pix_or_tel && (copy_packet < FRAME_PACKETS);
if (frame_start) frame_sum <= 0; if (frame_start) frame_sum <= 0;
else if (copy_pixels_pix) frame_sum <= frame_sum + copy_pxd; else if (copy_pixels_pix) frame_sum <= frame_sum + copy_pxd;
if (copy_run) packed_data[copy_wa_full] <= copy_din; // copy_d;
en_avg <= copy_crc && (copy_packet == (FRAME_PACKETS - 1)); // 1 cycle after last pixel written // en_avg <= copy_crc && (copy_packet == (FRAME_PACKETS - 1)); // 1 cycle after last pixel written
en_avg <= copy_crc_w && (copy_packet == (FRAME_PACKETS - 1)); // 1 cycle after last pixel written
end end
// readout, mclk part // readout, mclk part
...@@ -346,7 +381,9 @@ always @ (posedge mclk) begin ...@@ -346,7 +381,9 @@ always @ (posedge mclk) begin
else if ( segment_done && !start_segm_rd_mclk) segments_ready <= segments_ready + 1; else if ( segment_done && !start_segm_rd_mclk) segments_ready <= segments_ready + 1;
else if (!segment_done && start_segm_rd_mclk) segments_ready <= segments_ready - 1; else if (!segment_done && start_segm_rd_mclk) segments_ready <= segments_ready - 1;
segment_av <= !rst && !sync_lost && (segments_ready >= SEGMENTS_MIN); segment_av_mclk <= !rst && !sync_lost && (segments_ready >= SEGMENTS_MIN);
if (rst) sync_lost <= 0; if (rst) sync_lost <= 0;
else if (segments_ready >= SEGMENTS_MAX) sync_lost <= 1; else if (segments_ready >= SEGMENTS_MAX) sync_lost <= 1;
end end
...@@ -363,8 +400,6 @@ always @ (posedge rst or negedge spi_clk) begin ...@@ -363,8 +400,6 @@ always @ (posedge rst or negedge spi_clk) begin
if (rst) readout_first_bit <= 1; if (rst) readout_first_bit <= 1;
else if (!spi_cs) readout_first_bit <= readout_pre_first_bit; else if (!spi_cs) readout_first_bit <= readout_pre_first_bit;
if (rst) readout_good <= 0;
else if (!spi_cs && readout_first_bit && (readout_word_indx == 0)) readout_good <= readout_good_w;
if (!spi_cs) begin if (!spi_cs) begin
if (readout_first_bit) begin if (readout_first_bit) begin
...@@ -374,6 +409,7 @@ always @ (posedge rst or negedge spi_clk) begin ...@@ -374,6 +409,7 @@ always @ (posedge rst or negedge spi_clk) begin
readout_sr_good <= {readout_sr_good[14:0], 1'b0}; readout_sr_good <= {readout_sr_good[14:0], 1'b0};
readout_sr_bad <= {readout_sr_bad[14:0], 1'b0}; readout_sr_bad <= {readout_sr_bad[14:0], 1'b0};
end end
if (readout_first_bit) readout_sr_good_dbg <= packed_data[readout_address];
end end
if (rst) readout_word_indx <= 0; if (rst) readout_word_indx <= 0;
...@@ -398,13 +434,24 @@ always @ (posedge rst or negedge spi_clk) begin ...@@ -398,13 +434,24 @@ always @ (posedge rst or negedge spi_clk) begin
if (rst) readout_page <= 0; if (rst) readout_page <= 0;
else if (!spi_cs && packet_sent && readout_last_packet && readout_last_segment) readout_page <= !readout_page; else if (!spi_cs && packet_sent && readout_last_packet && readout_last_segment) readout_page <= !readout_page;
if (rst) readout_good <= 0;
else if (!spi_cs && readout_first_bit && (readout_word_indx == 0)) readout_good <= segment_av_mclk || readout_good;
// WRONG!
// else if (segment_done) readout_good <= 0;
else if (!spi_cs && readout_segment_done) readout_good <= 0;
if (!spi_cs) readout_segment_done <= readout_segment_done_w;
//segment_av_mclk
end end
crc16_x16x12x5x0 crc16_x16x12x5x0_i ( crc16_x16x12x5x0 crc16_x16x12x5x0_i (
.clk (mclk), // input .clk (mclk), // input
.srst (!copy_run || copy_crc), // input // .srst (!copy_run || copy_crc), // input
.srst (!segment_run || copy_crc), // input
.en (1'b1), // input .en (1'b1), // input
.din (crc_in), // input[15:0] .din (crc_in), // input[15:0]
.dout (crc_out) // output[15:0] .dout (crc_out) // output[15:0]
......
util_modules/gpio393.v
View file @ f35c087d
...@@ -161,7 +161,7 @@ module gpio393 #( ...@@ -161,7 +161,7 @@ module gpio393 #(
generate generate
genvar i; genvar i;
for (i=0; i < GPIO_N; i=i+1) begin: gpio_block for (i=0; i < GPIO_N; i=i+1) begin: gpio_block
gpio_bit gpio_bit_i ( gpio393_bit gpio_bit_i (
// .rst (rst), // input // .rst (rst), // input
.clk (mclk), // input .clk (mclk), // input
.srst (mrst), // input .srst (mrst), // input
......
util_modules/gpio393_bit.v
View file @ f35c087d
/*! /*!
* <b>Module:</b>gpio393 * <b>Module:</b>gpio393_bit
* @file gpio393.v * @file gpio393.v
* @date 2015-07-06 * @date 2015-07-06
* @author Andrey Filippov * @author Andrey Filippov
...@@ -48,7 +48,7 @@ ...@@ -48,7 +48,7 @@
// 1 0 2 1 1 // 1 0 2 1 1
// 1 1 3 0 0 // 1 1 3 0 0
module gpio_bit ( module gpio393_bit (
// input rst, // global reset // input rst, // global reset
input clk, // system clock input clk, // system clock
input srst, // @posedge clk - sync reset input srst, // @posedge clk - sync reset
......
x393.v
View file @ f35c087d
...@@ -88,8 +88,8 @@ module x393 #( ...@@ -88,8 +88,8 @@ module x393 #(
inout sns4_ctl, inout sns4_ctl,
inout sns4_pg, inout sns4_pg,
`elsif LWIR `elsif LWIR
input [4:0] sns1_dp40, inout [4:0] sns1_dp40,
input [4:0] sns1_dn40, inout [4:0] sns1_dn40,
inout sns1_dp5, // diff MIPI signals (not yet implemented) inout sns1_dp5, // diff MIPI signals (not yet implemented)
inout sns1_dn5, // diff MIPI signals (not yet implemented) inout sns1_dn5, // diff MIPI signals (not yet implemented)
inout [7:6] sns1_dp76, inout [7:6] sns1_dp76,
...@@ -101,8 +101,8 @@ module x393 #( ...@@ -101,8 +101,8 @@ module x393 #(
inout sns1_ctl, inout sns1_ctl,
inout sns1_pg, inout sns1_pg,
input [4:0] sns2_dp40, inout [4:0] sns2_dp40,
input [4:0] sns2_dn40, inout [4:0] sns2_dn40,
inout sns2_dp5, // diff MIPI signals (not yet implemented) inout sns2_dp5, // diff MIPI signals (not yet implemented)
inout sns2_dn5, // diff MIPI signals (not yet implemented) inout sns2_dn5, // diff MIPI signals (not yet implemented)
inout [7:6] sns2_dp76, inout [7:6] sns2_dp76,
...@@ -114,8 +114,8 @@ module x393 #( ...@@ -114,8 +114,8 @@ module x393 #(
inout sns2_ctl, inout sns2_ctl,
inout sns2_pg, inout sns2_pg,
input [4:0] sns3_dp40, inout [4:0] sns3_dp40,
input [4:0] sns3_dn40, inout [4:0] sns3_dn40,
inout sns3_dp5, // diff MIPI signals (not yet implemented) inout sns3_dp5, // diff MIPI signals (not yet implemented)
inout sns3_dn5, // diff MIPI signals (not yet implemented) inout sns3_dn5, // diff MIPI signals (not yet implemented)
inout [7:6] sns3_dp76, inout [7:6] sns3_dp76,
...@@ -127,8 +127,8 @@ module x393 #( ...@@ -127,8 +127,8 @@ module x393 #(
inout sns3_ctl, inout sns3_ctl,
inout sns3_pg, inout sns3_pg,
input [4:0] sns4_dp40, inout [4:0] sns4_dp40,
input [4:0] sns4_dn40, inout [4:0] sns4_dn40,
inout sns4_dp5, // diff MIPI signals (not yet implemented) inout sns4_dp5, // diff MIPI signals (not yet implemented)
inout sns4_dn5, // diff MIPI signals (not yet implemented) inout sns4_dn5, // diff MIPI signals (not yet implemented)
inout [7:6] sns4_dp76, inout [7:6] sns4_dp76,
......
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