Commit f026775f authored by Andrey Filippov's avatar Andrey Filippov
Browse files

fixed a bug caused by a counter-intuitive CLKINSEL in MMCME2_ADV

parent 50c837f9

.project

+4 −4
Original line number Diff line number Diff line
@@ -92,7 +92,7 @@ 
		<link>

			<name>vivado_logs/VivadoSynthesis.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150719165235946.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150719200102645.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
@@ -102,7 +102,7 @@ 
		<link>

			<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20150719165235946.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20150719200102645.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoTimingReportImplemented.log</name>
@@ -112,7 +112,7 @@ 
		<link>

			<name>vivado_logs/VivadoTimingReportSynthesis.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20150719165235946.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20150719200102645.log</location>

		</link>

		<link>

			<name>vivado_state/x393-opt-phys.dcp</name>
@@ -132,7 +132,7 @@ 
		<link>

			<name>vivado_state/x393-synth.dcp</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_state/x393-synth-20150719165235946.dcp</location>

			<location>/home/andrey/git/x393/vivado_state/x393-synth-20150719200102645.dcp</location>

		</link>

	</linkedResources>

</projectDescription>

memctrl/phy/phy_top.v

+1 −1
Original line number Diff line number Diff line
@@ -335,7 +335,7 @@ BUFG mclk_i (.O(mclk),.I(mclk_pre) ); 
    ) mmcm_phase_cntr_i (

        .clkin1              (clk_in), // input

        .clkin2              (1'b0), // input

        .clkinsel            (1'b0), // input

        .sel_clk2            (1'b0), // input

        .clkfbin             (clk_fb), // input

//        .rst                 (rst), // input

        .rst                 (rst_in), // input

sensor/sens_parallel12.v

+1 −1
Original line number Diff line number Diff line
@@ -595,7 +595,7 @@ module sens_parallel12 #( 
    ) mmcm_phase_cntr_i (

        .clkin1              (pclk),            // input

        .clkin2              (ibpf),            // input

        .clkinsel            (sel_ext_clk),     // input

        .sel_clk2            (sel_ext_clk),     // input

        .clkfbin             (clk_fb),          // input

        .rst                 (rst_mmcm),        // input

        .pwrdwn              (1'b0),            // input

util_modules/clocks393.v

+0 −1
Original line number Diff line number Diff line
@@ -121,7 +121,6 @@ module clocks393#( 
    wire memclk_rst = reset_clk[4];

    wire ffclk0_rst = reset_clk[5];

    wire ffclk1_rst = reset_clk[6];

    

    always @ (posedge mclk or posedge rst) begin

        if (rst)             reset_clk <= 0;

        else if (set_ctrl_w) reset_clk <= {cmd_data[10:8], cmd_data[3:0]};

wrap/mmcm_phase_cntr.v

+2 −2
Original line number Diff line number Diff line
@@ -73,7 +73,7 @@ module mmcm_phase_cntr#( 
(

    input clkin1,   // General clock input

    input clkin2,   // Alternative clock input

    input clkinsel, // Clock input select

    input sel_clk2, // Clock input select (inverted from MMCME2_ADV !!!)

    input clkfbin,  // Feedback clock input

    input rst,      // asynchronous reset input

    input pwrdwn,   // power down input
@@ -209,7 +209,7 @@ module mmcm_phase_cntr#( 
        .CLKFBIN        (clkfbin), // input

        .CLKIN1         (clkin1), // input

        .CLKIN2         (clkin2), // input

        .CLKINSEL       (clkinsel), // input Select CLKIN1

        .CLKINSEL       (~sel_clk2), // input  0: Select CLKIN2, 1: Select CLKIN1 !!!!!!!!!!!!! 

        .DADDR             (7'b0), // Dynamic reconfiguration address (input[6:0])

        .DCLK              (1'b0), // Dynamic reconfiguration clock input

        .DEN               (1'b0), // Dynamic reconfiguration enable input