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Commit ed32ff53 authored by Andrey Filippov's avatar Andrey Filippov
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hardware debugging/testing

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.project
View file @ ed32ff53
...@@ -62,42 +62,42 @@ ...@@ -62,42 +62,42 @@
<link> <link>
<name>vivado_logs/VivadoBitstream.log</name> <name>vivado_logs/VivadoBitstream.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20150831152219741.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20150903211518672.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOpt.log</name> <name>vivado_logs/VivadoOpt.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20150831152219741.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20150903211518672.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOptPhys.log</name> <name>vivado_logs/VivadoOptPhys.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20150831152219741.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20150903211518672.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOptPower.log</name> <name>vivado_logs/VivadoOptPower.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20150831152219741.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20150903211518672.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoPlace.log</name> <name>vivado_logs/VivadoPlace.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20150831152219741.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20150903211518672.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoRoute.log</name> <name>vivado_logs/VivadoRoute.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20150831152219741.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20150903211518672.log</location>
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<name>vivado_logs/VivadoSynthesis.log</name> <name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150831151630695.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150903211518672.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name> <name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20150831152219741.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20150903211518672.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name> <name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
...@@ -107,32 +107,32 @@ ...@@ -107,32 +107,32 @@
<link> <link>
<name>vivado_logs/VivadoTimingReportImplemented.log</name> <name>vivado_logs/VivadoTimingReportImplemented.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportImplemented-20150831152219741.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportImplemented-20150903211518672.log</location>
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<name>vivado_logs/VivadoTimingReportSynthesis.log</name> <name>vivado_logs/VivadoTimingReportSynthesis.log</name>
<type>1</type> <type>1</type>
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</link> </link>
<link> <link>
<name>vivado_state/x393-opt-phys.dcp</name> <name>vivado_state/x393-opt-phys.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_state/x393-opt-phys-20150831152219741.dcp</location> <location>/home/andrey/git/x393/vivado_state/x393-opt-phys-20150903211518672.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/x393-place.dcp</name> <name>vivado_state/x393-place.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_state/x393-place-20150831152219741.dcp</location> <location>/home/andrey/git/x393/vivado_state/x393-place-20150903211518672.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/x393-route.dcp</name> <name>vivado_state/x393-route.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_state/x393-route-20150831152219741.dcp</location> <location>/home/andrey/git/x393/vivado_state/x393-route-20150903211518672.dcp</location>
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<location>/home/andrey/git/x393/vivado_state/x393-synth-20150831151630695.dcp</location> <location>/home/andrey/git/x393/vivado_state/x393-synth-20150903211518672.dcp</location>
</link> </link>
</linkedResources> </linkedResources>
</projectDescription> </projectDescription>
compressor_jp/compressor393.v
View file @ ed32ff53
...@@ -111,6 +111,9 @@ module compressor393 # ( ...@@ -111,6 +111,9 @@ module compressor393 # (
parameter CMPRS_AFIMUX_WIDTH = 26, // maximal for status: currently only works with 26) parameter CMPRS_AFIMUX_WIDTH = 26, // maximal for status: currently only works with 26)
parameter CMPRS_AFIMUX_CYCBITS = 3, parameter CMPRS_AFIMUX_CYCBITS = 3,
parameter AFI_MUX_BUF_LATENCY = 4'd2 // buffers read latency from fifo_ren* to fifo_rdata* valid : 2 if no register layers are used parameter AFI_MUX_BUF_LATENCY = 4'd2 // buffers read latency from fifo_ren* to fifo_rdata* valid : 2 if no register layers are used
`ifdef DEBUG_RING
,parameter DEBUG_CMD_LATENCY = 2
`endif
)( )(
// input rst, // global reset // input rst, // global reset
...@@ -231,6 +234,12 @@ module compressor393 # ( ...@@ -231,6 +234,12 @@ module compressor393 # (
input [ 7:0] afi1_wcount, input [ 7:0] afi1_wcount,
input [ 5:0] afi1_wacount, input [ 5:0] afi1_wacount,
output afi1_wrissuecap1en output afi1_wrissuecap1en
`ifdef DEBUG_RING
,output debug_do, // output to the debug ring
input debug_sl, // 0 - idle, (1,0) - shift, (1,1) - load
input debug_di // input from the debug ring
`endif
); );
wire [47:0] status_ad_mux; wire [47:0] status_ad_mux;
......
fpga_version.vh
View file @ ed32ff53
parameter FPGA_VERSION = 32'h03930003; parameter FPGA_VERSION = 32'h0393000f;
\ No newline at end of file
includes/x393_parameters.vh
View file @ ed32ff53
...@@ -724,6 +724,18 @@ ...@@ -724,6 +724,18 @@
parameter CLK_CNTRL = 0, parameter CLK_CNTRL = 0,
parameter CLK_STATUS = 1, parameter CLK_STATUS = 1,
`ifdef DEBUG_RING
// Debug module (read/write serial ring)
parameter DEBUG_ADDR = 'h710, //..'h713
parameter DEBUG_MASK = 'h7fc,
parameter DEBUG_STATUS_REG_ADDR = 'hfc, // address where status can be read out
parameter DEBUG_READ_REG_ADDR = 'hfd, // read 32-bit received shifted data
parameter DEBUG_SHIFT_DATA = 'h0, // shift i/o data by 32 bits
parameter DEBUG_LOAD = 'h1, // parallel load of the distributed shift registe (both ways)
parameter DEBUG_SET_STATUS = 'h2, // program status (mode 3?)
parameter DEBUG_CMD_LATENCY = 2, // >0 extra registers in the debug_sl (distriburted in parallel)
`endif
parameter CLKIN_PERIOD_AXIHP = 20, //ns >1.25, 600<Fvco<1200 parameter CLKIN_PERIOD_AXIHP = 20, //ns >1.25, 600<Fvco<1200
parameter DIVCLK_DIVIDE_AXIHP = 1, parameter DIVCLK_DIVIDE_AXIHP = 1,
parameter CLKFBOUT_MULT_AXIHP = 18, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE parameter CLKFBOUT_MULT_AXIHP = 18, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
......
py393/x393_camsync.py
View file @ ed32ff53
...@@ -157,14 +157,15 @@ class X393Camsync(object): ...@@ -157,14 +157,15 @@ class X393Camsync(object):
@param delay - delay value in 10 ns steps - max 42.95 sec (or list/tuple if different for channels) @param delay - delay value in 10 ns steps - max 42.95 sec (or list/tuple if different for channels)
""" """
self.set_camsync_period (0) # reset circuitry self.set_camsync_period (0) # reset circuitry
self.set_gpio_ports (port_a = True) self.X393_gpio.set_gpio_ports (port_a = True)
self.set_camsync_mode ( self.set_camsync_mode (
en = True, en = True,
snd_en = True, en_snd = True,
en_ts_external = external_timestamp, en_ts_external = external_timestamp,
triggered_mode = trigger_mode, triggered_mode = trigger_mode,
master_chn = 0, master_chn = 0,
chn_en = sensor_mask) chn_en = sensor_mask)
# setting I/Os after camsync is enabled # setting I/Os after camsync is enabled
self.reset_camsync_inout (is_out = 0) # reset input selection self.reset_camsync_inout (is_out = 0) # reset input selection
if ext_trigger_mode : if ext_trigger_mode :
...@@ -180,6 +181,8 @@ class X393Camsync(object): ...@@ -180,6 +181,8 @@ class X393Camsync(object):
if not isinstance(camsync_delay,list) or isinstance(camsync_delay,tuple): if not isinstance(camsync_delay,list) or isinstance(camsync_delay,tuple):
camsync_delay = (camsync_delay, camsync_delay, camsync_delay, camsync_delay) camsync_delay = (camsync_delay, camsync_delay, camsync_delay, camsync_delay)
for i, dly in enumerate (camsync_delay): for i, dly in enumerate (camsync_delay):
if not dly is None:
self.set_camsync_delay(sub_chn = i, delay = dly) self.set_camsync_delay(sub_chn = i, delay = dly)
if not camsync_period is None:
self.set_camsync_period (period = camsync_period) # set period (start generating) - in 353 was after everything else was set self.set_camsync_period (period = camsync_period) # set period (start generating) - in 353 was after everything else was set
py393/x393_cmprs.py
View file @ ed32ff53
...@@ -390,7 +390,7 @@ class X393Cmprs(object): ...@@ -390,7 +390,7 @@ class X393Cmprs(object):
print ( "bayer = ",bayer) print ( "bayer = ",bayer)
print ( "focus_mode = ",focus_mode) print ( "focus_mode = ",focus_mode)
self.compressor_control( self.compressor_control(
num_sensor = num_sensor, # sensor channel number (0..3) chn = num_sensor, # sensor channel number (0..3)
qbank = qbank, # [6:3] quantization table page qbank = qbank, # [6:3] quantization table page
dc_sub = dc_sub, # [8:7] subtract DC dc_sub = dc_sub, # [8:7] subtract DC
cmode = cmode, # [13:9] color mode: cmode = cmode, # [13:9] color mode:
...@@ -399,18 +399,18 @@ class X393Cmprs(object): ...@@ -399,18 +399,18 @@ class X393Cmprs(object):
focus_mode = focus_mode) # [23:21] Set focus mode focus_mode = focus_mode) # [23:21] Set focus mode
self.compressor_format( self.compressor_format(
num_sensor = num_sensor, # sensor channel number (0..3) chn = num_sensor, # sensor channel number (0..3)
num_macro_cols_m1 = num_macro_cols_m1, # number of macroblock colums minus 1 num_macro_cols_m1 = num_macro_cols_m1, # number of macroblock colums minus 1
num_macro_rows_m1 = num_macro_rows_m1, # number of macroblock rows minus 1 num_macro_rows_m1 = num_macro_rows_m1, # number of macroblock rows minus 1
left_margin = left_margin) # left margin of the first pixel (0..31) for 32-pixel wide colums in memory access left_margin = left_margin) # left margin of the first pixel (0..31) for 32-pixel wide colums in memory access
self.compressor_color_saturation( self.compressor_color_saturation(
num_sensor = num_sensor, # sensor channel number (0..3) chn = num_sensor, # sensor channel number (0..3)
colorsat_blue = colorsat_blue, # color saturation for blue (10 bits) #'h90 for 100% colorsat_blue = colorsat_blue, # color saturation for blue (10 bits) #'h90 for 100%
colorsat_red = colorsat_red) # color saturation for red (10 bits) # 'b6 for 100% colorsat_red = colorsat_red) # color saturation for red (10 bits) # 'b6 for 100%
self.compressor_coring( self.compressor_coring(
num_sensor = num_sensor, # sensor channel number (0..3) chn = num_sensor, # sensor channel number (0..3)
coring = coring); # coring value coring = coring); # coring value
py393/x393_sens_cmprs.py
View file @ ed32ff53
This diff is collapsed.
py393/x393_sensor.py
View file @ ed32ff53
...@@ -97,6 +97,72 @@ class X393Sensor(object): ...@@ -97,6 +97,72 @@ class X393Sensor(object):
vrlg.SENSIO_STATUS, vrlg.SENSIO_STATUS,
mode, mode,
seq_num)# //MCONTR_PHY_STATUS_REG_ADDR= 'h0, seq_num)# //MCONTR_PHY_STATUS_REG_ADDR= 'h0,
def get_status_sensor_io ( self,
num_sensor):
"""
Read sensor_io status word (no sync)
@param num_sensor - number of the sensor port (0..3)
@return sesnor_io status
"""
return self.x393_axi_tasks.read_status(
address=(vrlg.SENSI2C_STATUS_REG_BASE + num_sensor * vrlg.SENSI2C_STATUS_REG_INC + vrlg.SENSIO_STATUS_REG_REL))
def print_status_sensor_io (self,
num_sensor):
"""
Print sensor_io status word (no sync)
@param num_sensor - number of the sensor port (0..3)
"""
status= self.get_status_sensor_io(num_sensor)
print ("print_status_sensor_io(%d):"%(num_sensor))
#last_in_line_1cyc_mclk, dout_valid_1cyc_mclk
print (" last_in_line_1cyc_mclk = %d"%((status>>23) & 1))
print (" dout_valid_1cyc_mclk = %d"%((status>>22) & 1))
print (" alive_hist0_gr = %d"%((status>>21) & 1))
print (" alive_hist0_rq = %d"%((status>>20) & 1))
print (" sof_out_mclk = %d"%((status>>19) & 1))
print (" eof_mclk = %d"%((status>>18) & 1))
print (" sof_mclk = %d"%((status>>17) & 1))
print (" sol_mclk = %d"%((status>>16) & 1))
print (" vact_alive = %d"%((status>>15) & 1))
print (" hact_ext_alive = %d"%((status>>14) & 1))
print (" hact_alive = %d"%((status>>13) & 1))
print (" locked_pxd_mmcm = %d"%((status>>12) & 1))
print (" clkin_pxd_stopped_mmcm = %d"%((status>>11) & 1))
print (" clkfb_pxd_stopped_mmcm = %d"%((status>>10) & 1))
print (" ps_rdy = %d"%((status>> 9) & 1))
print (" ps_out = %d"%((status>> 0) & 0xff))
print (" xfpgatdo = %d"%((status>>25) & 1))
print (" senspgmin = %d"%((status>>24) & 1))
print (" seq = %d"%((status>>26) & 0x3f))
#vact_alive, hact_ext_alive, hact_alive
def get_status_sensor_i2c ( self,
num_sensor):
"""
Read sensor_i2c status word (no sync)
@param num_sensor - number of the sensor port (0..3)
@return sesnor_io status
"""
return self.x393_axi_tasks.read_status(
address=(vrlg.SENSI2C_STATUS_REG_BASE + num_sensor * vrlg.SENSI2C_STATUS_REG_INC + vrlg.SENSI2C_STATUS_REG_REL))
def print_status_sensor_i2c (self,
num_sensor):
"""
Print sensor_i2c status word (no sync)
@param num_sensor - number of the sensor port (0..3)
"""
status= self.get_status_sensor_i2c(num_sensor)
print ("print_status_sensor_i2c(%d):"%(num_sensor))
print (" reset_on = %d"%((status>> 7) & 1))
print (" req_clr = %d"%((status>> 6) & 1))
print (" alive_fs = %d"%((status>> 5) & 1))
print (" busy = %d"%((status>> 4) & 1))
print (" frame_num = %d"%((status>> 0) & 0xf))
print (" sda_in = %d"%((status>>25) & 1))
print (" scl_in = %d"%((status>>24) & 1))
print (" seq = %d"%((status>>26) & 0x3f))
# Functions used by sensor-related tasks # Functions used by sensor-related tasks
def func_sensor_mode (self, def func_sensor_mode (self,
...@@ -497,7 +563,7 @@ class X393Sensor(object): ...@@ -497,7 +563,7 @@ class X393Sensor(object):
@param fatzero_out (16 bits) @param fatzero_out (16 bits)
@param post_scale (4 bits) - shift of the result @param post_scale (4 bits) - shift of the result
""" """
def func_lens_data (self, def func_lens_data (
num_sensor, num_sensor,
addr, addr,
data, data,
...@@ -653,8 +719,17 @@ class X393Sensor(object): ...@@ -653,8 +719,17 @@ class X393Sensor(object):
""" """
raddr = (vrlg.HISTOGRAM_RADDR0, vrlg.HISTOGRAM_RADDR1, vrlg.HISTOGRAM_RADDR2, vrlg.HISTOGRAM_RADDR3) raddr = (vrlg.HISTOGRAM_RADDR0, vrlg.HISTOGRAM_RADDR1, vrlg.HISTOGRAM_RADDR2, vrlg.HISTOGRAM_RADDR3)
reg_addr = (vrlg.SENSOR_GROUP_ADDR + num_sensor * vrlg.SENSOR_BASE_INC) + raddr[subchannel & 3] reg_addr = (vrlg.SENSOR_GROUP_ADDR + num_sensor * vrlg.SENSOR_BASE_INC) + raddr[subchannel & 3]
self.x393_axi_tasks.write_control_register(reg_addr + vrlg.HISTOGRAM_LEFT_TOP, ((top & 0xffff) << 16) | (left & 0xff)) if self.DEBUG_MODE:
self.x393_axi_tasks.write_control_register(reg_addr + vrlg.HISTOGRAM_WIDTH_HEIGHT, ((height_m1 & 0xffff) << 16) | (width_m1 & 0xff)) print("set_sensor_histogram_window():")
print("num_sensor = ", num_sensor)
print("subchannel = ", subchannel)
print("left = ", left)
print("top = ", top)
print("width_m1 = ", width_m1)
print("height_m1 = ", height_m1)
self.x393_axi_tasks.write_control_register(reg_addr + vrlg.HISTOGRAM_LEFT_TOP, ((top & 0xffff) << 16) | (left & 0xffff))
self.x393_axi_tasks.write_control_register(reg_addr + vrlg.HISTOGRAM_WIDTH_HEIGHT, ((height_m1 & 0xffff) << 16) | (width_m1 & 0xffff))
def set_sensor_histogram_saxi (self, def set_sensor_histogram_saxi (self,
en, en,
nrst, nrst,
...@@ -667,6 +742,12 @@ class X393Sensor(object): ...@@ -667,6 +742,12 @@ class X393Sensor(object):
@param confirm_write - wait for the write confirmed (over B channel) before switching channels @param confirm_write - wait for the write confirmed (over B channel) before switching channels
@param cache_mode AXI cache mode, default should be 4'h3 @param cache_mode AXI cache mode, default should be 4'h3
""" """
if self.DEBUG_MODE:
print("set_sensor_histogram_saxi():")
print("en = ", en)
print("nrst = ", nrst)
print("confirm_write = ", confirm_write)
print("cache_mode= ", cache_mode)
data = 0; data = 0;
data |= (0,1)[en] << vrlg.HIST_SAXI_EN data |= (0,1)[en] << vrlg.HIST_SAXI_EN
data |= (0,1)[nrst] << vrlg.HIST_SAXI_NRESET data |= (0,1)[nrst] << vrlg.HIST_SAXI_NRESET
...@@ -684,6 +765,11 @@ class X393Sensor(object): ...@@ -684,6 +765,11 @@ class X393Sensor(object):
@param num_sub_sensor - sub-sensor attached to the same port through multiplexer (0..3) @param num_sub_sensor - sub-sensor attached to the same port through multiplexer (0..3)
@param page - system memory page address (in 4KB units) @param page - system memory page address (in 4KB units)
""" """
if self.DEBUG_MODE:
print("set_sensor_histogram_saxi_addr():")
print("num_sensor = ", num_sensor)
print("subchannel = ", subchannel)
print("page = ", page)
channel = ((num_sensor & 3) << 2) + (subchannel & 3) channel = ((num_sensor & 3) << 2) + (subchannel & 3)
self.x393_axi_tasks.write_control_register(vrlg.SENSOR_GROUP_ADDR + vrlg.HIST_SAXI_ADDR_REL + channel,page) self.x393_axi_tasks.write_control_register(vrlg.SENSOR_GROUP_ADDR + vrlg.HIST_SAXI_ADDR_REL + channel,page)
......
sensor/sens_histogram.v
View file @ ed32ff53
...@@ -35,6 +35,7 @@ module sens_histogram #( ...@@ -35,6 +35,7 @@ module sens_histogram #(
input pclk, // global clock input, pixel rate (96MHz for MT9P006) input pclk, // global clock input, pixel rate (96MHz for MT9P006)
input pclk2x, input pclk2x,
input sof, input sof,
input eof,
input hact, input hact,
input [7:0] hist_di, // 8-bit pixel data input [7:0] hist_di, // 8-bit pixel data
...@@ -48,6 +49,7 @@ module sens_histogram #( ...@@ -48,6 +49,7 @@ module sens_histogram #(
input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3 input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
input cmd_stb, // strobe (with first byte) for the command a/d input cmd_stb, // strobe (with first byte) for the command a/d
input monochrome // tie to 0 to reduce hardware input monochrome // tie to 0 to reduce hardware
,output debug_mclk
); );
localparam PXD_2X_LATENCY = 2; localparam PXD_2X_LATENCY = 2;
reg hist_bank_pclk; reg hist_bank_pclk;
...@@ -101,7 +103,7 @@ module sens_histogram #( ...@@ -101,7 +103,7 @@ module sens_histogram #(
reg top_margin; // above (before) active window reg top_margin; // above (before) active window
reg hist_done; // @pclk single cycle reg hist_done; // @pclk single cycle
wire hist_done_mclk; wire hist_done_mclk;
reg vert_woi; // vertically in window reg vert_woi; // vertically in window TESTED ACTIVE
reg left_margin; // left of (before) active window reg left_margin; // left of (before) active window
reg [2:0] woi; // @ pclk2x - inside WOI (and delayed reg [2:0] woi; // @ pclk2x - inside WOI (and delayed
reg hor_woi; // vertically in window reg hor_woi; // vertically in window
...@@ -123,6 +125,8 @@ module sens_histogram #( ...@@ -123,6 +125,8 @@ module sens_histogram #(
reg hist_xfer_busy; // @pclk, during histogram readout , immediately after woi (no gaps) reg hist_xfer_busy; // @pclk, during histogram readout , immediately after woi (no gaps)
reg wait_readout; // only used in NOBUF mode, in outher modes readout is expected to be always finished in time reg wait_readout; // only used in NOBUF mode, in outher modes readout is expected to be always finished in time
reg debug_vert_woi_r;
assign set_left_top_w = pio_stb && (pio_addr == HISTOGRAM_LEFT_TOP ); assign set_left_top_w = pio_stb && (pio_addr == HISTOGRAM_LEFT_TOP );
assign set_width_height_w = pio_stb && (pio_addr == HISTOGRAM_WIDTH_HEIGHT ); assign set_width_height_w = pio_stb && (pio_addr == HISTOGRAM_WIDTH_HEIGHT );
...@@ -135,7 +139,7 @@ module sens_histogram #( ...@@ -135,7 +139,7 @@ module sens_histogram #(
assign hist_xfer_done_mclk = hist_out_d && !hist_out && hist_en; assign hist_xfer_done_mclk = hist_out_d && !hist_out && hist_en;
//AF2015-new mod //AF2015-new mod
wire line_start_w = hact && !hact_d[0]; wire line_start_w = hact && !hact_d[0]; // // tested active
reg pre_first_line; reg pre_first_line;
reg frame_active; // until done reg frame_active; // until done
reg hist_en_pclk2x; reg hist_en_pclk2x;
...@@ -157,6 +161,9 @@ module sens_histogram #( ...@@ -157,6 +161,9 @@ module sens_histogram #(
reg monochrome_pclk; reg monochrome_pclk;
reg monochrome_2x; reg monochrome_2x;
// assign debug_mclk = hist_done_mclk;
// assign debug_mclk = set_width_height_w;
always @ (posedge pclk) begin always @ (posedge pclk) begin
if (!hact) pxd_wa <= 0; if (!hact) pxd_wa <= 0;
else pxd_wa <= pxd_wa + 1; else pxd_wa <= pxd_wa + 1;
...@@ -196,7 +203,10 @@ module sens_histogram #( ...@@ -196,7 +203,10 @@ module sens_histogram #(
if (!en ||(pre_first_line && !hact)) vert_woi <= 0; if (!en ||(pre_first_line && !hact)) vert_woi <= 0;
else if (vcntr_zero_w & line_start_w) vert_woi <= top_margin; else if (vcntr_zero_w & line_start_w) vert_woi <= top_margin;
hist_done <= vcntr_zero_w && vert_woi && line_start_w; debug_vert_woi_r <= vcntr_zero_w && vert_woi; // vert_woi;
// hist_done <= vcntr_zero_w && vert_woi && line_start_w; // hist done never asserted, line_start_w - active
hist_done <= vert_woi && (eof || (vcntr_zero_w && line_start_w)); // hist done never asserted, line_start_w - active
if (!en || hist_done) frame_active <= 0; if (!en || hist_done) frame_active <= 0;
else if (sof && en_new) frame_active <= 1; else if (sof && en_new) frame_active <= 1;
...@@ -338,6 +348,17 @@ module sens_histogram #( ...@@ -338,6 +348,17 @@ module sens_histogram #(
end end
pulse_cross_clock pulse_cross_clock_debug_mclk_i (
.rst (prst), // input
.src_clk (pclk), // input
.dst_clk (mclk), // input
// .in_pulse (vert_woi && !debug_vert_woi_r), // line_start_w), // input vcntr_zero_w
// .in_pulse (vcntr_zero_w && !debug_vert_woi_r), // line_start_w), // input
.in_pulse (vcntr_zero_w && vert_woi && !debug_vert_woi_r), // line_start_w), // input
.out_pulse (debug_mclk), // output
.busy() // output
);
cmd_deser #( cmd_deser #(
.ADDR (HISTOGRAM_ADDR), .ADDR (HISTOGRAM_ADDR),
......
sensor/sens_parallel12.v
View file @ ed32ff53
...@@ -75,8 +75,8 @@ module sens_parallel12 #( ...@@ -75,8 +75,8 @@ module sens_parallel12 #(
parameter SENS_REF_JITTER2 = 0.010, parameter SENS_REF_JITTER2 = 0.010,
parameter SENS_SS_EN = "FALSE", // Enables Spread Spectrum mode parameter SENS_SS_EN = "FALSE", // Enables Spread Spectrum mode
parameter SENS_SS_MODE = "CENTER_HIGH",//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW" parameter SENS_SS_MODE = "CENTER_HIGH",//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW"
parameter SENS_SS_MOD_PERIOD = 10000 // integer 4000-40000 - SS modulation period in ns parameter SENS_SS_MOD_PERIOD = 10000, // integer 4000-40000 - SS modulation period in ns
parameter STATUS_ALIVE_WIDTH = 4
)( )(
// input rst, // input rst,
input pclk, // global clock input, pixel rate (96MHz for MT9P006) input pclk, // global clock input, pixel rate (96MHz for MT9P006)
...@@ -105,6 +105,8 @@ module sens_parallel12 #( ...@@ -105,6 +105,8 @@ module sens_parallel12 #(
output reg vact_out, output reg vact_out,
output hact_out, output hact_out,
input [STATUS_ALIVE_WIDTH-1:0] status_alive_1cyc, //extra toggle @mclk bits to report with status
// JTAG to program 10359 // JTAG to program 10359
// input xpgmen, // enable programming mode for external FPGA // input xpgmen, // enable programming mode for external FPGA
// input xfpgaprog, // PROG_B to be sent to an external FPGA // input xfpgaprog, // PROG_B to be sent to an external FPGA
...@@ -171,7 +173,7 @@ module sens_parallel12 #( ...@@ -171,7 +173,7 @@ module sens_parallel12 #(
wire [14:0] status; wire [17:0] status;
wire cmd_we; wire cmd_we;
wire [2:0] cmd_a; wire [2:0] cmd_a;
...@@ -189,9 +191,23 @@ module sens_parallel12 #( ...@@ -189,9 +191,23 @@ module sens_parallel12 #(
wire hact_ext; // received hact signal wire hact_ext; // received hact signal
reg hact_ext_r; // received hact signal, delayed by 1 clock reg hact_ext_r; // received hact signal, delayed by 1 clock
reg hact_r; // received or regenerated hact reg hact_r; // received or regenerated hact
// for debug/test alive
reg vact_r;
reg hact_r2;
wire vact_a_mclk;
wire hact_ext_a_mclk;
wire hact_a_mclk;
reg vact_alive;
reg hact_ext_alive;
reg hact_alive;
reg [STATUS_ALIVE_WIDTH-1:0] status_alive;
assign set_pxd_delay = set_idelay[2:0]; assign set_pxd_delay = set_idelay[2:0];
assign set_other_delay = set_idelay[3]; assign set_other_delay = set_idelay[3];
assign status = {locked_pxd_mmcm,clkin_pxd_stopped_mmcm,clkfb_pxd_stopped_mmcm,xfpgadone,ps_rdy, ps_out,xfpgatdo,senspgmin}; assign status = {vact_alive, hact_ext_alive, hact_alive, locked_pxd_mmcm,
clkin_pxd_stopped_mmcm, clkfb_pxd_stopped_mmcm, xfpgadone,
ps_rdy, ps_out, xfpgatdo, senspgmin};
assign hact_out = hact_r; assign hact_out = hact_r;
assign iaro = trigger_mode? ~trig : iaro_soft; assign iaro = trigger_mode? ~trig : iaro_soft;
...@@ -285,6 +301,26 @@ module sens_parallel12 #( ...@@ -285,6 +301,26 @@ module sens_parallel12 #(
pxd_out <= pxd_out_pre; pxd_out <= pxd_out_pre;
vact_out <= vact_out_pre; vact_out <= vact_out_pre;
// for debug/test alive
vact_r <= vact_out_pre;
hact_r2 <= hact_r;
end
// for debug/test alive
always @(posedge mclk) begin
if (mclk_rst || set_status_r) vact_alive <= 0;
else if (vact_a_mclk) vact_alive <= 1;
if (mclk_rst || set_status_r) hact_ext_alive <= 0;
else if (hact_ext_a_mclk) hact_ext_alive <= 1;
if (mclk_rst || set_status_r) hact_alive <= 0;
else if (hact_a_mclk) hact_alive <= 1;
if (mclk_rst || set_status_r) status_alive <= 0;
else status_alive <= status_alive | status_alive_1cyc;
end end
/* /*
...@@ -346,14 +382,14 @@ module sens_parallel12 #( ...@@ -346,14 +382,14 @@ module sens_parallel12 #(
status_generate #( status_generate #(
.STATUS_REG_ADDR(SENSIO_STATUS_REG), .STATUS_REG_ADDR(SENSIO_STATUS_REG),
.PAYLOAD_BITS(15) // STATUS_PAYLOAD_BITS) .PAYLOAD_BITS(15+3+STATUS_ALIVE_WIDTH) // STATUS_PAYLOAD_BITS)
) status_generate_sens_io_i ( ) status_generate_sens_io_i (
.rst (1'b0), // rst), // input .rst (1'b0), // rst), // input
.clk (mclk), // input .clk (mclk), // input
.srst (mclk_rst), // input .srst (mclk_rst), // input
.we (set_status_r), // input .we (set_status_r), // input
.wd (data_r[7:0]), // input[7:0] .wd (data_r[7:0]), // input[7:0]
.status (status), // input[25:0] .status ({status_alive,status}), // input[25:0]
.ad (status_ad), // output[7:0] .ad (status_ad), // output[7:0]
.rq (status_rq), // output .rq (status_rq), // output
.start (status_start) // input .start (status_start) // input
...@@ -691,6 +727,34 @@ module sens_parallel12 #( ...@@ -691,6 +727,34 @@ module sens_parallel12 #(
// BUFR ipclk_bufr_i (.O(ipclk), .CE(), .CLR(), .I(ipclk_pre)); // BUFR ipclk_bufr_i (.O(ipclk), .CE(), .CLR(), .I(ipclk_pre));
// BUFR ipclk2x_bufr_i (.O(ipclk2x), .CE(), .CLR(), .I(ipclk2x_pre)); // BUFR ipclk2x_bufr_i (.O(ipclk2x), .CE(), .CLR(), .I(ipclk2x_pre));
// for debug/test alive
pulse_cross_clock pulse_cross_clock_vact_a_mclk_i (
.rst (irst), // input
.src_clk (ipclk), // input
.dst_clk (mclk), // input
.in_pulse (vact_out_pre && !vact_r), // input
.out_pulse (vact_a_mclk), // output
.busy() // output
);
pulse_cross_clock pulse_cross_clock_hact_ext_a_mclk_i (
.rst (irst), // input
.src_clk (ipclk), // input
.dst_clk (mclk), // input
.in_pulse (hact_ext && !hact_ext_r), // input
.out_pulse (hact_ext_a_mclk), // output
.busy() // output
);
pulse_cross_clock pulse_cross_clock_hact_a_mclk_i (
.rst (irst), // input
.src_clk (ipclk), // input
.dst_clk (mclk), // input
.in_pulse (hact_r && !hact_r2), // input
.out_pulse (hact_a_mclk), // output
.busy() // output
);
endmodule endmodule
sensor/sensor_channel.v
View file @ ed32ff53
This diff is collapsed.
sensor/sensor_i2c.v
View file @ ed32ff53
...@@ -21,14 +21,14 @@ ...@@ -21,14 +21,14 @@
`timescale 1ns/1ps `timescale 1ns/1ps
module sensor_i2c#( module sensor_i2c#(
parameter SENSI2C_ABS_ADDR = 'h300, parameter SENSI2C_ABS_ADDR = 'h410,
parameter SENSI2C_REL_ADDR = 'h310, parameter SENSI2C_REL_ADDR = 'h420,
parameter SENSI2C_ADDR_MASK = 'h7f0, // both for SENSI2C_ABS_ADDR and SENSI2C_REL_ADDR parameter SENSI2C_ADDR_MASK = 'h7f0, // both for SENSI2C_ABS_ADDR and SENSI2C_REL_ADDR
parameter SENSI2C_CTRL_ADDR = 'h320, parameter SENSI2C_CTRL_ADDR = 'h402,
parameter SENSI2C_CTRL_MASK = 'h7fe, parameter SENSI2C_CTRL_MASK = 'h7fe,
parameter SENSI2C_CTRL = 'h0, parameter SENSI2C_CTRL = 'h0,
parameter SENSI2C_STATUS = 'h1, parameter SENSI2C_STATUS = 'h1,
parameter SENSI2C_STATUS_REG = 'h30, parameter SENSI2C_STATUS_REG = 'h20,
// Control register bits // Control register bits
parameter SENSI2C_CMD_RESET = 14, // [14] reset all FIFO (takes 16 clock pulses), also - stops i2c until run command parameter SENSI2C_CMD_RESET = 14, // [14] reset all FIFO (takes 16 clock pulses), also - stops i2c until run command
parameter SENSI2C_CMD_RUN = 13, // [13:12]3 - run i2c, 2 - stop i2c (needed before software i2c), 1,0 - no change to run state parameter SENSI2C_CMD_RUN = 13, // [13:12]3 - run i2c, 2 - stop i2c (needed before software i2c), 1,0 - no change to run state
...@@ -54,7 +54,7 @@ module sensor_i2c#( ...@@ -54,7 +54,7 @@ module sensor_i2c#(
output [7:0] status_ad, // status address/data - up to 5 bytes: A - {seq,status[1:0]} - status[2:9] - status[10:17] - status[18:25] output [7:0] status_ad, // status address/data - up to 5 bytes: A - {seq,status[1:0]} - status[2:9] - status[10:17] - status[18:25]
output status_rq, // input request to send status downstream output status_rq, // input request to send status downstream
input status_start,// Acknowledge of the first status packet byte (address) input status_start,// Acknowledge of the first status packet byte (address)
input frame_sync, // increment/reset frame number input frame_sync, // @posedge mclk increment/reset frame number
// input frame_0, // reset frame number to zero - can be done by soft reset before first enabled frame // input frame_0, // reset frame number to zero - can be done by soft reset before first enabled frame
// output busy, // busy (do not use software i2i) // output busy, // busy (do not use software i2i)
input scl_in, // i2c SCL input input scl_in, // i2c SCL input
...@@ -121,7 +121,7 @@ module sensor_i2c#( ...@@ -121,7 +121,7 @@ module sensor_i2c#(
wire [3:0] frame_num=wpage0[3:0]; wire [3:0] frame_num=wpage0[3:0];
//fifo write pointers (dual port distributed RAM) //fifo write pointers (dual port distributed RAM)
reg [5:0] fifo_wr_pointers [0:15]; // dual ported read? reg [5:0] fifo_wr_pointers_ram [0:15]; // dual ported read?
wire [5:0] fifo_wr_pointers_outw; // pointer dual-ported RAM - write port out, valid next after command wire [5:0] fifo_wr_pointers_outw; // pointer dual-ported RAM - write port out, valid next after command
wire [5:0] fifo_wr_pointers_outr; // pointer dual-ported RAM - read port out wire [5:0] fifo_wr_pointers_outr; // pointer dual-ported RAM - read port out
...@@ -188,16 +188,16 @@ module sensor_i2c#( ...@@ -188,16 +188,16 @@ module sensor_i2c#(
reg wen_fifo; // [1] was not used - we_fifo_wp was used instead reg wen_fifo; // [1] was not used - we_fifo_wp was used instead
assign set_ctrl_w = we_cmd && (wa == SENSI2C_CTRL );// ==0 assign set_ctrl_w = we_cmd && ((wa & ~SENSI2C_CTRL_MASK) == SENSI2C_CTRL );// ==0
assign set_status_w = we_cmd && (wa == SENSI2C_STATUS );// ==0 assign set_status_w = we_cmd && ((wa & ~SENSI2C_CTRL_MASK) == SENSI2C_STATUS );// ==0
assign scl_out=i2c_run? scl_hard: scl_soft ; assign scl_out=i2c_run? scl_hard: scl_soft ;
assign sda_out=i2c_run? sda_hard: sda_soft ; assign sda_out=i2c_run? sda_hard: sda_soft ;
assign scl_en=i2c_run? 1'b1: scl_en_soft ; assign scl_en=i2c_run? 1'b1: scl_en_soft ;
assign sda_en=i2c_run? sda_en_hard: sda_en_soft ; assign sda_en=i2c_run? sda_en_hard: sda_en_soft ;
assign pre_wpage0_inc = (!wen && !(|wen_r) && !wpage0_inc) && (req_clr || reset_on) ; assign pre_wpage0_inc = (!wen && !(|wen_r) && !wpage0_inc[0]) && (req_clr || reset_on) ;
assign fifo_wr_pointers_outw = fifo_wr_pointers[wpage_wr[3:0]]; // valid next after command assign fifo_wr_pointers_outw = fifo_wr_pointers_ram[wpage_wr[3:0]]; // valid next after command
assign fifo_wr_pointers_outr = fifo_wr_pointers[page_r[3:0]]; assign fifo_wr_pointers_outr = fifo_wr_pointers_ram[page_r[3:0]];
// wire we_abs; // wire we_abs;
...@@ -207,6 +207,11 @@ module sensor_i2c#( ...@@ -207,6 +207,11 @@ module sensor_i2c#(
// wire [3:0] wa; // wire [3:0] wa;
assign wen=set_ctrl_w || we_rel || we_abs; //remove set_ctrl_w? assign wen=set_ctrl_w || we_rel || we_abs; //remove set_ctrl_w?
reg alive_fs;
always @ (posedge mclk) begin
if (set_status_w) alive_fs <= 0;
else if (frame_sync) alive_fs <= 1;
end
cmd_deser #( cmd_deser #(
...@@ -232,14 +237,14 @@ module sensor_i2c#( ...@@ -232,14 +237,14 @@ module sensor_i2c#(
status_generate #( status_generate #(
.STATUS_REG_ADDR(SENSI2C_STATUS_REG), .STATUS_REG_ADDR(SENSI2C_STATUS_REG),
.PAYLOAD_BITS(7) // STATUS_PAYLOAD_BITS) .PAYLOAD_BITS(7+3) // STATUS_PAYLOAD_BITS)
) status_generate_sens_i2c_i ( ) status_generate_sens_i2c_i (
.rst (1'b0), // rst), // input .rst (1'b0), // rst), // input
.clk (mclk), // input .clk (mclk), // input
.srst (mrst), // input .srst (mrst), // input
.we (set_status_w), // input .we (set_status_w), // input
.wd (di[7:0]), // input[7:0] .wd (di[7:0]), // input[7:0]
.status ({busy, frame_num, sda_in, scl_in}), // input[25:0] .status ({reset_on, req_clr, alive_fs,busy, frame_num, sda_in, scl_in}), // input[25:0]
.ad (status_ad), // output[7:0] .ad (status_ad), // output[7:0]
.rq (status_rq), // output .rq (status_rq), // output
.start (status_start) // input .start (status_start) // input
...@@ -292,27 +297,28 @@ module sensor_i2c#( ...@@ -292,27 +297,28 @@ module sensor_i2c#(
// write pointer memory // write pointer memory
wpage0_inc <= {wpage0_inc[0],pre_wpage0_inc}; wpage0_inc <= {wpage0_inc[0],pre_wpage0_inc};
// reset pointers in all 16 pages: // reset pointers in all 16 pages:
reset_on <= reset_cmd || (reset_on && !(wpage0_inc && ( wpage0[3:0] == 4'hf))); reset_on <= reset_cmd || (reset_on && !(wpage0_inc[0] && ( wpage0[3:0] == 4'hf)));
// request to clear pointer(s)? for one page - during reset or delayed frame sync (if previous was not finished) // request to clear pointer(s)? for one page - during reset or delayed frame sync (if previous was not finished)
req_clr <= frame_sync || (req_clr && !wpage0_inc); req_clr <= frame_sync || (req_clr && !wpage0_inc[0]);
if (reset_cmd) wpage0 <= 0; if (reset_cmd) wpage0 <= 0;
// else if (frame_0) wpage0 <= 0; // else if (frame_0) wpage0 <= 0;
else if (wpage0_inc) wpage0<=wpage0+1; else if (wpage0_inc[0]) wpage0<=wpage0+1;
if (reset_cmd) wpage_prev<=4'hf; if (reset_cmd) wpage_prev<=4'hf;
else if (wpage0_inc) wpage_prev<=wpage0; else if (wpage0_inc[0]) wpage_prev<=wpage0;
if (we_abs) wpage_wr <= ((wa==wpage_prev)? wpage0[3:0] : wa); if (we_abs) wpage_wr <= ((wa==wpage_prev)? wpage0[3:0] : wa);
else if (we_rel) wpage_wr <= wpage0+wa; else if (we_rel) wpage_wr <= wpage0+wa;
else if (wpage0_inc) wpage_wr <= wpage_prev; // only for erasing? else if (wpage0_inc[0]) wpage_wr <= wpage_prev; // only for erasing?
// we_fifo_wp <= wen || wpage0_inc; // during commands and during reset? // we_fifo_wp <= wen || wpage0_inc; // during commands and during reset?
/// we_fifo_wp <= wen_fifo[0] || wpage0_inc; // during commands and during reset? /// we_fifo_wp <= wen_fifo[0] || wpage0_inc; // during commands and during reset?
// we_fifo_wp <= wen_fifo[0] || we_rel || we_abs; // ?? // we_fifo_wp <= wen_fifo[0] || we_rel || we_abs; // ??
we_fifo_wp <= wen_fifo || we_rel || we_abs; // ?? //// we_fifo_wp <= wen_fifo || we_rel || we_abs; // ??
we_fifo_wp <= wen_fifo || wpage0_inc[0];
// reg [1:0] wen_r; // reg [1:0] wen_r;
// reg [1:0] wen_fifo; // reg [1:0] wen_fifo;
...@@ -322,7 +328,7 @@ module sensor_i2c#( ...@@ -322,7 +328,7 @@ module sensor_i2c#(
if (wen_fifo) fifo_wr_pointers_outw_r[5:0] <= fifo_wr_pointers_outw[5:0]; if (wen_fifo) fifo_wr_pointers_outw_r[5:0] <= fifo_wr_pointers_outw[5:0];
// write to dual-port pointer memory // write to dual-port pointer memory
if (we_fifo_wp) fifo_wr_pointers[wpage_wr] <= wpage0_inc[1]? 6'h0:(fifo_wr_pointers_outw_r[5:0]+1); if (we_fifo_wp) fifo_wr_pointers_ram[wpage_wr] <= wpage0_inc[1]? 6'h0:(fifo_wr_pointers_outw_r[5:0]+1);
fifo_wr_pointers_outr_r[5:0] <= fifo_wr_pointers_outr[5:0]; // just register distri fifo_wr_pointers_outr_r[5:0] <= fifo_wr_pointers_outr[5:0]; // just register distri
// command i2c fifo (RAMB16_S9_S18) // command i2c fifo (RAMB16_S9_S18)
...@@ -342,7 +348,7 @@ module sensor_i2c#( ...@@ -342,7 +348,7 @@ module sensor_i2c#(
if (reset_cmd || page_r_inc[0]) rpointer[5:0] <= 6'h0; if (reset_cmd || page_r_inc[0]) rpointer[5:0] <= 6'h0;
else if (i2c_done) rpointer[5:0] <= rpointer[5:0] + 1; else if (i2c_done) rpointer[5:0] <= rpointer[5:0] + 1;
i2c_run <= !reset_cmd && (i2c_start || (i2c_run && !i2c_done)); i2c_run <= !reset_cmd && !reset_on && (i2c_start || (i2c_run && !i2c_done));
i2c_start <= i2c_enrun && !i2c_run && !i2c_start && (rpointer[5:0]!= fifo_wr_pointers_outr_r[5:0]) && !(|page_r_inc); i2c_start <= i2c_enrun && !i2c_run && !i2c_start && (rpointer[5:0]!= fifo_wr_pointers_outr_r[5:0]) && !(|page_r_inc);
page_r_inc[1:0] <= {page_r_inc[0], page_r_inc[1:0] <= {page_r_inc[0],
!i2c_run && // not i2c in progress !i2c_run && // not i2c in progress
......
sensor/sensor_i2c_io.v
View file @ ed32ff53
...@@ -21,10 +21,10 @@ ...@@ -21,10 +21,10 @@
`timescale 1ns/1ps `timescale 1ns/1ps
module sensor_i2c_io#( module sensor_i2c_io#(
parameter SENSI2C_ABS_ADDR = 'h300, parameter SENSI2C_ABS_ADDR = 'h410,
parameter SENSI2C_REL_ADDR = 'h310, parameter SENSI2C_REL_ADDR = 'h420,
parameter SENSI2C_ADDR_MASK = 'h7f0, // both for SENSI2C_ABS_ADDR and SENSI2C_REL_ADDR parameter SENSI2C_ADDR_MASK = 'h7f0, // both for SENSI2C_ABS_ADDR and SENSI2C_REL_ADDR
parameter SENSI2C_CTRL_ADDR = 'h320, parameter SENSI2C_CTRL_ADDR = 'h402, // channel 0 will be 'h402..'h403
parameter SENSI2C_CTRL_MASK = 'h7fe, parameter SENSI2C_CTRL_MASK = 'h7fe,
parameter SENSI2C_CTRL = 'h0, parameter SENSI2C_CTRL = 'h0,
parameter SENSI2C_STATUS = 'h1, parameter SENSI2C_STATUS = 'h1,
......
sensor/sensors393.v
View file @ ed32ff53
...@@ -224,6 +224,9 @@ module sensors393 #( ...@@ -224,6 +224,9 @@ module sensors393 #(
parameter SENS_SS_EN = "FALSE", // Enables Spread Spectrum mode parameter SENS_SS_EN = "FALSE", // Enables Spread Spectrum mode
parameter SENS_SS_MODE = "CENTER_HIGH",//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW" parameter SENS_SS_MODE = "CENTER_HIGH",//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW"
parameter SENS_SS_MOD_PERIOD = 10000 // integer 4000-40000 - SS modulation period in ns parameter SENS_SS_MOD_PERIOD = 10000 // integer 4000-40000 - SS modulation period in ns
`ifdef DEBUG_RING
,parameter DEBUG_CMD_LATENCY = 2
`endif
) ( ) (
// input rst, // input rst,
...@@ -304,6 +307,11 @@ module sensors393 #( ...@@ -304,6 +307,11 @@ module sensors393 #(
output saxi_bready, // AXI PS Slave GP0 BREADY, input output saxi_bready, // AXI PS Slave GP0 BREADY, input
input [ 5:0] saxi_bid, // AXI PS Slave GP0 BID[5:0], output input [ 5:0] saxi_bid, // AXI PS Slave GP0 BID[5:0], output
input [ 1:0] saxi_bresp // AXI PS Slave GP0 BRESP[1:0], output input [ 1:0] saxi_bresp // AXI PS Slave GP0 BRESP[1:0], output
`ifdef DEBUG_RING
,output debug_do, // output to the debug ring
input debug_sl, // 0 - idle, (1,0) - shift, (1,1) - load
input debug_di // input from the debug ring
`endif
); );
wire [1:0] idelay_ctrl_rdy; // need to connect outputs to prevent optimizing out wire [1:0] idelay_ctrl_rdy; // need to connect outputs to prevent optimizing out
......
system_defines.vh
View file @ ed32ff53
...@@ -2,6 +2,7 @@ ...@@ -2,6 +2,7 @@
`ifndef SYSTEM_DEFINES `ifndef SYSTEM_DEFINES
`define SYSTEM_DEFINES `define SYSTEM_DEFINES
`define PRELOAD_BRAMS `define PRELOAD_BRAMS
`define DEBUG_RING
// Enviroment-dependent options // Enviroment-dependent options
`ifdef IVERILOG `ifdef IVERILOG
`define SIMULATION `define SIMULATION
......
x393.v
View file @ ed32ff53
...@@ -311,6 +311,16 @@ module x393 #( ...@@ -311,6 +311,16 @@ module x393 #(
wire status_clocks_rq; // Other status request wire status_clocks_rq; // Other status request
wire status_clocks_start; // S uppressThisWarning VEditor ****** Other status packet transfer start (currently with 0 latency from status_root_rq) wire status_clocks_start; // S uppressThisWarning VEditor ****** Other status packet transfer start (currently with 0 latency from status_root_rq)
`ifdef DEBUG_RING
wire [7:0] status_debug_ad; // saxi1 - logger data Other status byte-wide address/data
wire status_debug_rq; // Other status request
wire status_debug_start; // S uppressThisWarning VEditor ****** Other status packet transfer start (currently with 0 latency from status_root_rq)
localparam DEBUG_RING_LENGTH = 10;
wire [DEBUG_RING_LENGTH-1:0] debug_ring; // TODO: adjust number of bits
wire debug_sl; // debug shift/load: 0 - idle, (1,0) - shift, (1,1) - load
`endif
// Insert register layer if needed // Insert register layer if needed
reg [7:0] cmd_mcontr_ad; reg [7:0] cmd_mcontr_ad;
reg cmd_mcontr_stb; reg cmd_mcontr_stb;
...@@ -345,6 +355,10 @@ module x393 #( ...@@ -345,6 +355,10 @@ module x393 #(
reg [7:0] cmd_clocks_ad; reg [7:0] cmd_clocks_ad;
reg cmd_clocks_stb; reg cmd_clocks_stb;
`ifdef DEBUG_RING
reg [7:0] cmd_debug_ad;
reg cmd_debug_stb;
`endif
// membridge // membridge
wire frame_start_chn1; // input wire frame_start_chn1; // input
wire next_page_chn1; // input wire next_page_chn1; // input
...@@ -533,6 +547,11 @@ module x393 #( ...@@ -533,6 +547,11 @@ module x393 #(
cmd_clocks_ad <= cmd_root_ad; cmd_clocks_ad <= cmd_root_ad;
cmd_clocks_stb <= cmd_root_stb; cmd_clocks_stb <= cmd_root_stb;
`ifdef DEBUG_RING
cmd_debug_ad <= cmd_root_ad;
cmd_debug_stb <= cmd_root_stb;
`endif
end end
// For now - connect status_test01 to status_other, if needed - increase number of multiplexer inputs) // For now - connect status_test01 to status_other, if needed - increase number of multiplexer inputs)
...@@ -892,9 +911,9 @@ assign axi_grst = axi_rst_pre; ...@@ -892,9 +911,9 @@ assign axi_grst = axi_rst_pre;
.rq_in10 (status_clocks_rq), // input .rq_in10 (status_clocks_rq), // input
.start_in10(status_clocks_start), // output .start_in10(status_clocks_start), // output
.db_in11 (8'b0), // input[7:0] .db_in11 (status_debug_ad), // input[7:0]
.rq_in11 (1'b0), // input .rq_in11 (status_debug_rq), // input
.start_in11(), // output .start_in11(status_debug_start), // output
.db_in12 (8'b0), // input[7:0] .db_in12 (8'b0), // input[7:0]
.rq_in12 (1'b0), // input .rq_in12 (1'b0), // input
...@@ -1518,6 +1537,9 @@ assign axi_grst = axi_rst_pre; ...@@ -1518,6 +1537,9 @@ assign axi_grst = axi_rst_pre;
.SENS_SS_EN (SENS_SS_EN), .SENS_SS_EN (SENS_SS_EN),
.SENS_SS_MODE (SENS_SS_MODE), .SENS_SS_MODE (SENS_SS_MODE),
.SENS_SS_MOD_PERIOD (SENS_SS_MOD_PERIOD) .SENS_SS_MOD_PERIOD (SENS_SS_MOD_PERIOD)
`ifdef DEBUG_RING
,.DEBUG_CMD_LATENCY (DEBUG_CMD_LATENCY)
`endif
) sensors393_i ( ) sensors393_i (
// .rst (axi_rst), // input // .rst (axi_rst), // input
.pclk (pclk), // input .pclk (pclk), // input
...@@ -1586,6 +1608,11 @@ assign axi_grst = axi_rst_pre; ...@@ -1586,6 +1608,11 @@ assign axi_grst = axi_rst_pre;
.saxi_bready (saxi0_bready), // output .saxi_bready (saxi0_bready), // output
.saxi_bid (saxi0_bid), // input[5:0] .saxi_bid (saxi0_bid), // input[5:0]
.saxi_bresp (saxi0_bresp) // input[1:0] .saxi_bresp (saxi0_bresp) // input[1:0]
`ifdef DEBUG_RING
,.debug_do (debug_ring[1]), // output
.debug_sl (debug_sl), // output
.debug_di (debug_ring[0]) // input
`endif
); );
// AFI1 (AXI_HP1) signals - write channels only // AFI1 (AXI_HP1) signals - write channels only
...@@ -1720,6 +1747,10 @@ assign axi_grst = axi_rst_pre; ...@@ -1720,6 +1747,10 @@ assign axi_grst = axi_rst_pre;
.CMPRS_AFIMUX_WIDTH (CMPRS_AFIMUX_WIDTH), .CMPRS_AFIMUX_WIDTH (CMPRS_AFIMUX_WIDTH),
.CMPRS_AFIMUX_CYCBITS (CMPRS_AFIMUX_CYCBITS), .CMPRS_AFIMUX_CYCBITS (CMPRS_AFIMUX_CYCBITS),
.AFI_MUX_BUF_LATENCY (AFI_MUX_BUF_LATENCY) .AFI_MUX_BUF_LATENCY (AFI_MUX_BUF_LATENCY)
`ifdef DEBUG_RING
,.DEBUG_CMD_LATENCY (DEBUG_CMD_LATENCY)
`endif
) compressor393_i ( ) compressor393_i (
// .rst (axi_rst), // input // .rst (axi_rst), // input
.xclk (xclk), // input .xclk (xclk), // input
...@@ -1809,6 +1840,12 @@ assign axi_grst = axi_rst_pre; ...@@ -1809,6 +1840,12 @@ assign axi_grst = axi_rst_pre;
.afi1_wcount (afi2_wcount), // input[7:0] .afi1_wcount (afi2_wcount), // input[7:0]
.afi1_wacount (afi2_wacount), // input[5:0] .afi1_wacount (afi2_wacount), // input[5:0]
.afi1_wrissuecap1en (afi2_wrissuecap1en) // output .afi1_wrissuecap1en (afi2_wrissuecap1en) // output
`ifdef DEBUG_RING
,.debug_do (debug_ring[DEBUG_RING_LENGTH-1]), // output
.debug_sl (debug_sl), // output
.debug_di (debug_ring[1]) // input
`endif
); );
// general purpose I/Os, connected to the 10389 boards // general purpose I/Os, connected to the 10389 boards
...@@ -2146,6 +2183,30 @@ assign axi_grst = axi_rst_pre; ...@@ -2146,6 +2183,30 @@ assign axi_grst = axi_rst_pre;
.rst ({hrst, arst, lrst, crst, xrst, prst, mrst}) // output[6:0] .rst ({hrst, arst, lrst, crst, xrst, prst, mrst}) // output[6:0]
); );
`ifdef DEBUG_RING
debug_master #(
.DEBUG_ADDR (DEBUG_ADDR),
.DEBUG_MASK (DEBUG_MASK),
.DEBUG_STATUS_REG_ADDR (DEBUG_STATUS_REG_ADDR),
.DEBUG_READ_REG_ADDR (DEBUG_READ_REG_ADDR),
.DEBUG_SHIFT_DATA (DEBUG_SHIFT_DATA),
.DEBUG_LOAD (DEBUG_LOAD),
.DEBUG_SET_STATUS (DEBUG_SET_STATUS),
.DEBUG_CMD_LATENCY (DEBUG_CMD_LATENCY)
) debug_master_i (
.mclk (mclk), // input
.mrst (mrst), // input
.cmd_ad (cmd_debug_ad), // input[7:0]
.cmd_stb (cmd_debug_stb), // input
.status_ad (status_debug_ad), // output[7:0]
.status_rq (status_debug_rq), // output
.status_start (status_debug_start), // input
.debug_do (debug_ring[0]), // output
.debug_sl (debug_sl), // output
.debug_di (debug_ring[DEBUG_RING_LENGTH-1]) // input
);
`endif
axibram_write #( axibram_write #(
.ADDRESS_BITS(AXI_WR_ADDR_BITS) .ADDRESS_BITS(AXI_WR_ADDR_BITS)
) axibram_write_i ( //SuppressThisWarning ISExst Output port <bram_wstb> of the instance <axibram_write_i> is unconnected or connected to loadless signal. ) axibram_write_i ( //SuppressThisWarning ISExst Output port <bram_wstb> of the instance <axibram_write_i> is unconnected or connected to loadless signal.
......
x393_testbench02.tf
View file @ ed32ff53
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