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Commit e8678ccd authored by Andrey Filippov's avatar Andrey Filippov
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Added reporting of the memory channel last transferred frame in a buffer 

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parent dadbda68
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Showing with 406 additions and 11 deletions
dsp/dtt_iv8_1d.v 0 → 100644
View file @ e8678ccd
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fpga_version.vh
View file @ e8678ccd
...@@ -36,7 +36,10 @@ ...@@ -36,7 +36,10 @@
* with at least one of the Free Software programs. * with at least one of the Free Software programs.
*/ */
parameter FPGA_VERSION = 32'h039300f0; //parallel - 17.4 - retry with spells in clean directory parameter FPGA_VERSION = 32'h039300f3; //parallel - 17.4 - adding buffer frame number to status (no debug)
// parameter FPGA_VERSION = 32'h039300f2; //parallel - 17.4 - inactive debug, OK on fresh
// parameter FPGA_VERSION = 32'h039300f1; //parallel - 17.4 - without power optimize failed, second - OK
// parameter FPGA_VERSION = 32'h039300f0; //parallel - 17.4 - retry with spells in clean directory - failed
// parameter FPGA_VERSION = 32'h039300ef; //parallel - 17.4 - trying more set_param VivadoSynthesis-20180203230051566.log - OK! // parameter FPGA_VERSION = 32'h039300ef; //parallel - 17.4 - trying more set_param VivadoSynthesis-20180203230051566.log - OK!
// parameter FPGA_VERSION = 32'h039300ee; //parallel - 17.4 - save after re-running vivado, same dir - bad // parameter FPGA_VERSION = 32'h039300ee; //parallel - 17.4 - save after re-running vivado, same dir - bad
// parameter FPGA_VERSION = 32'h039300ed; //parallel - 17.4 - twice synth+par, then bit - good // parameter FPGA_VERSION = 32'h039300ed; //parallel - 17.4 - twice synth+par, then bit - good
......
memctrl/mcntrl_linear_rw.v
View file @ e8678ccd
...@@ -39,6 +39,7 @@ ...@@ -39,6 +39,7 @@
*/ */
`timescale 1ns/1ps `timescale 1ns/1ps
// TODO: ADD MCNTRL_SCANLINE_FRAME_PAGE_RESET to caller // TODO: ADD MCNTRL_SCANLINE_FRAME_PAGE_RESET to caller
`define REPORT_FRAME_NUMBER 1
`undef DEBUG_MCNTRL_LINEAR_EXTRA_STATUS `undef DEBUG_MCNTRL_LINEAR_EXTRA_STATUS
module mcntrl_linear_rw #( module mcntrl_linear_rw #(
parameter ADDRESS_NUMBER= 15, parameter ADDRESS_NUMBER= 15,
...@@ -222,7 +223,12 @@ module mcntrl_linear_rw #( ...@@ -222,7 +223,12 @@ module mcntrl_linear_rw #(
`ifdef DEBUG_MCNTRL_LINEAR_EXTRA_STATUS `ifdef DEBUG_MCNTRL_LINEAR_EXTRA_STATUS
wire [11:0] status_data; wire [11:0] status_data;
`else `else
`ifdef REPORT_FRAME_NUMBER
wire [LAST_FRAME_BITS+1:0] status_data;
`else
wire [1:0] status_data; wire [1:0] status_data;
`endif
`endif `endif
wire [3:0] cmd_a; wire [3:0] cmd_a;
wire [31:0] cmd_data; wire [31:0] cmd_data;
...@@ -272,7 +278,9 @@ module mcntrl_linear_rw #( ...@@ -272,7 +278,9 @@ module mcntrl_linear_rw #(
reg buf_reset_pend; // reset buffer page at next (late)frame sync (compressor should be disabled reg buf_reset_pend; // reset buffer page at next (late)frame sync (compressor should be disabled
// if total number of pages in a frame is not multiple of 4 // if total number of pages in a frame is not multiple of 4
wire chn_dis_delayed = chn_rst || (!chn_en && !busy_r); // reset if real reset or disabled and frame finished wire chn_dis_delayed = chn_rst || (!chn_en && !busy_r); // reset if real reset or disabled and frame finished
`ifdef REPORT_FRAME_NUMBER
reg [LAST_FRAME_BITS-1:0] done_frame_number;
`endif
// wire // wire
assign frame_number = frame_number_current; assign frame_number = frame_number_current;
...@@ -326,6 +334,11 @@ module mcntrl_linear_rw #( ...@@ -326,6 +334,11 @@ module mcntrl_linear_rw #(
// else is_last_frame <= frame_number_cntr == last_frame_number; // else is_last_frame <= frame_number_cntr == last_frame_number;
else is_last_frame <= frame_number_cntr >= last_frame_number; // trying to make it safe else is_last_frame <= frame_number_cntr >= last_frame_number; // trying to make it safe
`ifdef REPORT_FRAME_NUMBER
if (mrst) done_frame_number <= 0;
else if (frame_done_r) done_frame_number <= frame_number_cntr;
`endif
// if (mrst) frame_start_r <= 0; // if (mrst) frame_start_r <= 0;
// else frame_start_r <= {frame_start_r[3:0], frame_start_late & frame_en}; // else frame_start_r <= {frame_start_r[3:0], frame_start_late & frame_en};
...@@ -429,7 +442,11 @@ module mcntrl_linear_rw #( ...@@ -429,7 +442,11 @@ module mcntrl_linear_rw #(
`ifdef DEBUG_MCNTRL_LINEAR_EXTRA_STATUS `ifdef DEBUG_MCNTRL_LINEAR_EXTRA_STATUS
assign status_data= {last_row_w, last_in_row,line_unfinished[7:0], frame_finished_r, busy_r}; assign status_data= {last_row_w, last_in_row,line_unfinished[7:0], frame_finished_r, busy_r};
`else `else
`ifdef REPORT_FRAME_NUMBER
assign status_data= {done_frame_number, frame_finished_r, busy_r}; // TODO: Add second bit?
`else
assign status_data= {frame_finished_r, busy_r}; // TODO: Add second bit? assign status_data= {frame_finished_r, busy_r}; // TODO: Add second bit?
`endif
`endif `endif
assign pgm_param_w= cmd_we; assign pgm_param_w= cmd_we;
localparam [COLADDR_NUMBER-3-NUM_XFER_BITS-1:0] EXTRA_BITS=0; localparam [COLADDR_NUMBER-3-NUM_XFER_BITS-1:0] EXTRA_BITS=0;
...@@ -710,10 +727,14 @@ wire start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r; ...@@ -710,10 +727,14 @@ wire start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r;
`else `else
`ifdef DEBUG_MCNTRL_LINEAR_EXTRA_STATUS `ifdef DEBUG_MCNTRL_LINEAR_EXTRA_STATUS
.PAYLOAD_BITS (12) .PAYLOAD_BITS (12)
`else
`ifdef REPORT_FRAME_NUMBER
.PAYLOAD_BITS (2 + LAST_FRAME_BITS)
`else `else
.PAYLOAD_BITS (2) .PAYLOAD_BITS (2)
`endif `endif
`endif `endif
`endif
) status_generate_i ( ) status_generate_i (
.rst (1'b0), //rst), // input .rst (1'b0), //rst), // input
.clk (mclk), // input .clk (mclk), // input
......
memctrl/mcntrl_tiled_rw.v
View file @ e8678ccd
...@@ -40,6 +40,7 @@ ...@@ -40,6 +40,7 @@
* with at least one of the Free Software programs. * with at least one of the Free Software programs.
*/ */
`timescale 1ns/1ps `timescale 1ns/1ps
`define REPORT_FRAME_NUMBER 1
`undef DEBUG_MCNTRL_TILED_EXTRA_STATUS `undef DEBUG_MCNTRL_TILED_EXTRA_STATUS
module mcntrl_tiled_rw#( module mcntrl_tiled_rw#(
parameter ADDRESS_NUMBER= 15, parameter ADDRESS_NUMBER= 15,
...@@ -220,7 +221,11 @@ module mcntrl_tiled_rw#( ...@@ -220,7 +221,11 @@ module mcntrl_tiled_rw#(
`ifdef DEBUG_MCNTRL_TILED_EXTRA_STATUS `ifdef DEBUG_MCNTRL_TILED_EXTRA_STATUS
wire [13:0] status_data; wire [13:0] status_data;
`else `else
`ifdef REPORT_FRAME_NUMBER
wire [LAST_FRAME_BITS+1:0] status_data;
`else
wire [1:0] status_data; wire [1:0] status_data;
`endif
`endif `endif
wire [3:0] cmd_a; wire [3:0] cmd_a;
...@@ -286,6 +291,9 @@ module mcntrl_tiled_rw#( ...@@ -286,6 +291,9 @@ module mcntrl_tiled_rw#(
// if total number of pages in a frame is not multiple of 4 // if total number of pages in a frame is not multiple of 4
reg frames_in_sync_r; reg frames_in_sync_r;
wire chn_dis_delayed = chn_rst || (!chn_en && !busy_r); // reset if real reset or disabled and frame finished wire chn_dis_delayed = chn_rst || (!chn_en && !busy_r); // reset if real reset or disabled and frame finished
`ifdef REPORT_FRAME_NUMBER
reg [LAST_FRAME_BITS-1:0] done_frame_number;
`endif
assign frames_in_sync = frames_in_sync_r; assign frames_in_sync = frames_in_sync_r;
assign frame_number = frame_number_current; assign frame_number = frame_number_current;
...@@ -339,7 +347,10 @@ module mcntrl_tiled_rw#( ...@@ -339,7 +347,10 @@ module mcntrl_tiled_rw#(
if (mrst) is_last_frame <= 0; if (mrst) is_last_frame <= 0;
// else is_last_frame <= frame_number_cntr == last_frame_number; // else is_last_frame <= frame_number_cntr == last_frame_number;
else is_last_frame <= frame_number_cntr >= last_frame_number; // trying to make it safe else is_last_frame <= frame_number_cntr >= last_frame_number; // trying to make it safe
`ifdef REPORT_FRAME_NUMBER
if (mrst) done_frame_number <= 0;
else if (frame_done_r) done_frame_number <= frame_number_cntr;
`endif
if (mrst) frame_start_r <= 0; if (mrst) frame_start_r <= 0;
else frame_start_r <= {frame_start_r[3:0], frame_start_mod & frame_en}; // frame_start else frame_start_r <= {frame_start_r[3:0], frame_start_mod & frame_en}; // frame_start
...@@ -452,7 +463,11 @@ module mcntrl_tiled_rw#( ...@@ -452,7 +463,11 @@ module mcntrl_tiled_rw#(
`ifdef DEBUG_MCNTRL_TILED_EXTRA_STATUS `ifdef DEBUG_MCNTRL_TILED_EXTRA_STATUS
assign status_data= {frames_in_sync, suspend, last_row_w, last_in_row,line_unfinished[7:0], frame_finished_r, busy_r}; assign status_data= {frames_in_sync, suspend, last_row_w, last_in_row,line_unfinished[7:0], frame_finished_r, busy_r};
`else `else
assign status_data= {frame_finished_r, busy_r}; `ifdef REPORT_FRAME_NUMBER
assign status_data= {done_frame_number, frame_finished_r, busy_r}; // TODO: Add second bit?
`else
assign status_data= {frame_finished_r, busy_r}; // TODO: Add second bit?
`endif
`endif `endif
...@@ -682,7 +697,11 @@ wire start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r; ...@@ -682,7 +697,11 @@ wire start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r;
`ifdef DEBUG_MCNTRL_TILED_EXTRA_STATUS `ifdef DEBUG_MCNTRL_TILED_EXTRA_STATUS
.PAYLOAD_BITS (14) .PAYLOAD_BITS (14)
`else `else
`ifdef REPORT_FRAME_NUMBER
.PAYLOAD_BITS (2 + LAST_FRAME_BITS)
`else
.PAYLOAD_BITS (2) .PAYLOAD_BITS (2)
`endif
`endif `endif
) status_generate_i ( ) status_generate_i (
.rst (1'b0), // input .rst (1'b0), // input
......
py393/x393_export_c.py
View file @ e8678ccd
...@@ -800,6 +800,7 @@ class X393ExportC(object): ...@@ -800,6 +800,7 @@ class X393ExportC(object):
(("X393_MCNTRL_CHN3_STATUS", c, vrlg.MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR+ba,0,None, "x393_status_mcntrl_lintile", "ro", "Status register for MCNTRL CHN3 (scanline)")), (("X393_MCNTRL_CHN3_STATUS", c, vrlg.MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR+ba,0,None, "x393_status_mcntrl_lintile", "ro", "Status register for MCNTRL CHN3 (scanline)")),
(("X393_MCNTRL_CHN2_STATUS", c, vrlg.MCNTRL_TILED_STATUS_REG_CHN2_ADDR+ba,0,None, "x393_status_mcntrl_lintile", "ro", "Status register for MCNTRL CHN2 (tiled)")), (("X393_MCNTRL_CHN2_STATUS", c, vrlg.MCNTRL_TILED_STATUS_REG_CHN2_ADDR+ba,0,None, "x393_status_mcntrl_lintile", "ro", "Status register for MCNTRL CHN2 (tiled)")),
(("X393_MCNTRL_CHN4_STATUS", c, vrlg.MCNTRL_TILED_STATUS_REG_CHN4_ADDR+ba,0,None, "x393_status_mcntrl_lintile", "ro", "Status register for MCNTRL CHN4 (tiled)")), (("X393_MCNTRL_CHN4_STATUS", c, vrlg.MCNTRL_TILED_STATUS_REG_CHN4_ADDR+ba,0,None, "x393_status_mcntrl_lintile", "ro", "Status register for MCNTRL CHN4 (tiled)")),
(("X393_TEST01_CHN2_STATUS", c, vrlg.MCNTRL_TEST01_STATUS_REG_CHN2_ADDR+ba,0,None, "x393_status_mcntrl_testchn", "ro", "Status register for test channel 2")), (("X393_TEST01_CHN2_STATUS", c, vrlg.MCNTRL_TEST01_STATUS_REG_CHN2_ADDR+ba,0,None, "x393_status_mcntrl_testchn", "ro", "Status register for test channel 2")),
(("X393_TEST01_CHN3_STATUS", c, vrlg.MCNTRL_TEST01_STATUS_REG_CHN3_ADDR+ba,0,None, "x393_status_mcntrl_testchn", "ro", "Status register for test channel 3")), (("X393_TEST01_CHN3_STATUS", c, vrlg.MCNTRL_TEST01_STATUS_REG_CHN3_ADDR+ba,0,None, "x393_status_mcntrl_testchn", "ro", "Status register for test channel 3")),
(("X393_TEST01_CHN4_STATUS", c, vrlg.MCNTRL_TEST01_STATUS_REG_CHN4_ADDR+ba,0,None, "x393_status_mcntrl_testchn", "ro", "Status register for test channel 4")), (("X393_TEST01_CHN4_STATUS", c, vrlg.MCNTRL_TEST01_STATUS_REG_CHN4_ADDR+ba,0,None, "x393_status_mcntrl_testchn", "ro", "Status register for test channel 4")),
...@@ -807,6 +808,22 @@ class X393ExportC(object): ...@@ -807,6 +808,22 @@ class X393ExportC(object):
(("X393_FPGA_VERSION", c, fpga_ver + ba, 0, None, "u32*", "ro", "FPGA bitstream version")), (("X393_FPGA_VERSION", c, fpga_ver + ba, 0, None, "u32*", "ro", "FPGA bitstream version")),
(("X393_SENSOR_INTERFACE", c, sens_iface + ba, 0, None, "u32*", "ro", "Sensor interface 0-parallel 12, 1 - HiSPI 4 lanes")), (("X393_SENSOR_INTERFACE", c, sens_iface + ba, 0, None, "u32*", "ro", "Sensor interface 0-parallel 12, 1 - HiSPI 4 lanes")),
] ]
#Sensor memory status (frame number)
ba = vrlg.STATUS_ADDR
ia = vrlg.MCONTR_SENS_STATUS_INC
c = "chn"
sdefines +=[
(('Sensor memory channel status)',)),
(("X393_SENS_MEM_STATUS", c, vrlg.MCONTR_SENS_STATUS_BASE + ba, ia, z3, "x393_status_mcntrl_lintile", "ro", "Status register for sensor memory channel"))]
#Compressor memory status (frame number)
ba = vrlg.STATUS_ADDR
ia = vrlg.MCONTR_CMPRS_STATUS_INC
c = "chn"
sdefines +=[
(('Sensor memory channel status)',)),
(("X393_CMPRS_MEM_STATUS", c, vrlg.MCONTR_CMPRS_STATUS_BASE + ba, ia, z3, "x393_status_mcntrl_lintile", "ro", "Status register for compressor memory channel"))]
#Registers to control sensor channels #Registers to control sensor channels
ba = vrlg.SENSOR_GROUP_ADDR ba = vrlg.SENSOR_GROUP_ADDR
...@@ -1783,6 +1800,7 @@ class X393ExportC(object): ...@@ -1783,6 +1800,7 @@ class X393ExportC(object):
def _enc_status_lintile(self): #status for memory accesses of the test channels (2,3,4) def _enc_status_lintile(self): #status for memory accesses of the test channels (2,3,4)
dw=[] dw=[]
dw.append(("frame_number", 0, 16,0, "Number of the last transferred frame in the buffer"))
dw.append(("busy", 24, 1,0, "Channel is busy (started and some memory accesses are pending)")) dw.append(("busy", 24, 1,0, "Channel is busy (started and some memory accesses are pending)"))
dw.append(("frame_finished", 25, 1,0, "Channel completed all memory accesses")) dw.append(("frame_finished", 25, 1,0, "Channel completed all memory accesses"))
dw.append(("seq_num", 26, 6,0, "Sequence number")) dw.append(("seq_num", 26, 6,0, "Sequence number"))
......
x393.v
View file @ e8678ccd
...@@ -3533,7 +3533,7 @@ sata_ahci_top sata_top( ...@@ -3533,7 +3533,7 @@ sata_ahci_top sata_top(
); );
`ifdef DEBUG_SAXI1 `ifdef DEBUG_SAXI1
/* /* */
debug_saxigp #( debug_saxigp #(
.DEBUG_STATUS ('h714), .DEBUG_STATUS ('h714),
.DEBUG_STATUS_MASK ('h7ff), .DEBUG_STATUS_MASK ('h7ff),
...@@ -3570,7 +3570,7 @@ sata_ahci_top sata_top( ...@@ -3570,7 +3570,7 @@ sata_ahci_top sata_top(
.saxi_bid (6'b0), // saxi1_bid), // input[5:0] .saxi_bid (6'b0), // saxi1_bid), // input[5:0]
.saxi_bresp (2'b0) // saxi1_bresp) // input[1:0] .saxi_bresp (2'b0) // saxi1_bresp) // input[1:0]
); );
*/ /**/ /*
debug_saxigp #( debug_saxigp #(
.DEBUG_STATUS ('h714), .DEBUG_STATUS ('h714),
.DEBUG_STATUS_MASK ('h7ff), .DEBUG_STATUS_MASK ('h7ff),
...@@ -3606,7 +3606,7 @@ sata_ahci_top sata_top( ...@@ -3606,7 +3606,7 @@ sata_ahci_top sata_top(
.saxi_bready (saxi1_bready), // input .saxi_bready (saxi1_bready), // input
.saxi_bid (saxi1_bid), // input[5:0] .saxi_bid (saxi1_bid), // input[5:0]
.saxi_bresp (saxi1_bresp) // input[1:0] .saxi_bresp (saxi1_bresp) // input[1:0]
); ); */
`endif `endif
......
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