converted channel buffers to configurable width (e79823db) · Commits · Elphel / x393

memctrl/mcntrl393.v

+24 −8

Original line number	Original line	Diff line number	Diff line
	@@ -779,7 +779,9 @@ module mcntrl393 #(
	// Port memory buffer (4 pages each, R/W fixed, port 0 - AXI read from DDR, port 1 - AXI write to DDR		// Port memory buffer (4 pages each, R/W fixed, port 0 - AXI read from DDR, port 1 - AXI write to DDR

	// Port 1rd (read DDR to AXI) buffer, linear		// Port 1rd (read DDR to AXI) buffer, linear
	mcntrl_1kx32r chn1rd_buf_i (		mcntrl_buf_rd #(
			.LOG2WIDTH_RD(5)
			) chn1rd_buf_i (
	.ext_clk (axi_clk), // input		.ext_clk (axi_clk), // input
	.ext_raddr (buf_raddr), // input[9:0]		.ext_raddr (buf_raddr), // input[9:0]
	.ext_rd (buf1rd_rd), // input		.ext_rd (buf1rd_rd), // input
	@@ -795,7 +797,9 @@ module mcntrl393 #(
	);		);

	// Port 1wr (write DDR from AXI) buffer, linear		// Port 1wr (write DDR from AXI) buffer, linear
	mcntrl_1kx32w chn1wr_buf_i (		mcntrl_buf_wr #(
			.LOG2WIDTH_WR(5)
			) chn1wr_buf_i (
	.ext_clk (axi_clk), // input		.ext_clk (axi_clk), // input
	.ext_waddr (buf_waddr), // input[9:0]		.ext_waddr (buf_waddr), // input[9:0]
	.ext_we (buf1wr_we), // input		.ext_we (buf1wr_we), // input
	@@ -810,7 +814,9 @@ module mcntrl393 #(
	);		);

	// Port 2rd (read DDR to AXI) buffer, tiled		// Port 2rd (read DDR to AXI) buffer, tiled
	mcntrl_1kx32r chn2rd_buf_i (		mcntrl_buf_rd #(
			.LOG2WIDTH_RD(5)
			) chn2rd_buf_i (
	.ext_clk (axi_clk), // input		.ext_clk (axi_clk), // input
	.ext_raddr (buf_raddr), // input[9:0]		.ext_raddr (buf_raddr), // input[9:0]
	.ext_rd (buf2rd_rd), // input		.ext_rd (buf2rd_rd), // input
	@@ -826,7 +832,9 @@ module mcntrl393 #(
	);		);

	// Port 2wr (write DDR from AXI) buffer, tiled		// Port 2wr (write DDR from AXI) buffer, tiled
	mcntrl_1kx32w chn2wr_buf_i (		mcntrl_buf_wr #(
			.LOG2WIDTH_WR(5)
			) chn2wr_buf_i (
	.ext_clk (axi_clk), // input		.ext_clk (axi_clk), // input
	.ext_waddr (buf_waddr), // input[9:0]		.ext_waddr (buf_waddr), // input[9:0]
	.ext_we (buf2wr_we), // input		.ext_we (buf2wr_we), // input
	@@ -841,7 +849,9 @@ module mcntrl393 #(
	);		);
	//-----------		//-----------
	// Port 3rd (read DDR to AXI) buffer, linear		// Port 3rd (read DDR to AXI) buffer, linear
	mcntrl_1kx32r chn3rd_buf_i (		mcntrl_buf_rd #(
			.LOG2WIDTH_RD(5)
			) chn3rd_buf_i (
	.ext_clk (axi_clk), // input		.ext_clk (axi_clk), // input
	.ext_raddr (buf_raddr), // input[9:0]		.ext_raddr (buf_raddr), // input[9:0]
	.ext_rd (buf3rd_rd), // input		.ext_rd (buf3rd_rd), // input
	@@ -857,7 +867,9 @@ module mcntrl393 #(
	);		);

	// Port 3wr (write DDR from AXI) buffer, linear		// Port 3wr (write DDR from AXI) buffer, linear
	mcntrl_1kx32w chn3wr_buf_i (		mcntrl_buf_wr #(
			.LOG2WIDTH_WR(5)
			) chn3wr_buf_i (
	.ext_clk (axi_clk), // input		.ext_clk (axi_clk), // input
	.ext_waddr (buf_waddr), // input[9:0]		.ext_waddr (buf_waddr), // input[9:0]
	.ext_we (buf3wr_we), // input		.ext_we (buf3wr_we), // input
	@@ -872,7 +884,9 @@ module mcntrl393 #(
	);		);

	// Port 4rd (read DDR to AXI) buffer, tiled		// Port 4rd (read DDR to AXI) buffer, tiled
	mcntrl_1kx32r chn4rd_buf_i (		mcntrl_buf_rd #(
			.LOG2WIDTH_RD(5)
			) chn4rd_buf_i (
	.ext_clk (axi_clk), // input		.ext_clk (axi_clk), // input
	.ext_raddr (buf_raddr), // input[9:0]		.ext_raddr (buf_raddr), // input[9:0]
	.ext_rd (buf4rd_rd), // input		.ext_rd (buf4rd_rd), // input
	@@ -888,7 +902,9 @@ module mcntrl393 #(
	);		);

	// Port 4wr (write DDR from AXI) buffer, tiled		// Port 4wr (write DDR from AXI) buffer, tiled
	mcntrl_1kx32w chn4wr_buf_i (		mcntrl_buf_wr #(
			.LOG2WIDTH_WR(5)
			) chn4wr_buf_i (
	.ext_clk (axi_clk), // input		.ext_clk (axi_clk), // input
	.ext_waddr (buf_waddr), // input[9:0]		.ext_waddr (buf_waddr), // input[9:0]
	.ext_we (buf4wr_we), // input		.ext_we (buf4wr_we), // input

memctrl/mcntrl_buf_rd.v

0 → 100644

+70 −0

Original line number	Original line	Diff line number	Diff line
			/*******************************************************************************
			* Module: mcntrl_buf_rd
			* Date:2015-02-03
			* Author: andrey
			* Description: Paged buffer for ddr3 controller read channel
			* with address autoincrement. Variable width external data
			*
			* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
			* mcntrl_buf_rd.v is free software; you can redistribute it and/or modify
			* it under the terms of the GNU General Public License as published by
			* the Free Software Foundation, either version 3 of the License, or
			* (at your option) any later version.
			*
			* mcntrl_buf_rd.v is distributed in the hope that it will be useful,
			* but WITHOUT ANY WARRANTY; without even the implied warranty of
			* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
			* GNU General Public License for more details.
			*
			* You should have received a copy of the GNU General Public License
			* along with this program. If not, see <http://www.gnu.org/licenses/> .
			*******************************************************************************/
			`timescale 1ns/1ps

			module mcntrl_buf_rd #(
			parameter integer LOG2WIDTH_RD = 5 // WIDTH= 1 << LOG2WIDTH
			) (
			input ext_clk,
			input [14-LOG2WIDTH_RD:0] ext_raddr, // read address
			input ext_rd, // read port enable
			input ext_regen, // output register enable
			output [(1 << LOG2WIDTH_RD)-1:0] ext_data_out, // data out

			input wclk, // !mclk (inverted)
			input [1:0] wpage_in, // will register to wclk, input OK with mclk
			input wpage_set, // set internal read page to rpage_in
			input page_next, // advance to next page (and reset lower bits to 0)
			output [1:0] page, // current inernal page
			input we, // write port enable (also increment write buffer address)
			input [63:0] data_in // data in
			);
			reg [1:0] page_r;
			reg [6:0] waddr;
			assign page=page_r;
			always @ (posedge wclk) begin

			if (wpage_set) page_r <= wpage_in;
			else if (page_next) page_r <= page_r+1;

			if (page_next \|\| wpage_set) waddr <= 0;
			else if (we) waddr <= waddr+1;
			end
			// ram_512x64w_1kx32r #(
			ram_var_w_var_r #(
			.REGISTERS(1),
			.LOG2WIDTH_WR(6),
			.LOG2WIDTH_RD(LOG2WIDTH_RD)
			) ram_512x64w_1kx32r_i (
			.rclk (ext_clk), // input
			.raddr (ext_raddr), // input[9:0]
			.ren (ext_rd), // input
			.regen (ext_regen), // input
			.data_out (ext_data_out), // output[31:0]
			.wclk (wclk), // input - OK, negedge mclk
			.waddr ({page,waddr}), // input[8:0] @negedge mclk
			.we (we), // input @negedge mclk
			.web (8'hff), // input[7:0]
			.data_in (data_in) // input[63:0] @negedge mclk
			);
			endmodule

memctrl/mcntrl_buf_wr.v

0 → 100644

+72 −0

Original line number	Original line	Diff line number	Diff line
			/*******************************************************************************
			* Module: mcntrl_buf_wr
			* Date:2015-02-03
			* Author: andrey
			* Description: Paged buffer for ddr3 controller write channel
			* with address autoincrement. 32 bit external data. Extends rd to regen
			*
			* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
			* mcntrl_buf_wr.v is free software; you can redistribute it and/or modify
			* it under the terms of the GNU General Public License as published by
			* the Free Software Foundation, either version 3 of the License, or
			* (at your option) any later version.
			*
			* mcntrl_buf_wr.v is distributed in the hope that it will be useful,
			* but WITHOUT ANY WARRANTY; without even the implied warranty of
			* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
			* GNU General Public License for more details.
			*
			* You should have received a copy of the GNU General Public License
			* along with this program. If not, see <http://www.gnu.org/licenses/> .
			*******************************************************************************/
			`timescale 1ns/1ps

			module mcntrl_buf_wr #(
			parameter integer LOG2WIDTH_WR = 5 // WIDTH= 1 << LOG2WIDTH
			) (
			input ext_clk,
			input [14-LOG2WIDTH_WR:0] ext_waddr, // external write address
			input ext_we, // external write enable
			input [(1 << LOG2WIDTH_WR)-1:0] ext_data_in, // data input

			input rclk, // mclk
			input [1:0] rpage_in, // will register to wclk, input OK with mclk
			input rpage_set, // set internal read page to rpage_in
			input page_next, // advance to next page (and reset lower bits to 0)
			output [1:0] page, // current inernal page
			input rd, // read buffer to memory, increment read address (regester enable will be delayed)
			output [63:0] data_out // data out

			);
			reg [1:0] page_r;
			reg [6:0] raddr;
			reg regen;
			assign page=page_r;
			always @ (posedge rclk) begin
			regen <= rd;

			if (rpage_set) page_r <= rpage_in;
			else if (page_next) page_r <= page_r+1;

			if (page_next \|\| rpage_set) raddr <= 0;
			else if (rd) raddr <= raddr+1;
			end
			// ram_1kx32w_512x64r #(
			ram_var_w_var_r #(
			.REGISTERS(1),
			.LOG2WIDTH_WR(LOG2WIDTH_WR),
			.LOG2WIDTH_RD(6)
			)ram_1kx32w_512x64r_i (
			.rclk (rclk), // input
			.raddr ({page_r,raddr}), // input[8:0]
			.ren (rd), // input
			.regen (regen), // input
			.data_out (data_out), // output[63:0]
			.wclk (ext_clk), // input
			.waddr (ext_waddr), // input[9:0]
			.we (ext_we), // input
			.web (8'hff), // input[3:0]
			.data_in (ext_data_in) // input[31:0]
			);
			endmodule

memctrl/mcntrl_ps_pio.v

+6 −2

Original line number	Original line	Diff line number	Diff line
	@@ -228,7 +228,9 @@ fifo_same_clock #(


	// Port 0 (read DDR to AXI) buffer		// Port 0 (read DDR to AXI) buffer
	mcntrl_1kx32r chn0_buf_i (		mcntrl_buf_rd #(
			.LOG2WIDTH_RD(5)
			) chn0_buf_i (
	.ext_clk (port0_clk), // input		.ext_clk (port0_clk), // input
	.ext_raddr (port0_addr), // input[9:0]		.ext_raddr (port0_addr), // input[9:0]
	.ext_rd (port0_re), // input		.ext_rd (port0_re), // input
	@@ -244,7 +246,9 @@ fifo_same_clock #(
	);		);

	// Port 1 (write DDR from AXI) buffer		// Port 1 (write DDR from AXI) buffer
	mcntrl_1kx32w chn1_buf_i (		mcntrl_buf_wr #(
			.LOG2WIDTH_WR(5)
			) chn1_buf_i (
	.ext_clk (port1_clk), // input		.ext_clk (port1_clk), // input
	.ext_waddr (port1_addr), // input[9:0]		.ext_waddr (port1_addr), // input[9:0]
	.ext_we (port1_we), // input		.ext_we (port1_we), // input

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