module to keep global (Verilog) parameters, self-modified code to include...

module to keep global (Verilog) parameters, self-modified code to include pre-defines fro PyDev to be happy)

py393/vrlg.py

+'''
+# Copyright (C) 2015, Elphel.inc.
+# Module to keep globals (Verilog parameters) accessible for all modules
+# that import (not import from) this one
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
+@author:     Andrey Filippov
+@copyright:  2015 Elphel, Inc.
+@license:    GPLv3.0+
+@contact:    andrey@elphel.coml
+@deffield    updated: Updated
+'''
+__author__ = "Andrey Filippov"
+__copyright__ = "Copyright 2015, Elphel, Inc."
+__license__ = "GPL"
+__version__ = "3.0+"
+__maintainer__ = "Andrey Filippov"
+__email__ = "andrey@elphel.com"
+__status__ = "Development"
+DEFAULTS={}
+def init_vars(d):
+    global DEFAULTS
+    if d:
+        globals().update(d)
+        for k,v in d.items():
+            DEFAULTS[k]=v
+def set_name_field(vname,
+                   fieldIndex,
+                   value):
+    """
+    Set specified byte in the parameter
+    <vname>      Verilog parameter name string (as listen in 'parameters')
+    <fieldIndex> byte field index (0 - lowest byte, 1 - bits[15:8], etc)
+    <value>      value to set the specified byte to  
+    """
+#        v=vrlg.__dict__[vname]
+    v=globals()[vname]
+#        print ("old value for %s is %s"%(vname,str(vrlg.__dict__[vname])))
+    mask = 0xff << (8*fieldIndex)
+    val = value << (8*fieldIndex)
+    v = ((v ^ val) & mask) ^ v
+#        vrlg.__dict__[vname]=v
+    globals()[vname]=v
+#        print ("new value for %s is %s (0x%x)"%(vname,str(vrlg.__dict__[vname]),vrlg.__dict__[vname]))
+
+def get_name_field(vname,
+                   fieldIndex):
+    """
+    Get specified byte in the parameter
+    <vname>      Verilog parameter name string (as listen in 'parameters')
+    <fieldIndex> byte field index (0 - lowest byte, 1 - bits[15:8], etc)
+    Return  specified byte
+    """
+    return ( globals()[vname] >> (8*fieldIndex)) & 0xff
+
+def get_default_field(vname,
+                      fieldIndex):
+    """
+    Get specified byte in the parameter default value (read at program
+    start from Verilog parameters)
+    <vname>      Verilog parameter name string (as listen in 'parameters')
+    <fieldIndex> byte field index (0 - lowest byte, 1 - bits[15:8], etc)
+    Return  specified byte
+    """
+    global DEFAULTS
+
+#        return (vrlg.DEFAULTS[vname] >> (8*fieldIndex)) & 0xff
+    return (DEFAULTS[vname] >> (8*fieldIndex)) & 0xff
+
+def get_default(vname):
+    """
+    Get parameter default value (read at program start from Verilog parameters)
+    <vname>      Verilog parameter name string (as listen in 'parameters')
+    Return       specified parameter default
+    """
+    global DEFAULTS
+    return DEFAULTS[vname]
+    
+def save_default(vname=None):
+    """
+    Save parameter default value (replace read at program start from Verilog
+                 parameters) using current parameter value
+    <vname>      Verilog parameter name string (as listen in 'parameters')
+    """
+    global DEFAULTS
+    if vname:
+        DEFAULTS[vname] =  globals()[vname]
+    else:
+        for vname in DEFAULTS:
+            DEFAULTS[vname] =  globals()[vname]
+
+def restore_default(vname=None):
+    """
+    Restore parameter value from default
+    <vname>      Verilog parameter name string (as listen in 'parameters')
+    """
+    global DEFAULTS
+    if vname:
+        globals()[vname] = DEFAULTS[vname]
+    else:
+        for vname in DEFAULTS:
+            globals()[vname] = DEFAULTS[vname]
+
+#### PyDev predefines
+
+DFLT_REFRESH_ADDR__TYPE = str
+NUM_CYCLES_09__RAW = str
+DQSTRI_LAST__TYPE = str
+DLY_LD_MASK__TYPE = str
+STATUS_MSB_RSHFT__TYPE = str
+MCONTR_BUF0_RD_ADDR = int
+MCNTRL_SCANLINE_WINDOW_WH__RAW = str
+MCNTRL_TEST01_STATUS_REG_CHN4_ADDR = int
+MCNTRL_TEST01_CHN3_STATUS_CNTRL = int
+MCNTRL_PS_EN_RST__TYPE = str
+MCONTR_TOP_16BIT_STATUS_CNTRL__TYPE = str
+MCNTRL_TILED_CHN4_ADDR = int
+WINDOW_Y0__RAW = str
+DLY_LD__RAW = str
+MCNTRL_TEST01_CHN3_MODE__RAW = str
+DFLT_INV_CLK_DIV__RAW = str
+NUM_CYCLES_12__TYPE = str
+IBUF_LOW_PWR__RAW = str
+DLY_LANE1_ODELAY__RAW = str
+DLY_DQ_IDELAY__TYPE = str
+MCONTR_TOP_0BIT_ADDR_MASK = int
+MCNTRL_TEST01_STATUS_REG_CHN4_ADDR__TYPE = str
+MCONTR_PHY_0BIT_DCI_RST = int
+TILED_STARTX__TYPE = str
+HIGH_PERFORMANCE_MODE__TYPE = str
+MCONTR_PHY_STATUS_REG_ADDR__TYPE = str
+MCONTR_TOP_16BIT_ADDR__TYPE = str
+WBUF_DLY_WLV__TYPE = str
+TEST01_SUSPEND = int
+MCONTR_TOP_16BIT_CHN_EN = int
+NUM_XFER_BITS__TYPE = str
+DLY_LANE1_IDELAY__TYPE = str
+REF_JITTER1__RAW = str
+MCNTRL_TILED_MASK__TYPE = str
+MCONTR_BUF1_WR_ADDR = int
+DFLT_DQ_TRI_ON_PATTERN = int
+MCONTR_PHY_0BIT_SDRST_ACT = int
+DEFAULT_STATUS_MODE = int
+TILED_EXTRA_PAGES__TYPE = str
+DLY_LD__TYPE = str
+MCNTRL_TEST01_CHN2_STATUS_CNTRL__TYPE = str
+MCNTRL_SCANLINE_FRAME_PAGE_RESET = int
+STATUS_2LSB_SHFT__TYPE = str
+DFLT_WBUF_DELAY__RAW = str
+DLY_LANE1_ODELAY__TYPE = str
+TILE_VSTEP__RAW = str
+MCNTRL_SCANLINE_STATUS_REG_CHN1_ADDR__RAW = str
+NUM_CYCLES_04 = int
+NUM_CYCLES_05 = int
+DLY_LD = int
+NUM_CYCLES_07 = int
+NUM_CYCLES_00 = int
+NUM_CYCLES_01 = int
+MCNTRL_SCANLINE_CHN1_ADDR__TYPE = str
+NUM_CYCLES_03 = int
+NUM_CYCLES_08 = int
+NUM_CYCLES_09 = int
+MCNTRL_TEST01_CHN4_STATUS_CNTRL__TYPE = str
+NUM_CYCLES_13__RAW = str
+MCONTR_BUF0_RD_ADDR__TYPE = str
+STATUS_ADDR__RAW = str
+MCNTRL_SCANLINE_MASK__TYPE = str
+MCNTRL_PS_ADDR__TYPE = str
+WINDOW_WIDTH__RAW = str
+CHNBUF_READ_LATENCY = int
+DFLT_DQS_PATTERN__TYPE = str
+STATUS_PSHIFTER_RDY_MASK__RAW = str
+MCNTRL_TEST01_ADDR__RAW = str
+TILE_WIDTH__TYPE = str
+DFLT_REFRESH_PERIOD = int
+MCNTRL_TILED_MASK__RAW = str
+MCONTR_TOP_0BIT_REFRESH_EN__RAW = str
+MCONTR_PHY_16BIT_ADDR__RAW = str
+REFRESH_OFFSET = int
+MCNTRL_PS_EN_RST = int
+DLY_DQS_ODELAY__RAW = str
+MCNTRL_TILED_TILE_WHS = int
+FRAME_START_ADDRESS__TYPE = str
+MCNTRL_TILED_STATUS_REG_CHN2_ADDR = int
+MCNTRL_TILED_STATUS_CNTRL__RAW = str
+DQSTRI_FIRST = int
+DFLT_DQS_TRI_OFF_PATTERN = int
+NUM_CYCLES_03__TYPE = str
+MCONTR_TOP_16BIT_CHN_EN__TYPE = str
+LD_DLY_LANE1_IDELAY__TYPE = str
+MCNTRL_SCANLINE_CHN1_ADDR = int
+TILED_EXTRA_PAGES__RAW = str
+T_RFC = int
+VERBOSE = int
+DLY_LANE1_ODELAY = long
+MCONTR_TOP_16BIT_REFRESH_ADDRESS__TYPE = str
+CMD_DONE_BIT__TYPE = str
+MCNTRL_SCANLINE_STATUS_CNTRL__TYPE = str
+DLY_LANE0_IDELAY = long
+NUM_CYCLES_13__TYPE = str
+AXI_RD_ADDR_BITS__RAW = str
+MCNTRL_TEST01_CHN3_STATUS_CNTRL__TYPE = str
+MCONTR_WR_MASK__RAW = str
+MCNTRL_TILED_WINDOW_STARTXY = int
+MCONTR_TOP_0BIT_MCONTR_EN = int
+SCANLINE_EXTRA_PAGES__RAW = str
+MCONTR_PHY_16BIT_EXTRA = int
+MCONTR_ARBIT_ADDR_MASK__TYPE = str
+TEST01_NEXT_PAGE__TYPE = str
+MCONTR_PHY_0BIT_DLY_SET__TYPE = str
+MCONTR_PHY_STATUS_REG_ADDR = int
+CLKFBOUT_MULT_REF = int
+NUM_CYCLES_14__RAW = str
+MCONTR_PHY_0BIT_CMDA_EN__TYPE = str
+MCNTRL_TEST01_STATUS_REG_CHN1_ADDR = int
+DFLT_DQ_TRI_ON_PATTERN__RAW = str
+MCNTRL_TEST01_CHN1_MODE__TYPE = str
+DFLT_DQS_TRI_ON_PATTERN__RAW = str
+SLEW_DQ = str
+PHASE_WIDTH__TYPE = str
+STATUS_2LSB_SHFT = int
+COLADDR_NUMBER__RAW = str
+CONTROL_ADDR_MASK = int
+SS_MOD_PERIOD = int
+WINDOW_HEIGHT = int
+MCONTR_BUF0_WR_ADDR = int
+MCNTRL_PS_STATUS_REG_ADDR__RAW = str
+MCONTR_PHY_16BIT_PATTERNS_TRI__TYPE = str
+MCNTRL_TEST01_STATUS_REG_CHN1_ADDR__RAW = str
+CLKFBOUT_MULT = int
+MCNTRL_TILED_STATUS_CNTRL__TYPE = str
+SCANLINE_STARTY = int
+SCANLINE_STARTX = int
+SS_MODE = str
+MCONTR_CMD_WR_ADDR__RAW = str
+NUM_CYCLES_06 = int
+MCONTR_BUF2_WR_ADDR__RAW = str
+NUM_CYCLES_11__TYPE = str
+MCNTRL_SCANLINE_STARTADDR__TYPE = str
+WBUF_DLY_DFLT__RAW = str
+DLY_PHASE = int
+LD_DLY_CMDA__TYPE = str
+DLY_CMDA_ODELAY__TYPE = str
+LD_DLY_CMDA = int
+DLY_SET__RAW = str
+DFLT_REFRESH_ADDR__RAW = str
+DFLT_DQ_TRI_OFF_PATTERN__TYPE = str
+MCONTR_PHY_0BIT_SDRST_ACT__RAW = str
+REFCLK_FREQUENCY__TYPE = str
+MCNTRL_SCANLINE_MASK = int
+TILE_HEIGHT = int
+AXI_WR_ADDR_BITS__TYPE = str
+MCNTRL_PS_MASK = int
+MCNTRL_TEST01_STATUS_REG_CHN3_ADDR = int
+MCONTR_PHY_STATUS_CNTRL = int
+MCNTRL_PS_ADDR__RAW = str
+MCONTR_BUF2_RD_ADDR__TYPE = str
+TILED_STARTX__RAW = str
+WRITE_BLOCK_OFFSET__TYPE = str
+STATUS_ADDR_MASK = int
+MCNTRL_TEST01_ADDR__TYPE = str
+AXI_WR_ADDR_BITS = int
+TEST01_NEXT_PAGE = int
+CLKFBOUT_MULT__RAW = str
+MAX_TILE_HEIGHT__RAW = str
+INITIALIZE_OFFSET__TYPE = str
+IBUF_LOW_PWR = str
+CONTROL_ADDR = int
+DQSTRI_FIRST__TYPE = str
+DQSTRI_FIRST__RAW = str
+CMD_DONE_BIT = int
+NUM_CYCLES_10__TYPE = str
+MCNTRL_SCANLINE_WINDOW_X0Y0 = int
+NEWPAR__TYPE = str
+STATUS_ADDR = int
+LD_DLY_LANE0_ODELAY__RAW = str
+MCONTR_BUF0_RD_ADDR__RAW = str
+MCNTRL_TILED_STARTADDR__RAW = str
+WINDOW_X0__RAW = str
+AXI_RD_ADDR_BITS = int
+MCONTR_BUF2_RD_ADDR__RAW = str
+FRAME_START_ADDRESS = int
+MCNTRL_SCANLINE_PENDING_CNTR_BITS__TYPE = str
+CONTROL_ADDR__TYPE = str
+MCNTRL_TEST01_CHN3_STATUS_CNTRL__RAW = str
+WINDOW_Y0 = int
+DLY_DQS_IDELAY__RAW = str
+MCNTRL_TEST01_CHN3_MODE__TYPE = str
+MCNTRL_SCANLINE_WINDOW_X0Y0__RAW = str
+MCONTR_BUF4_WR_ADDR = int
+DLY_DQS_IDELAY__TYPE = str
+MCNTRL_TEST01_CHN2_STATUS_CNTRL = int
+CLK_PHASE = float
+MCNTRL_TILED_FRAME_PAGE_RESET = int
+MCONTR_TOP_16BIT_ADDR_MASK = int
+DLY_LANE1_DQS_WLV_IDELAY__RAW = str
+READ_BLOCK_OFFSET__TYPE = str
+CONTROL_ADDR_MASK__RAW = str
+LD_DLY_CMDA__RAW = str
+MCONTR_BUF0_WR_ADDR__RAW = str
+LD_DLY_LANE1_ODELAY__RAW = str
+MCNTRL_TILED_WINDOW_WH__TYPE = str
+MCONTR_WR_MASK__TYPE = str
+SS_MOD_PERIOD__RAW = str
+MAX_TILE_HEIGHT = int
+MCNTRL_SCANLINE_STARTADDR__RAW = str
+MCNTRL_SCANLINE_FRAME_FULL_WIDTH__RAW = str
+MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR__TYPE = str
+SS_MODE__RAW = str
+DLY_PHASE__TYPE = str
+MCONTR_TOP_0BIT_ADDR_MASK__TYPE = str
+MCONTR_TOP_STATUS_REG_ADDR__TYPE = str
+MCONTR_PHY_16BIT_WBUF_DELAY = int
+DEFAULT_STATUS_MODE__RAW = str
+DLY_LANE1_DQS_WLV_IDELAY__TYPE = str
+FRAME_WIDTH_BITS = int
+MCNTRL_TILED_STATUS_REG_CHN2_ADDR__TYPE = str
+SLEW_CMDA__TYPE = str
+MCONTR_RD_MASK__TYPE = str
+READ_BLOCK_OFFSET__RAW = str
+MCLK_PHASE = float
+SLEW_DQ__RAW = str
+FRAME_HEIGHT_BITS__TYPE = str
+DLY_DQS_IDELAY = long
+MCONTR_BUF3_RD_ADDR__TYPE = str
+DLY_DQ_ODELAY__TYPE = str
+MCONTR_PHY_16BIT_PATTERNS_TRI__RAW = str
+MCNTRL_TEST01_STATUS_REG_CHN4_ADDR__RAW = str
+SLEW_CLK__RAW = str
+MCNTRL_TEST01_CHN1_STATUS_CNTRL__TYPE = str
+WBUF_DLY_DFLT = int
+MCONTR_PHY_16BIT_WBUF_DELAY__TYPE = str
+DQTRI_FIRST = int
+MCONTR_BUF2_WR_ADDR = int
+DLY_LANE0_DQS_WLV_IDELAY__TYPE = str
+MCNTRL_SCANLINE_STATUS_CNTRL__RAW = str
+SCANLINE_EXTRA_PAGES__TYPE = str
+PHASE_WIDTH__RAW = str
+DFLT_DQS_PATTERN = int
+DLY_LANE0_DQS_WLV_IDELAY__RAW = str
+MCNTRL_TEST01_CHN2_MODE__TYPE = str
+DLY_LANE1_IDELAY__RAW = str
+MCONTR_BUF1_RD_ADDR = int
+SLEW_CLK = str
+LD_DLY_LANE1_ODELAY__TYPE = str
+MCNTRL_PS_STATUS_CNTRL = int
+TEST01_START_FRAME__TYPE = str
+SS_MODE__TYPE = str
+MCONTR_TOP_16BIT_REFRESH_ADDRESS__RAW = str
+WINDOW_Y0__TYPE = str
+MCONTR_PHY_0BIT_DLY_RST__TYPE = str
+MCONTR_BUF1_WR_ADDR__TYPE = str
+BUFFER_DEPTH32__TYPE = str
+MCONTR_TOP_16BIT_STATUS_CNTRL = int
+MCONTR_BUF4_RD_ADDR__RAW = str
+WINDOW_X0__TYPE = str
+T_RFC__TYPE = str
+WINDOW_WIDTH = int
+DQSTRI_LAST = int
+MCNTRL_TEST01_CHN1_MODE = int
+DFLT_CHN_EN__RAW = str
+MCNTRL_SCANLINE_WINDOW_STARTXY__TYPE = str
+DLY_CMDA = long
+DLY_LANE0_IDELAY__RAW = str
+MCONTR_ARBIT_ADDR = int
+MCNTRL_TEST01_CHN1_STATUS_CNTRL__RAW = str
+CLKFBOUT_DIV_REF__TYPE = str
+NUM_CYCLES_04__TYPE = str
+MCNTRL_SCANLINE_MODE__RAW = str
+READ_PATTERN_OFFSET__TYPE = str
+MCNTRL_TILED_PENDING_CNTR_BITS = int
+NUM_CYCLES_00__TYPE = str
+MAX_TILE_WIDTH__TYPE = str
+MCONTR_CMD_WR_ADDR = int
+MCONTR_BUF3_RD_ADDR__RAW = str
+CLKIN_PERIOD = int
+MCNTRL_TILED_FRAME_PAGE_RESET__TYPE = str
+MCNTRL_TEST01_MASK__RAW = str
+MCONTR_PHY_16BIT_ADDR_MASK = int
+MCNTRL_SCANLINE_STATUS_REG_CHN1_ADDR__TYPE = str
+HIGH_PERFORMANCE_MODE = str
+NUM_CYCLES_07__RAW = str
+DQTRI_LAST__RAW = str
+MCONTR_BUF1_RD_ADDR__RAW = str
+CLKFBOUT_PHASE = float
+DFLT_DQM_PATTERN = int
+MCNTRL_TILED_STATUS_REG_CHN2_ADDR__RAW = str
+NUM_XFER_BITS = int
+MCNTRL_TEST01_STATUS_REG_CHN2_ADDR = int
+DLY_DQS_ODELAY__TYPE = str
+DFLT_REFRESH_PERIOD__RAW = str
+DLY_LANE0_ODELAY__RAW = str
+MCONTR_BUF3_WR_ADDR__TYPE = str
+SCANLINE_STARTX__TYPE = str
+MCONTR_PHY_0BIT_DCI_RST__TYPE = str
+MAX_TILE_WIDTH__RAW = str
+MCNTRL_SCANLINE_WINDOW_WH__TYPE = str
+FRAME_FULL_WIDTH__RAW = str
+TILE_VSTEP__TYPE = str
+MCONTR_PHY_STATUS_CNTRL__RAW = str
+MCNTRL_TILED_WINDOW_WH__RAW = str
+MCONTR_PHY_16BIT_EXTRA__TYPE = str
+DLY_LANE0_DQS_WLV_IDELAY = long
+MCNTRL_SCANLINE_STATUS_CNTRL = int
+DLY_DM_ODELAY__RAW = str
+DLY_LANE1_IDELAY = long
+NUM_CYCLES_01__RAW = str
+MCONTR_PHY_STATUS_CNTRL__TYPE = str
+WINDOW_HEIGHT__RAW = str
+MCNTRL_TEST01_STATUS_REG_CHN2_ADDR__RAW = str
+NUM_CYCLES_02 = int
+CHNBUF_READ_LATENCY__TYPE = str
+NUM_CYCLES_LOW_BIT__TYPE = str
+FRAME_WIDTH_BITS__RAW = str
+ADDRESS_NUMBER__RAW = str
+STATUS_PSHIFTER_RDY_MASK__TYPE = str
+MCNTRL_TEST01_STATUS_REG_CHN1_ADDR__TYPE = str
+MCONTR_TOP_0BIT_ADDR__RAW = str
+TEST_INITIAL_BURST__TYPE = str
+CMD_PAUSE_BITS__RAW = str
+MCNTRL_PS_CMD__RAW = str
+MCONTR_BUF3_WR_ADDR = int
+NEWPAR = int
+MCNTRL_PS_MASK__RAW = str
+MCONTR_PHY_0BIT_CKE_EN = int
+MCNTRL_SCANLINE_WINDOW_X0Y0__TYPE = str
+BUFFER_DEPTH32 = int
+MCNTRL_TILED_CHN2_ADDR__TYPE = str
+SLEW_DQS = str
+DFLT_REFRESH_ADDR = int
+MCONTR_WR_MASK = int
+MCNTRL_SCANLINE_STATUS_REG_CHN1_ADDR = int
+TEST01_SUSPEND__RAW = str
+T_REFI__TYPE = str
+STATUS_DEPTH__RAW = str
+DFLT_DQ_TRI_ON_PATTERN__TYPE = str
+MCONTR_TOP_0BIT_ADDR_MASK__RAW = str
+TEST01_START_FRAME = int
+DQTRI_FIRST__TYPE = str
+MCONTR_PHY_0BIT_ADDR_MASK__TYPE = str
+DLY_LANE0_IDELAY__TYPE = str
+T_RFC__RAW = str
+DLY_CMDA__TYPE = str
+CLKFBOUT_MULT__TYPE = str
+WBUF_DLY_DFLT__TYPE = str
+MCONTR_PHY_0BIT_CMDA_EN__RAW = str
+STATUS_SEQ_SHFT__RAW = str
+DLY_DM_ODELAY__TYPE = str
+MCONTR_PHY_0BIT_DCI_RST__RAW = str
+REFCLK_FREQUENCY__RAW = str
+MCONTR_PHY_0BIT_DLY_RST = int
+MCNTRL_TEST01_STATUS_REG_CHN3_ADDR__TYPE = str
+TILE_VSTEP = int
+DFLT_DQS_TRI_OFF_PATTERN__TYPE = str
+SS_EN__TYPE = str
+MCONTR_PHY_0BIT_DLY_RST__RAW = str
+SCANLINE_STARTY__RAW = str
+FRAME_FULL_WIDTH__TYPE = str
+WRITE_BLOCK_OFFSET = int
+COLADDR_NUMBER__TYPE = str
+MCNTRL_SCANLINE_FRAME_FULL_WIDTH = int
+TEST01_SUSPEND__TYPE = str
+NUM_CYCLES_15__RAW = str
+MCONTR_PHY_0BIT_ADDR_MASK = int
+MCNTRL_TILED_TILE_WHS__TYPE = str
+DLY_DQ_IDELAY = long
+WINDOW_X0 = int
+DFLT_WBUF_DELAY__TYPE = str
+MCNTRL_TEST01_CHN1_STATUS_CNTRL = int
+LD_DLY_LANE0_ODELAY = int
+SCANLINE_EXTRA_PAGES = int
+READ_PATTERN_OFFSET__RAW = str
+MCNTRL_SCANLINE_CHN1_ADDR__RAW = str
+TILE_HEIGHT__RAW = str
+MCONTR_PHY_0BIT_CKE_EN__TYPE = str
+MCNTRL_TILED_MODE__TYPE = str
+DIVCLK_DIVIDE = int
+NUM_CYCLES_07__TYPE = str
+DLY_DQ_IDELAY__RAW = str
+AXI_RD_ADDR_BITS__TYPE = str
+REF_JITTER1 = float
+CONTROL_ADDR__RAW = str
+TILED_STARTY__RAW = str
+NUM_CYCLES_00__RAW = str
+DLY_DQ_ODELAY__RAW = str
+MCONTR_TOP_16BIT_ADDR_MASK__RAW = str
+MCNTRL_TILED_PENDING_CNTR_BITS__RAW = str
+NUM_CYCLES_14__TYPE = str
+TILED_EXTRA_PAGES = int
+MCNTRL_PS_EN_RST__RAW = str
+MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR__RAW = str
+CLK_PHASE__RAW = str
+MCONTR_RD_MASK__RAW = str
+MCONTR_PHY_16BIT_ADDR__TYPE = str
+TILED_STARTY = int
+TILED_STARTX = int
+AXI_WR_ADDR_BITS__RAW = str
+MCONTR_BUF3_RD_ADDR = int
+DFLT_REFRESH_PERIOD__TYPE = str
+MCNTRL_TILED_FRAME_FULL_WIDTH__RAW = str
+MCNTRL_TILED_MASK = int
+NUM_CYCLES_03__RAW = str
+MCONTR_BUF1_WR_ADDR__RAW = str
+MCONTR_PHY_16BIT_ADDR_MASK__RAW = str
+DLY_LANE1_DQS_WLV_IDELAY = long
+MCNTRL_TILED_WINDOW_WH = int
+CLKFBOUT_PHASE__TYPE = str
+NUM_CYCLES_06__RAW = str
+MCNTRL_TILED_WINDOW_X0Y0__TYPE = str
+NUM_XFER_BITS__RAW = str
+MCNTRL_TILED_WINDOW_STARTXY__RAW = str
+DLY_CMDA_ODELAY = long
+MCONTR_TOP_0BIT_ADDR = int
+MCNTRL_SCANLINE_MODE = int
+MCONTR_ARBIT_ADDR_MASK = int
+NUM_CYCLES_05__RAW = str
+MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR = int
+MCNTRL_PS_CMD = int
+MCNTRL_SCANLINE_CHN3_ADDR__TYPE = str
+STATUS_2LSB_SHFT__RAW = str
+WBUF_DLY_WLV__RAW = str
+MCONTR_TOP_0BIT_REFRESH_EN = int
+MCNTRL_TILED_STATUS_REG_CHN4_ADDR = int
+SLEW_CMDA__RAW = str
+MCNTRL_TEST01_CHN2_MODE__RAW = str
+LD_DLY_PHASE__RAW = str
+MCONTR_TOP_STATUS_REG_ADDR__RAW = str
+MCONTR_ARBIT_ADDR__TYPE = str
+DFLT_DQS_TRI_ON_PATTERN = int
+MCNTRL_TEST01_STATUS_REG_CHN3_ADDR__RAW = str
+DFLT_CHN_EN = int
+LD_DLY_LANE0_IDELAY = int
+DLY_DQS_ODELAY = long
+ADDRESS_NUMBER = int
+NUM_CYCLES_01__TYPE = str
+MCLK_PHASE__TYPE = str
+MCNTRL_TILED_TILE_WHS__RAW = str
+MCNTRL_TILED_STATUS_REG_CHN4_ADDR__TYPE = str
+DQTRI_LAST = int
+CMD_PAUSE_BITS__TYPE = str
+MCONTR_BUF2_RD_ADDR = int
+MCONTR_BUF2_WR_ADDR__TYPE = str
+NUM_CYCLES_02__TYPE = str
+DQTRI_LAST__TYPE = str
+TILE_WIDTH = int
+FRAME_HEIGHT_BITS__RAW = str
+MCNTRL_TILED_STARTADDR = int
+WINDOW_HEIGHT__TYPE = str
+MCNTRL_TILED_FRAME_FULL_WIDTH = int
+TILE_HEIGHT__TYPE = str
+MCNTRL_TILED_CHN4_ADDR__TYPE = str
+FRAME_HEIGHT_BITS = int
+MCONTR_PHY_16BIT_ADDR_MASK__TYPE = str
+SS_EN__RAW = str
+LD_DLY_LANE0_IDELAY__TYPE = str
+MCONTR_PHY_0BIT_ADDR__RAW = str
+CLKFBOUT_PHASE__RAW = str
+MCONTR_PHY_0BIT_DLY_SET__RAW = str
+NUM_CYCLES_08__RAW = str
+DFLT_DQ_TRI_OFF_PATTERN = int
+NUM_CYCLES_11__RAW = str
+MCNTRL_PS_STATUS_CNTRL__RAW = str
+PHASE_WIDTH = int
+SDCLK_PHASE = float
+DFLT_DQS_PATTERN__RAW = str
+MCNTRL_TEST01_CHN4_MODE__TYPE = str
+SLEW_CMDA = str
+REFCLK_FREQUENCY = float
+MCNTRL_PS_STATUS_CNTRL__TYPE = str
+MCONTR_PHY_16BIT_ADDR = int
+REF_JITTER1__TYPE = str
+MCNTRL_SCANLINE_MODE__TYPE = str
+MCONTR_PHY_16BIT_PATTERNS_TRI = int
+DLY_CMDA__RAW = str
+NUM_CYCLES_LOW_BIT = int
+READ_BLOCK_OFFSET = int
+T_REFI__RAW = str
+STATUS_MSB_RSHFT = int
+BUFFER_DEPTH32__RAW = str
+CLKIN_PERIOD__TYPE = str
+DIVCLK_DIVIDE__RAW = str
+DLY_LANE0_ODELAY__TYPE = str
+COLADDR_NUMBER = int
+SDCLK_PHASE__TYPE = str
+SCANLINE_STARTY__TYPE = str
+REFRESH_OFFSET__RAW = str
+MCNTRL_TEST01_CHN2_MODE = int
+MCNTRL_TEST01_CHN1_MODE__RAW = str
+MCONTR_BUF4_RD_ADDR__TYPE = str
+LD_DLY_LANE0_ODELAY__TYPE = str
+MCONTR_TOP_16BIT_ADDR__RAW = str
+MCNTRL_SCANLINE_PENDING_CNTR_BITS = int
+DFLT_DQS_TRI_ON_PATTERN__TYPE = str
+MCONTR_PHY_0BIT_SDRST_ACT__TYPE = str
+TILED_KEEP_OPEN__RAW = str
+MCNTRL_SCANLINE_STARTADDR = int
+MCONTR_TOP_0BIT_ADDR__TYPE = str
+CLKFBOUT_MULT_REF__TYPE = str
+MCNTRL_PS_CMD__TYPE = str
+STATUS_MSB_RSHFT__RAW = str
+STATUS_PSHIFTER_RDY_MASK = int
+NUM_CYCLES_04__RAW = str
+MCNTRL_TEST01_MASK__TYPE = str
+STATUS_DEPTH = int
+MCNTRL_SCANLINE_WINDOW_STARTXY__RAW = str
+NUM_CYCLES_15__TYPE = str
+MCNTRL_TILED_MODE__RAW = str
+DLY_SET = int
+MCNTRL_TILED_CHN2_ADDR__RAW = str
+DQTRI_FIRST__RAW = str
+DIVCLK_DIVIDE__TYPE = str
+MCONTR_TOP_0BIT_MCONTR_EN__RAW = str
+MCNTRL_SCANLINE_FRAME_PAGE_RESET__TYPE = str
+VERBOSE__RAW = str
+WBUF_DLY_WLV = int
+MCONTR_BUF3_WR_ADDR__RAW = str
+MCNTRL_TEST01_CHN3_MODE = int
+LD_DLY_PHASE__TYPE = str
+MCONTR_PHY_0BIT_ADDR__TYPE = str
+TEST_INITIAL_BURST__RAW = str
+MCNTRL_SCANLINE_FRAME_PAGE_RESET__RAW = str
+MCONTR_ARBIT_ADDR_MASK__RAW = str
+DFLT_WBUF_DELAY = int
+DLY_DQ_ODELAY = long
+STATUS_ADDR_MASK__RAW = str
+MCNTRL_SCANLINE_CHN3_ADDR = int
+DLY_SET__TYPE = str
+MCONTR_TOP_16BIT_ADDR = int
+MCONTR_BUF1_RD_ADDR__TYPE = str
+DLY_DM_ODELAY = long
+MCONTR_TOP_16BIT_REFRESH_ADDRESS = int
+DFLT_DQS_TRI_OFF_PATTERN__RAW = str
+FRAME_FULL_WIDTH = int
+NUM_CYCLES_13 = int
+NUM_CYCLES_12 = int
+NUM_CYCLES_11 = int
+NUM_CYCLES_10 = int
+NUM_CYCLES_15 = int
+NUM_CYCLES_14 = int
+DLY_PHASE__RAW = str
+MCNTRL_TEST01_CHN4_MODE = int
+MCNTRL_SCANLINE_WINDOW_WH = int
+TILE_WIDTH__RAW = str
+WINDOW_WIDTH__TYPE = str
+MCNTRL_TEST01_MASK = int
+SLEW_CLK__TYPE = str
+DFLT_INV_CLK_DIV = int
+DEFAULT_STATUS_MODE__TYPE = str
+CLKFBOUT_DIV_REF__RAW = str
+CMD_PAUSE_BITS = int
+MCNTRL_PS_STATUS_REG_ADDR = int
+ADDRESS_NUMBER__TYPE = str
+MCNTRL_SCANLINE_FRAME_FULL_WIDTH__TYPE = str
+LD_DLY_LANE1_IDELAY__RAW = str
+MCNTRL_TEST01_CHN4_STATUS_CNTRL = int
+TEST01_START_FRAME__RAW = str
+WRITE_BLOCK_OFFSET__RAW = str
+MCNTRL_TILED_MODE = int
+NUM_CYCLES_09__TYPE = str
+MCNTRL_TILED_WINDOW_STARTXY__TYPE = str
+LD_DLY_LANE0_IDELAY__RAW = str
+FRAME_WIDTH_BITS__TYPE = str
+MCNTRL_TEST01_CHN2_STATUS_CNTRL__RAW = str
+TILED_STARTY__TYPE = str
+DFLT_DQM_PATTERN__RAW = str
+MCNTRL_TILED_CHN4_ADDR__RAW = str
+MCNTRL_TILED_FRAME_PAGE_RESET__RAW = str
+MCONTR_CMD_WR_ADDR__TYPE = str
+STATUS_DEPTH__TYPE = str
+SLEW_DQ__TYPE = str
+CLKIN_PERIOD__RAW = str
+INITIALIZE_OFFSET = int
+MCNTRL_PS_MASK__TYPE = str
+CLK_DIV_PHASE__RAW = str
+LD_DLY_LANE1_IDELAY = int
+MCONTR_PHY_16BIT_PATTERNS__TYPE = str
+MCONTR_PHY_0BIT_CKE_EN__RAW = str
+NUM_CYCLES_02__RAW = str
+TEST01_NEXT_PAGE__RAW = str
+DQSTRI_LAST__RAW = str
+WRITELEV_OFFSET__TYPE = str
+NUM_CYCLES_06__TYPE = str
+STATUS_ADDR_MASK__TYPE = str
+SCANLINE_STARTX__RAW = str
+SLEW_DQS__RAW = str
+MCNTRL_TILED_WINDOW_X0Y0 = int
+MCONTR_TOP_16BIT_REFRESH_PERIOD__RAW = str
+MCONTR_PHY_0BIT_DLY_SET = int
+WRITELEV_OFFSET__RAW = str
+MCONTR_BUF4_WR_ADDR__TYPE = str
+MCONTR_PHY_0BIT_ADDR = int
+MCONTR_PHY_16BIT_EXTRA__RAW = str
+MCNTRL_TEST01_STATUS_REG_CHN2_ADDR__TYPE = str
+MAX_TILE_HEIGHT__TYPE = str
+MCONTR_TOP_16BIT_CHN_EN__RAW = str
+NUM_CYCLES_08__TYPE = str
+STATUS_SEQ_SHFT = int
+NUM_CYCLES_LOW_BIT__RAW = str
+MCONTR_PHY_16BIT_WBUF_DELAY__RAW = str
+READ_PATTERN_OFFSET = int
+CLK_PHASE__TYPE = str
+NUM_CYCLES_05__TYPE = str
+MCNTRL_TILED_PENDING_CNTR_BITS__TYPE = str
+MCONTR_RD_MASK = int
+MCONTR_PHY_16BIT_PATTERNS = int
+NEWPAR__RAW = str
+MCLK_PHASE__RAW = str
+MCONTR_TOP_16BIT_REFRESH_PERIOD = int
+T_REFI = int
+MCNTRL_TILED_FRAME_FULL_WIDTH__TYPE = str
+STATUS_SEQ_SHFT__TYPE = str
+DFLT_CHN_EN__TYPE = str
+MCNTRL_SCANLINE_PENDING_CNTR_BITS__RAW = str
+MCONTR_TOP_STATUS_REG_ADDR = int
+MCNTRL_PS_ADDR = int
+MCNTRL_TILED_STATUS_REG_CHN4_ADDR__RAW = str
+MCONTR_TOP_16BIT_STATUS_CNTRL__RAW = str
+MCONTR_PHY_16BIT_PATTERNS__RAW = str
+MCONTR_PHY_0BIT_ADDR_MASK__RAW = str
+CLKFBOUT_MULT_REF__RAW = str
+DLY_LD_MASK__RAW = str
+MCNTRL_TILED_CHN2_ADDR = int
+MCNTRL_TILED_STATUS_CNTRL = int
+LD_DLY_LANE1_ODELAY = int
+DLY_CMDA_ODELAY__RAW = str
+MCNTRL_TILED_WINDOW_X0Y0__RAW = str
+SS_EN = str
+DLY_LANE0_ODELAY = long
+CLKFBOUT_DIV_REF = int
+WRITELEV_OFFSET = int
+MCONTR_TOP_16BIT_ADDR_MASK__TYPE = str
+VERBOSE__TYPE = str
+TILED_KEEP_OPEN = int
+MCNTRL_SCANLINE_MASK__RAW = str
+MCNTRL_SCANLINE_WINDOW_STARTXY = int
+TEST_INITIAL_BURST = int
+MCONTR_ARBIT_ADDR__RAW = str
+MCNTRL_TEST01_ADDR = int
+MCONTR_TOP_0BIT_MCONTR_EN__TYPE = str
+MCONTR_BUF4_WR_ADDR__RAW = str
+TILED_KEEP_OPEN__TYPE = str
+CONTROL_ADDR_MASK__TYPE = str
+MCONTR_PHY_STATUS_REG_ADDR__RAW = str
+HIGH_PERFORMANCE_MODE__RAW = str
+MCNTRL_TEST01_CHN4_MODE__RAW = str
+DFLT_DQM_PATTERN__TYPE = str
+STATUS_ADDR__TYPE = str
+CLK_DIV_PHASE__TYPE = str
+MCONTR_PHY_0BIT_CMDA_EN = int
+MCNTRL_SCANLINE_CHN3_ADDR__RAW = str
+REFRESH_OFFSET__TYPE = str
+DFLT_INV_CLK_DIV__TYPE = str
+MAX_TILE_WIDTH = int
+CHNBUF_READ_LATENCY__RAW = str
+MCONTR_BUF4_RD_ADDR = int
+SS_MOD_PERIOD__TYPE = str
+MCNTRL_PS_STATUS_REG_ADDR__TYPE = str
+DFLT_DQ_TRI_OFF_PATTERN__RAW = str
+IBUF_LOW_PWR__TYPE = str
+LD_DLY_PHASE = int
+SDCLK_PHASE__RAW = str
+NUM_CYCLES_10__RAW = str
+INITIALIZE_OFFSET__RAW = str
+CMD_DONE_BIT__RAW = str
+MCONTR_TOP_0BIT_REFRESH_EN__TYPE = str
+CLK_DIV_PHASE = float
+MCONTR_TOP_16BIT_REFRESH_PERIOD__TYPE = str
+MCNTRL_TEST01_CHN4_STATUS_CNTRL__RAW = str
+MCONTR_BUF0_WR_ADDR__TYPE = str
+FRAME_START_ADDRESS__RAW = str
+NUM_CYCLES_12__RAW = str
+SLEW_DQS__TYPE = str
+MCNTRL_TILED_STARTADDR__TYPE = str
+DLY_LD_MASK = int