implemented @file in the test_mcntrl.py command line

py393/.settings/org.eclipse.core.resources.prefs

 eclipse.preferences.version=1
 encoding/import_verilog_parameters.py=utf-8
-encoding/test1.py=utf-8
+encoding/test_mcntrl.py=utf-8

py393/args

+-v
+-d aaa=bbb
+-d ccc=ddd
+-f ../system_defines.vh
+-f ../includes/x393_parameters.vh  ../includes/x393_localparams.vh
+-p NEWPAR='h3ff
+-c write_mem 0x377 25
+-c read_mem 0x3ff
+-i
\ No newline at end of file

py393/import_verilog_parameters.py

@@ -51,11 +51,12 @@ class ImportVerilogParameters(object):
     parameters={}
     conditions=[True]
     rootPath=None
-    verbose=1
+    verbose=3
     '''
     parameters - dictionalry of already known parameters, defines - defined macros
     '''
     def __init__(self, parameters=None,defines=None,rootPath=None):
+        print("parameters=%s"%str(parameters))
         '''
         Constructor
         '''
@@ -337,11 +338,11 @@ class ImportVerilogParameters(object):
             pass
         def parsePrimary(start=0):
             return useBest(useBest(useBest(parseString(start),parseNumber(start)),parseRealNumber(start)),parseParameter(start))
-        def parsePraamryOrBinary(start=0):
+        def parsePrimaryOrBinary(start=0):
             operand1=parsePrimary(start)
             if (self.verbose>2) and (start !=0):
-                print ("parsePraamryOrBinary(start=%d), line=%s, result=%s"%(start,line,str(operand1)))
-                
+                print ("parsePrimaryOrBinary(start=%d), line=%s, result=%s"%(start,line,str(operand1)))
+            if not operand1: print (line)    
             opStart=skipWS(operand1[2])
             if opStart == len(line): # just primary
                 return operand1
@@ -394,7 +395,7 @@ class ImportVerilogParameters(object):
                     return None
                 endPos=skipWS(endPos+1)
                 return (exp[0],"[%d:0]"%(exp[1]-1),endPos)
-            return parsePraamryOrBinary(start)
+            return parsePrimaryOrBinary(start)
         '''
         parseExpression top level code
         no support for bit select, &&, ||, ~ ! ? and more... 

py393/test1.py → py393/test_mcntrl.py

@@ -30,7 +30,7 @@ __maintainer__ = "Andrey Filippov"
 __email__ = "andrey@elphel.com"
 __status__ = "Development"
 '''
-~/git/x393/py393$ ./test1.py -vv -f/home/andrey/git/x393/system_defines.vh -f /home/andrey/git/x393/includes/x393_parameters.vh  /home/andrey/git/x393/includes/x393_localparams.vh -pNEWPAR=\'h3ff -c write_mem 0x377 25 -c read_mem 0x3ff -i
+./test_mcntrl.py -v -f../system_defines.vh -f ../includes/x393_parameters.vh  ../includes/x393_localparams.vh -pNEWPAR=\'h3ff -c write_mem 0x377 25 -c read_mem 0x3ff -i -d aaa=bbb -d ccc=ddd
 
 '''
 import sys
@@ -81,7 +81,7 @@ def extractTasks(obj,inst):
             func_args=obj.__dict__[name].func_code.co_varnames[1:obj.__dict__[name].func_code.co_argcount]
             callableTasks[name]={'func':obj.__dict__[name],'args':func_args,'inst':inst}
 def execTask(commandLine):
-    result=None
+#    result=None
     cmdList=commandLine #.split()
     try:
         funcName=cmdList[0]
@@ -153,37 +153,68 @@ USAGE
     preParameters={}
     try:
         # Setup argument parser
-        parser = ArgumentParser(description=program_license, formatter_class=RawDescriptionHelpFormatter)
+        parser = ArgumentParser(description=program_license, formatter_class=RawDescriptionHelpFormatter,fromfile_prefix_chars='@')
         parser.add_argument("-v", "--verbose", dest="verbose", action="count", help="set verbosity level [default: %(default)s]")
         parser.add_argument('-V', '--version', action='version', version=program_version_message)
 #        parser.add_argument(                   dest="paths", help="Verilog include files with parameter definitions [default: %(default)s]", metavar="path", nargs='*')
-        parser.add_argument("-f", "--icludeFile",  dest="paths", action="append", help="Verilog include files with parameter definitions [default: %(default)s]", metavar="path", nargs='*')
-        parser.add_argument("-d", "--define",  dest="defines", action="append", help="Define macro(s)" )
-        parser.add_argument("-p", "--parameter",  dest="parameters", action="append", help="Define parameter(s) as name=value" )
-        parser.add_argument("-c", "--command",  dest="commands", action="append", help="execute command" , nargs='*')
+        parser.add_argument("-f", "--icludeFile",  dest="paths", action="append", default=[],
+                             help="Verilog include files with parameter definitions [default: %(default)s]", metavar="path", nargs='*')
+        parser.add_argument("-d", "--define",  dest="defines", action="append", default=[], help="Define macro(s)" , nargs='*' )
+        parser.add_argument("-p", "--parameter",  dest="parameters", action="append", default=[], help="Define parameter(s) as name=value" , nargs='*' )
+        parser.add_argument("-c", "--command",  dest="commands", action="append", default=[], help="execute command" , nargs='*')
         parser.add_argument("-i", "--interactive", dest="interactive", action="store_true", help="enter interactive mode [default: %(default)s]")
 
         # Process arguments
         args = parser.parse_args()
-#        paths = args.paths
+        #print("--- defines=%s"%    str(args.defines))
+        #print("--- paths=%s"%      str(args.paths))
+        #print("--- parameters=%s"% str(args.parameters))
+        #print("--- commands=%s"%   str(args.commands))
+            #        paths = args.paths
+        verbose = args.verbose
         paths=[]
+        if (args.paths):
             for group in args.paths:
-            paths+=group
-        verbose = args.verbose
-        if args.defines:
-            for predef in args.defines:
+                for item in group:
+                    paths+=item.split()
+        #print("+++ paths=%s"%      str(paths))
+        if (args.defines):
+            defines=[]
+            for group in args.defines:
+                for item in group:
+                    defines+=item.split()
+            for predef in defines:
                 kv=predef.split("=")
                 if len(kv)<2:
                     kv.append("")
                 preDefines[kv[0].strip("`")]=kv[1]
+        #print("+++ defines=%s"%      str(preDefines))
+
         if verbose > 0:
 #            print("Verbose mode on "+hex(verbose))
-            args.parameters.append('VERBOSE=%d'%verbose) # add as verilog parameter
-        if args.parameters:
-            for prePars in args.parameters:
+            args.parameters.append(['VERBOSE=%d'%verbose]) # add as verilog parameter
+        
+        if (args.parameters):
+            parameters=[]
+            for group in args.parameters:
+                for item in group:
+                    parameters+=item.split()
+            for prePars in parameters:
                 kv=prePars.split("=")
                 if len(kv)>1:
-                    preParameters[kv[0]]=(kv[1],"RAW",kv[1]) # todo - need to go through the parser
+                    preParameters[kv[0]]=(kv[1],"RAW",kv[1])
+        #print("+++ parameters=%s"%      str(preParameters))
+        
+        commands=[]
+        if (args.commands):
+            for group in args.commands:
+                cmd=[]
+                for item in group:
+                    cmd+=item.split()
+                commands.append(cmd)    
+        #print("+++ commands=%s"%      str(commands))
+        
+                    
 
     except KeyboardInterrupt:
         ### handle keyboard interrupt ###
@@ -200,7 +231,7 @@ USAGE
     if verbose > 3: print ('paths='+str(paths))   
     if verbose > 3: print ('defines='+str(args.defines))   
     if verbose > 3: print ('parameters='+str(args.parameters)) 
-    if verbose > 3: print ('comamnds='+str(args.commands)) 
+    if verbose > 3: print ('comamnds='+str(commands)) 
     for path in paths:
         if verbose > 2: print ('path='+str(path))
         ### do something with inpath ###
@@ -274,7 +305,7 @@ USAGE
                     print ("Usage:\n%s %s"%(funcName,sFuncArgs))
                     print ("exception message:"+str(e))
      
-    for cmdLine in args.commands:
+    for cmdLine in commands:
         print ('Running task: '+str(cmdLine))
         rslt= execTask(cmdLine)
         print ('    Result: '+str(rslt))
@@ -319,8 +350,8 @@ USAGE
 
             elif (line == 'defines') or (line == 'macros'):
                 defines= ivp.getDefines()
-                for macro,val in sorted(parameters.items()):
-                    print ("`"+macro+": "+val)        
+                for macro,val in sorted(defines.items()):
+                    print ("`"+macro+": "+str(val))        
 
 #                for macro in defines:
 #                    print ("`"+macro+": "+defines[macro])        

py393/x393_mcntrl_tests.py

@@ -91,6 +91,30 @@ class X393McntrlTests(object):
                        ((0,1)[write_mem],1), # write_mem,
                        ((0,1)[enable],   1), #enable,
                        ((1,0)[chn_reset],1)) # ~chn_reset};
+    def task_set_up(self,
+                    set_per_pin_delays):
+# set dq /dqs tristate on/off patterns
+        self.x393_mcntrl_timing.axi_set_tristate_patterns()
+# set patterns for DM (always 0) and DQS - always the same (may try different for write lev.)
+        self.x393_mcntrl_timing.axi_set_dqs_dqm_patterns()
+# prepare all sequences
+        self.set_all_sequences;
+# prepare write buffer    
+        self.x393_mcntrl_buffers.write_block_buf_chn(0,0,256); # fill block memory (channel, page, number)
+# set all delays
+##axi_set_delays - from tables, per-pin
+        if set_per_pin_delays:
+            self.x393_mcntrl_timing.axi_set_delays() # set all individual delays, aslo runs axi_set_phase()
+        else:
+            self.x393_mcntrl_timing.axi_set_same_delays(
+                                                        self.DLY_DQ_IDELAY,
+                                                        self.DLY_DQ_ODELAY,
+                                                        self.DLY_DQS_IDELAY,
+                                                        self.DLY_DQS_ODELAY,
+                                                        self.DLY_DM_ODELAY,
+                                                        self.DLY_CMDA_ODELAY)
+# set clock phase relative to DDR clk
+        self.x393_mcntrl_timing.axi_set_phase(self.DLY_PHASE);
 
     def set_all_sequences(self):
         if self.verbose>0: print("SET MRS")