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Commit e3d5b404 authored by Andrey Filippov's avatar Andrey Filippov
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modified scanline mode to work with SDRAM page crossing (by splitting in 2), debugging read mode

parent 547054f6
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Showing with 464 additions and 151 deletions
memctrl/cmd_encod_linear_mux.v
View file @ e3d5b404
......@@ -32,6 +32,7 @@ module cmd_encod_linear_mux#(
input [ADDRESS_NUMBER-1:0] row0, // memory row
input [COLADDR_NUMBER-4:0] start_col0, // start memory column in 8-bursts
input [5:0] num128_0, // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
input partial0, // first of the two halves of a split tile (caused by memory page crossing)
input start0, // start generating commands
`endif
`ifdef def_scanline_chn1
......@@ -39,6 +40,7 @@ module cmd_encod_linear_mux#(
input [ADDRESS_NUMBER-1:0] row1, // memory row
input [COLADDR_NUMBER-4:0] start_col1, // start memory column in 8-bursts
input [5:0] num128_1, // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
input partial1, // first of the two halves of a split tile (caused by memory page crossing)
input start1, // start generating commands
`endif
`ifdef def_scanline_chn2
......@@ -46,6 +48,7 @@ module cmd_encod_linear_mux#(
input [ADDRESS_NUMBER-1:0] row2, // memory row
input [COLADDR_NUMBER-4:0] start_col2, // start memory column in 8-bursts
input [5:0] num128_2, // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
input partial2, // first of the two halves of a split tile (caused by memory page crossing)
input start2, // start generating commands
`endif
`ifdef def_scanline_chn3
......@@ -53,6 +56,7 @@ module cmd_encod_linear_mux#(
input [ADDRESS_NUMBER-1:0] row3, // memory row
input [COLADDR_NUMBER-4:0] start_col3, // start memory column in 8-bursts
input [5:0] num128_3, // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
input partial3, // first of the two halves of a split tile (caused by memory page crossing)
input start3, // start generating commands
`endif
`ifdef def_scanline_chn4
......@@ -60,6 +64,7 @@ module cmd_encod_linear_mux#(
input [ADDRESS_NUMBER-1:0] row4, // memory row
input [COLADDR_NUMBER-4:0] start_col4, // start memory column in 8-bursts
input [5:0] num128_4, // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
input partial4, // first of the two halves of a split tile (caused by memory page crossing)
input start4, // start generating commands
`endif
......@@ -68,6 +73,7 @@ module cmd_encod_linear_mux#(
input [ADDRESS_NUMBER-1:0] row5, // memory row
input [COLADDR_NUMBER-4:0] start_col5, // start memory column in 8-bursts
input [5:0] num128_5, // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
input partial5, // first of the two halves of a split tile (caused by memory page crossing)
input start5, // start generating commands
`endif
......@@ -76,6 +82,7 @@ module cmd_encod_linear_mux#(
input [ADDRESS_NUMBER-1:0] row6, // memory row
input [COLADDR_NUMBER-4:0] start_col6, // start memory column in 8-bursts
input [5:0] num128_6, // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
input partial6, // first of the two halves of a split tile (caused by memory page crossing)
input start6, // start generating commands
`endif
`ifdef def_scanline_chn7
......@@ -83,6 +90,7 @@ module cmd_encod_linear_mux#(
input [ADDRESS_NUMBER-1:0] row7, // memory row
input [COLADDR_NUMBER-4:0] start_col7, // start memory column in 8-bursts
input [5:0] num128_7, // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
input partial7, // first of the two halves of a split tile (caused by memory page crossing)
input start7, // start generating commands
`endif
`ifdef def_scanline_chn8
......@@ -90,6 +98,7 @@ module cmd_encod_linear_mux#(
input [ADDRESS_NUMBER-1:0] row8, // memory row
input [COLADDR_NUMBER-4:0] start_col8, // start memory column in 8-bursts
input [5:0] num128_8, // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
input partial8, // first of the two halves of a split tile (caused by memory page crossing)
input start8, // start generating commands
`endif
`ifdef def_scanline_chn9
......@@ -97,6 +106,7 @@ module cmd_encod_linear_mux#(
input [ADDRESS_NUMBER-1:0] row9, // memory row
input [COLADDR_NUMBER-4:0] start_col9, // start memory column in 8-bursts
input [5:0] num128_9, // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
input partial9, // first of the two halves of a split tile (caused by memory page crossing)
input start9, // start generating commands
`endif
`ifdef def_scanline_chn10
......@@ -104,6 +114,7 @@ module cmd_encod_linear_mux#(
input [ADDRESS_NUMBER-1:0] row10, // memory row
input [COLADDR_NUMBER-4:0] start_col10, // start memory column in 8-bursts
input [5:0] num128_10, // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
input partial10, // first of the two halves of a split tile (caused by memory page crossing)
input start10, // start generating commands
`endif
`ifdef def_scanline_chn11
......@@ -111,6 +122,7 @@ module cmd_encod_linear_mux#(
input [ADDRESS_NUMBER-1:0] row11, // memory row
input [COLADDR_NUMBER-4:0] start_col11, // start memory column in 8-bursts
input [5:0] num128_11, // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
input partial11, // first of the two halves of a split tile (caused by memory page crossing)
input start11, // start generating commands
`endif
`ifdef def_scanline_chn12
......@@ -118,6 +130,7 @@ module cmd_encod_linear_mux#(
input [ADDRESS_NUMBER-1:0] row12, // memory row
input [COLADDR_NUMBER-4:0] start_col12, // start memory column in 8-bursts
input [5:0] num128_12, // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
input partial12, // first of the two halves of a split tile (caused by memory page crossing)
input start12, // start generating commands
`endif
`ifdef def_scanline_chn13
......@@ -125,6 +138,7 @@ module cmd_encod_linear_mux#(
input [ADDRESS_NUMBER-1:0] row13, // memory row
input [COLADDR_NUMBER-4:0] start_col13, // start memory column in 8-bursts
input [5:0] num128_13, // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
input partial13, // first of the two halves of a split tile (caused by memory page crossing)
input start13, // start generating commands
`endif
`ifdef def_scanline_chn14
......@@ -132,6 +146,7 @@ module cmd_encod_linear_mux#(
input [ADDRESS_NUMBER-1:0] row14, // memory row
input [COLADDR_NUMBER-4:0] start_col14, // start memory column in 8-bursts
input [5:0] num128_14, // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
input partial14, // first of the two halves of a split tile (caused by memory page crossing)
input start14, // start generating commands
`endif
`ifdef def_scanline_chn15
......@@ -139,12 +154,14 @@ module cmd_encod_linear_mux#(
input [ADDRESS_NUMBER-1:0] row15, // memory row
input [COLADDR_NUMBER-4:0] start_col15, // start memory column in 8-bursts
input [5:0] num128_15, // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
input partial15, // first of the two halves of a split tile (caused by memory page crossing)
input start15, // start generating commands
`endif
output [2:0] bank, // bank address
output [ADDRESS_NUMBER-1:0] row, // memory row
output [COLADDR_NUMBER-4:0] start_col, // start memory column in 8-bursts
output [5:0] num128, // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
output partial, // first of the two halves of a split tile (caused by memory page crossing)
output start_rd, // start generating commands in cmd_encod_linear_rd
output start_wr // start generating commands in cmd_encod_linear_wr
);
......@@ -152,6 +169,7 @@ module cmd_encod_linear_mux#(
reg [ADDRESS_NUMBER-1:0] row_r; // memory row
reg [COLADDR_NUMBER-4:0] start_col_r;// start memory column in 8-bursts
reg [5:0] num128_r; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
reg partial_r;
reg start_rd_r; // start generating commands
reg start_wr_r; // start generating commands
......@@ -159,15 +177,17 @@ module cmd_encod_linear_mux#(
wire [ADDRESS_NUMBER-1:0] row_w; // memory row
wire [COLADDR_NUMBER-4:0] start_col_w;// start memory column in 8-bursts
wire [5:0] num128_w; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
wire partial_w;
wire start_rd_w; // start generating commands
wire start_wr_w; // start generating commands
localparam PAR_WIDTH=3+ADDRESS_NUMBER+COLADDR_NUMBER-3+6+2;
localparam PAR_WIDTH=3+ADDRESS_NUMBER+COLADDR_NUMBER-3+6+2+1;
localparam [PAR_WIDTH-1:0] PAR_DEFAULT=0;
assign bank = bank_r;
assign row = row_r;
assign start_col = start_col_r;
assign num128 = num128_r;
assign partial= partial_r;
assign start_rd = start_rd_r;
assign start_wr = start_wr_r;
localparam [15:0] CHN_RD_MEM={
......@@ -253,54 +273,54 @@ module cmd_encod_linear_mux#(
`endif
assign {bank_w, row_w, start_col_w, num128_w, start_rd_w, start_wr_w} = 0
assign {bank_w, row_w, start_col_w, num128_w, partial_w, start_rd_w, start_wr_w} = 0
`ifdef def_scanline_chn0
| (start0?{bank0, row0, start_col0, num128_0,CHN_RD_MEM[0],~CHN_RD_MEM[0]}:PAR_DEFAULT)
| (start0?{bank0, row0, start_col0, num128_0, partial0, CHN_RD_MEM[0],~CHN_RD_MEM[0]}:PAR_DEFAULT)
`endif
`ifdef def_scanline_chn1
| (start1?{bank1, row1, start_col1, num128_1,CHN_RD_MEM[1],~CHN_RD_MEM[1]}:PAR_DEFAULT)
| (start1?{bank1, row1, start_col1, num128_1, partial1, CHN_RD_MEM[1],~CHN_RD_MEM[1]}:PAR_DEFAULT)
`endif
`ifdef def_scanline_chn2
| (start2?{bank2, row2, start_col2, num128_2,CHN_RD_MEM[2],~CHN_RD_MEM[2]}:PAR_DEFAULT)
| (start2?{bank2, row2, start_col2, num128_2, partial2, CHN_RD_MEM[2],~CHN_RD_MEM[2]}:PAR_DEFAULT)
`endif
`ifdef def_scanline_chn3
| (start3?{bank3, row3, start_col3, num128_3,CHN_RD_MEM[3],~CHN_RD_MEM[3]}:PAR_DEFAULT)
| (start3?{bank3, row3, start_col3, num128_3, partial3, CHN_RD_MEM[3],~CHN_RD_MEM[3]}:PAR_DEFAULT)
`endif
`ifdef def_scanline_chn4
| (start4?{bank4, row4, start_col4, num128_4,CHN_RD_MEM[4],~CHN_RD_MEM[4]}:PAR_DEFAULT)
| (start4?{bank4, row4, start_col4, num128_4, partial4, CHN_RD_MEM[4],~CHN_RD_MEM[4]}:PAR_DEFAULT)
`endif
`ifdef def_scanline_chn5
| (start5?{bank5, row5, start_col5, num128_5,CHN_RD_MEM[5],~CHN_RD_MEM[5]}:PAR_DEFAULT)
| (start5?{bank5, row5, start_col5, num128_5, partial5, CHN_RD_MEM[5],~CHN_RD_MEM[5]}:PAR_DEFAULT)
`endif
`ifdef def_scanline_chn6
| (start6?{bank6, row6, start_col6, num128_6,CHN_RD_MEM[6],~CHN_RD_MEM[6]}:PAR_DEFAULT)
| (start6?{bank6, row6, start_col6, num128_6, partial6, CHN_RD_MEM[6],~CHN_RD_MEM[6]}:PAR_DEFAULT)
`endif
`ifdef def_scanline_chn7
| (start7?{bank7, row7, start_col7, num128_7,CHN_RD_MEM[7],~CHN_RD_MEM[7]}:PAR_DEFAULT)
| (start7?{bank7, row7, start_col7, num128_7, partial7, CHN_RD_MEM[7],~CHN_RD_MEM[7]}:PAR_DEFAULT)
`endif
`ifdef def_scanline_chn8
| (start8?{bank8, row8, start_col8, num128_8,CHN_RD_MEM[8],~CHN_RD_MEM[8]}:PAR_DEFAULT)
| (start8?{bank8, row8, start_col8, num128_8, partial8, CHN_RD_MEM[8],~CHN_RD_MEM[8]}:PAR_DEFAULT)
`endif
`ifdef def_scanline_chn9
| (start9?{bank9, row9, start_col9, num128_9,CHN_RD_MEM[9],~CHN_RD_MEM[9]}:PAR_DEFAULT)
| (start9?{bank9, row9, start_col9, num128_9, partial9, CHN_RD_MEM[9],~CHN_RD_MEM[9]}:PAR_DEFAULT)
`endif
`ifdef def_scanline_chn10
| (start10?{bank10, row10, start_col10, num128_10,CHN_RD_MEM[10],~CHN_RD_MEM[10]}:PAR_DEFAULT)
| (start10?{bank10, row10, start_col10, num128_10, partial10, CHN_RD_MEM[10],~CHN_RD_MEM[10]}:PAR_DEFAULT)
`endif
`ifdef def_scanline_chn11
| (start11?{bank11, row11, start_col11, num128_11,CHN_RD_MEM[11],~CHN_RD_MEM[11]}:PAR_DEFAULT)
| (start11?{bank11, row11, start_col11, num128_11, partial11, CHN_RD_MEM[11],~CHN_RD_MEM[11]}:PAR_DEFAULT)
`endif
`ifdef def_scanline_chn12
| (start12?{bank12, row12, start_col12, num128_12,CHN_RD_MEM[12],~CHN_RD_MEM[12]}:PAR_DEFAULT)
| (start12?{bank12, row12, start_col12, num128_12, partial12, CHN_RD_MEM[12],~CHN_RD_MEM[12]}:PAR_DEFAULT)
`endif
`ifdef def_scanline_chn13
| (start13?{bank13, row13, start_col13, num128_13,CHN_RD_MEM[13],~CHN_RD_MEM[13]}:PAR_DEFAULT)
| (start13?{bank13, row13, start_col13, num128_13, partial13, CHN_RD_MEM[13],~CHN_RD_MEM[13]}:PAR_DEFAULT)
`endif
`ifdef def_scanline_chn14
| (start14?{bank14, row14, start_col14, num128_14,CHN_RD_MEM[14],~CHN_RD_MEM[14]}:PAR_DEFAULT)
| (start14?{bank14, row14, start_col14, num128_14, partial14, CHN_RD_MEM[14],~CHN_RD_MEM[14]}:PAR_DEFAULT)
`endif
`ifdef def_scanline_chn15
| (start15?{bank15, row15, start_col15, num128_15,CHN_RD_MEM[15],~CHN_RD_MEM[15]}:PAR_DEFAULT)
| (start15?{bank15, row15, start_col15, num128_15, partial15, CHN_RD_MEM[15],~CHN_RD_MEM[15]}:PAR_DEFAULT)
`endif
;
always @ (posedge clk) begin
......@@ -309,6 +329,7 @@ module cmd_encod_linear_mux#(
row_r <= row_w;
start_col_r <= start_col_w;
num128_r <= num128_w;
partial_r <= partial_w;
end
start_rd_r <= start_rd_w;
start_wr_r <= start_wr_w;
......
memctrl/cmd_encod_linear_rd.v
View file @ e3d5b404
......@@ -47,6 +47,7 @@ module cmd_encod_linear_rd #(
input [ADDRESS_NUMBER-1:0] row_in, // memory row
input [COLADDR_NUMBER-4:0] start_col, // start memory column in 8-bursts
input [NUM_XFER_BITS-1:0] num128_in, // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
input skip_next_page_in, // do not reset external buffer (continue)
input start, // start generating commands
output reg [31:0] enc_cmd, // encoded commnad
output reg enc_wr, // write encoded command
......@@ -72,7 +73,7 @@ module cmd_encod_linear_rd #(
localparam REPEAT_ADDR=3;
localparam CMD_NOP= 0; // 3-bit normal memory RCW commands (positive logic)
localparam CMD_READ= 3;
localparam CMD_READ= 2;
localparam CMD_PRECHARGE=5;
localparam CMD_ACTIVATE= 4;
......@@ -80,7 +81,7 @@ module cmd_encod_linear_rd #(
reg [COLADDR_NUMBER-4:0] col; // start memory column (3 LSBs should be 0?) // VDT BUG: col is used as a function call parameter!
reg [2:0] bank; // memory bank;
reg [NUM_XFER_BITS-1:0] num128; // number of 128-bit words to transfer
reg skip_next_page;
reg gen_run;
reg gen_run_d;
reg [ROM_DEPTH-1:0] gen_addr; // will overrun as stop comes from ROM
......@@ -120,6 +121,8 @@ module cmd_encod_linear_rd #(
row<=row_in;
col <= start_col;
bank <= bank_in;
skip_next_page <= skip_next_page_in;
end
// ROM-based (registered output) encoded sequence
......@@ -146,7 +149,7 @@ module cmd_encod_linear_rd #(
else enc_wr <= gen_run || gen_run_d;
if (rst) enc_done <= 0;
else enc_done <= enc_wr || !gen_run_d;
else enc_done <= enc_wr && !gen_run_d;
if (rst) enc_cmd <= 0;
else if (rom_cmd==0) enc_cmd <= func_encode_skip ( // encode pause
......@@ -162,7 +165,7 @@ module cmd_encod_linear_rd #(
rom_r[ENC_DCI], // dci; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
rom_r[ENC_BUF_WR], // buf_wr; // connect to external buffer (but only if not paused)
1'b0, // buf_rd; // connect to external buffer (but only if not paused)
rom_r[ENC_BUF_PGNEXT]); // buf_rst; // connect to external buffer (but only if not paused)
rom_r[ENC_BUF_PGNEXT] && !skip_next_page); // buf_rst; // connect to external buffer (but only if not paused)
else enc_cmd <= func_encode_cmd ( // encode non-NOP command
rom_cmd[1]?
row:
......@@ -179,7 +182,7 @@ module cmd_encod_linear_rd #(
rom_r[ENC_BUF_WR], // buf_wr; // connect to external buffer (but only if not paused)
1'b0, // buf_rd; // connect to external buffer (but only if not paused)
rom_r[ENC_NOP], // nop; // add NOP after the current command, keep other data
rom_r[ENC_BUF_PGNEXT]); // buf_rst; // connect to external buffer (but only if not paused)
rom_r[ENC_BUF_PGNEXT] && !skip_next_page); // buf_rst; // connect to external buffer (but only if not paused)
end
......
memctrl/cmd_encod_linear_wr.v
View file @ e3d5b404
......@@ -38,6 +38,7 @@ module cmd_encod_linear_wr #(
input [ADDRESS_NUMBER-1:0] row_in, // memory row
input [COLADDR_NUMBER-4:0] start_col, // start memory column (3 LSBs should be 0?)
input [NUM_XFER_BITS-1:0] num128_in, // number of 128-bit words to transfer (8*16 bits) - full burst of 8 (0 - full 64)
input skip_next_page_in, // do not reset external buffer (continue)
input start, // start generating commands
output reg [31:0] enc_cmd, // encoded commnad
output reg enc_wr, // write encoded command
......@@ -73,6 +74,7 @@ module cmd_encod_linear_wr #(
reg [COLADDR_NUMBER-4:0] col; // start memory column (3 LSBs should be 0?) // VDT BUG: col is used as a function call parameter!
reg [2:0] bank; // memory bank;
reg [NUM_XFER_BITS:0] num128; // number of 128-bit words to transfer
reg skip_next_page;
reg gen_run;
reg gen_run_d;
......@@ -131,6 +133,7 @@ module cmd_encod_linear_wr #(
row<=row_in;
col <= start_col;
bank <= bank_in;
skip_next_page <= skip_next_page_in;
end
// ROM-based (registered output) encoded sequence
......@@ -177,7 +180,7 @@ module cmd_encod_linear_wr #(
1'b0, // dci; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
1'b0, // buf_wr; // connect to external buffer (but only if not paused)
rom_r[ENC_BUF_RD] && !cut_buf_rd, //buf_rd;// connect to external buffer (but only if not paused)
rom_r[ENC_BUF_PGNEXT]); // buf_rst; // connect to external buffer (but only if not paused)
rom_r[ENC_BUF_PGNEXT] && !skip_next_page); // buf_rst; // connect to external buffer (but only if not paused)
else enc_cmd <= func_encode_cmd ( // encode non-NOP command
rom_cmd[1]?
row:
......@@ -194,7 +197,7 @@ module cmd_encod_linear_wr #(
1'b0, // buf_wr; // connect to external buffer (but only if not paused)
rom_r[ENC_BUF_RD] && !cut_buf_rd, //buf_rd;// connect to external buffer (but only if not paused)
rom_r[ENC_NOP], // nop; // add NOP after the current command, keep other data
rom_r[ENC_BUF_PGNEXT]); // buf_rst; // connect to external buffer (but only if not paused)
rom_r[ENC_BUF_PGNEXT] && !skip_next_page); // buf_rst; // connect to external buffer (but only if not paused)
end
......
memctrl/cmd_encod_tiled_rd.v
View file @ e3d5b404
......@@ -242,7 +242,7 @@ module cmd_encod_tiled_rd #(
4'h7: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (1 << ENC_SEL);
4'h8: rom_r <= (ENC_CMD_READ << ENC_CMD_SHIFT) | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (1 << ENC_SEL);
4'h9: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (2 << ENC_PAUSE_SHIFT) | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (1 << ENC_SEL);
4'ha: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_DCI) | (1 << ENC_SEL) | (skip_next_page? 1'b0:(1 << ENC_BUF_PGNEXT));
4'ha: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_DCI) | (1 << ENC_SEL) | (1 << ENC_BUF_PGNEXT);
4'hb: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (3 << ENC_PAUSE_SHIFT) | (1 << ENC_DCI);
4'hc: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_PRE_DONE);
default:rom_r <= 0;
......@@ -272,7 +272,7 @@ module cmd_encod_tiled_rd #(
rom_r[ENC_DCI], // dci; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
rom_r[ENC_BUF_WR], // buf_wr; // connect to external buffer (but only if not paused)
1'b0, // buf_rd; // connect to external buffer (but only if not paused)
rom_r[ENC_BUF_PGNEXT]); // buf_rst; // connect to external buffer (but only if not paused)
rom_r[ENC_BUF_PGNEXT] && !skip_next_page); // buf_rst; // connect to external buffer (but only if not paused)
else enc_cmd <= func_encode_cmd ( // encode non-NOP command
rom_cmd[1]? // activate
row_col_bank[FULL_ADDR_NUMBER-1:COLADDR_NUMBER]: // top combined row,column,bank burst address (excludes 3 CA LSBs), valid/modified @pre_act
......@@ -294,7 +294,7 @@ module cmd_encod_tiled_rd #(
rom_r[ENC_BUF_WR], // buf_wr; // connect to external buffer (but only if not paused)
1'b0, // buf_rd; // connect to external buffer (but only if not paused)
rom_r[ENC_NOP], // nop; // add NOP after the current command, keep other data
rom_r[ENC_BUF_PGNEXT]); // buf_rst; // connect to external buffer (but only if not paused)
rom_r[ENC_BUF_PGNEXT] && !skip_next_page); // buf_rst; // connect to external buffer (but only if not paused)
end
// move to include?, Yes, after fixing problem with paths
......
memctrl/mcntrl393.v
View file @ e3d5b404
......@@ -463,6 +463,7 @@ module mcntrl393 #(
wire [ADDRESS_NUMBER-1:0] lin_rw_row; // memory row
wire [COLADDR_NUMBER-4:0] lin_rw_col; // start memory column in 8-bursts
wire [5:0] lin_rw_num128; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
wire lin_rw_xfer_partial; // do not increment page in the end, continue current
wire lin_rd_start; // start generating commands for read sequence
wire lin_wr_start; // start generating commands for write sequence
......@@ -470,6 +471,7 @@ module mcntrl393 #(
wire [ADDRESS_NUMBER-1:0] lin_rd_chn2_row; // memory row
wire [COLADDR_NUMBER-4:0] lin_rd_chn2_col; // start memory column in 8-bursts
wire [5:0] lin_rd_chn2_num128; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
wire lin_rd_chn2_partial; // do not increment page in the end, continue current
wire lin_rd_chn2_start; // start generating commands
// wire [1:0] xfer_page2; // "internal" buffer page
wire xfer_reset_page2_pos; // "internal" buffer page reset, @posedge mclk
......@@ -479,6 +481,7 @@ module mcntrl393 #(
wire [ADDRESS_NUMBER-1:0] lin_wr_chn3_row; // memory row
wire [COLADDR_NUMBER-4:0] lin_wr_chn3_col; // start memory column in 8-bursts
wire [5:0] lin_wr_chn3_num128; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
wire lin_wr_chn3_partial; // do not increment page in the end, continue current
wire lin_wr_chn3_start; // start generating commands
// wire [1:0] xfer_page3; // "internal" buffer page
wire xfer_reset_page3; // "internal" buffer page reset, @posedge mclk
......@@ -837,11 +840,11 @@ module mcntrl393 #(
.xfer_row (lin_rd_chn2_row), // output[14:0]
.xfer_col (lin_rd_chn2_col), // output[6:0]
.xfer_num128 (lin_rd_chn2_num128), // output[5:0]
.xfer_partial (lin_rd_chn2_partial), // output
.xfer_done (seq_done2), // input: sequence over
.xfer_reset_page (xfer_reset_page2_pos) // output
);
mcntrl_linear_rw #(
.ADDRESS_NUMBER (ADDRESS_NUMBER),
.COLADDR_NUMBER (COLADDR_NUMBER),
......@@ -881,6 +884,7 @@ module mcntrl393 #(
.xfer_row (lin_wr_chn3_row), // output[14:0]
.xfer_col (lin_wr_chn3_col), // output[6:0]
.xfer_num128 (lin_wr_chn3_num128), // output[5:0]
.xfer_partial (lin_wr_chn3_partial), // output
.xfer_done (seq_done3), // input : sequence over
// .xfer_page (xfer_page3) // output[1:0]
.xfer_reset_page (xfer_reset_page3) // output
......@@ -895,24 +899,26 @@ module mcntrl393 #(
.row2 (lin_rd_chn2_row), // input[14:0]
.start_col2 (lin_rd_chn2_col), // input[6:0]
.num128_2 (lin_rd_chn2_num128), // input[5:0]
.partial2 (lin_rd_chn2_partial), // input
.start2 (lin_rd_chn2_start), // input
.bank3 (lin_wr_chn3_bank), // input[2:0]
.row3 (lin_wr_chn3_row), // input[14:0]
.start_col3 (lin_wr_chn3_col), // input[6:0]
.num128_3 (lin_wr_chn3_num128), // input[5:0]
.partial3 (lin_wr_chn3_partial), // input
.start3 (lin_wr_chn3_start), // input
.bank (lin_rw_bank), // output[2:0]
.row (lin_rw_row), // output[14:0]
.start_col (lin_rw_col), // output[6:0]
.num128 (lin_rw_num128), // output[5:0]
.partial (lin_rw_xfer_partial), // output
.start_rd (lin_rd_start), // output
.start_wr (lin_wr_start) // output
);
/* Instance template for module cmd_encod_linear_rd */
cmd_encod_linear_rd #(
.ADDRESS_NUMBER (ADDRESS_NUMBER),
.COLADDR_NUMBER (COLADDR_NUMBER),
......@@ -926,13 +932,13 @@ module mcntrl393 #(
.row_in (lin_rw_row), // input[14:0]
.start_col (lin_rw_col), // input[6:0]
.num128_in (lin_rw_num128), // input[5:0]
.skip_next_page_in (lin_rw_xfer_partial), // input
.start (lin_rd_start), // input
.enc_cmd (seq_data2x), // output[31:0] reg
.enc_wr (seq_wr2x), // output reg
.enc_done (seq_set2x) // output reg
);
/* Instance template for module cmd_encod_linear_wr */
cmd_encod_linear_wr #(
.ADDRESS_NUMBER (ADDRESS_NUMBER),
.COLADDR_NUMBER (COLADDR_NUMBER),
......@@ -946,6 +952,7 @@ module mcntrl393 #(
.row_in (lin_rw_row), // input[14:0]
.start_col (lin_rw_col), // input[6:0]
.num128_in (lin_rw_num128), // input[5:0]
.skip_next_page_in (lin_rw_xfer_partial), // input
.start (lin_wr_start), // input
.enc_cmd (seq_data3x), // output[31:0] reg
.enc_wr (seq_wr3x), // output reg
......@@ -953,7 +960,6 @@ module mcntrl393 #(
);
/* Instance template for module mcntrl_ps_pio */
mcntrl_ps_pio #(
.MCNTRL_PS_ADDR (MCNTRL_PS_ADDR), //'h100),
.MCNTRL_PS_MASK (MCNTRL_PS_MASK), //'h3e0),
......
memctrl/mcntrl393_test01.v
View file @ e3d5b404
......@@ -118,9 +118,9 @@ module mcntrl393_test01#(
assign suspend_chn2 = suspend_chn2_r;
assign suspend_chn3 = suspend_chn3_r;
assign suspend_chn4 = suspend_chn4_r;
assign status_chn2={page_chn2,line_unfinished_chn2,1'b0, frame_busy_chn2};
assign status_chn3={page_chn3,line_unfinished_chn3,1'b0, frame_busy_chn3};
assign status_chn4={page_chn4,line_unfinished_chn4,1'b0, frame_busy_chn4};
assign status_chn2={page_chn2,line_unfinished_chn2,frame_busy_chn2, frame_busy_chn2};
assign status_chn3={page_chn3,line_unfinished_chn3,frame_busy_chn3, frame_busy_chn3};
assign status_chn4={page_chn4,line_unfinished_chn4,frame_busy_chn4, frame_busy_chn4};
always @ (posedge mclk) begin
frame_start_chn2_r <= set_chh2_mode && cmd_frame_start_w;
......
memctrl/mcntrl_linear_rw.v
View file @ e3d5b404
......@@ -71,6 +71,7 @@ module mcntrl_linear_rw #(
output [ADDRESS_NUMBER-1:0] xfer_row, // memory row
output [COLADDR_NUMBER-4:0] xfer_col, // start memory column in 8-bursts
output [NUM_XFER_BITS-1:0] xfer_num128, // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
output xfer_partial, // partial tile (first of 2) , sequencer will not generate page_next at the end of block
input xfer_done, // transfer to/from the buffer finished
output xfer_reset_page // reset internal buffer page to zero
// output [1:0] xfer_page // page number for transfer (goes to channel buffer memory-side adderss)
......@@ -96,14 +97,23 @@ module mcntrl_linear_rw #(
reg last_in_row;
reg [COLADDR_NUMBER-3:0] mem_page_left; // number of 8-bursts left in the pointed memory page
reg [NUM_XFER_BITS:0] lim_by_xfer; // number of bursts left limited by the longest transfer (currently 64)
// reg [MAX_TILE_WIDTH:0] lim_by_tile_width; // number of bursts left limited by the longest transfer (currently 64)
wire [COLADDR_NUMBER-3:0] remainder_in_xfer ;//remainder_tile_width; // number of bursts postponed to the next partial tile (because of the page crossing) MSB-sign
reg continued_xfer; //continued_tile; // this is a continued tile (caused by page crossing) - only once
reg [NUM_XFER_BITS-1:0] leftover; //[MAX_TILE_WIDTH-1:0] leftover_cols; // valid with continued_tile, number of columns left
reg [NUM_XFER_BITS:0] xfer_num128_r; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8
// reg [NUM_XFER_BITS-1:0] xfer_num128_m1_r; // number of 128-bit words to transfer minus 1 (8*16 bits) - full bursts of 8
wire pgm_param_w; // program one of the parameters, invalidate calculated results for PAR_MOD_LATENCY
reg [2:0] xfer_start_r;
reg [PAR_MOD_LATENCY-1:0] par_mod_r;
reg [PAR_MOD_LATENCY-1:0] recalc_r; // 1-hot CE for re-calculating registers
wire calc_valid; // calculated registers have valid values
wire chn_en; // enable requests by channle (continue ones in progress)
wire chn_rst; // resets command, including fifo;
reg chn_rst_d; // delayed by 1 cycle do detect turning off
reg xfer_reset_page_r;
reg [2:0] page_cntr;
......@@ -203,6 +213,8 @@ module mcntrl_linear_rw #(
assign calc_valid= par_mod_r[PAR_MOD_LATENCY-1]; // MSB, longest 0
// assign xfer_page= xfer_page_r;
assign xfer_reset_page = xfer_reset_page_r;
assign xfer_partial= xfer_limited_by_mem_page_r;
assign frame_done= frame_done_r;
assign pre_want= chn_en && busy_r && !want_r && !xfer_start_r[0] && calc_valid && !last_block && !suspend;
// assign pre_want= chn_en && busy_r && !want_r && !xfer_start_r[0] && calc_valid && !no_more_needed && !suspend;
......@@ -219,38 +231,64 @@ module mcntrl_linear_rw #(
assign chn_rst = ~mode_reg[0]; // resets command, including fifo;
assign cmd_extra_pages = mode_reg[3:2]; // external module needs more than 1 page
// assign cmd_wrmem = mode_reg[4];// 0: read from memory, 1:write to memory
assign status_data= {1'b0, busy_r}; // TODO: Add second bit?
assign status_data= {frame_done, busy_r}; // TODO: Add second bit?
assign pgm_param_w= cmd_we;
localparam [COLADDR_NUMBER-3-NUM_XFER_BITS-1:0] EXTRA_BITS=0;
assign remainder_in_xfer = {EXTRA_BITS, lim_by_xfer}-mem_page_left;
integer i;
// localparam EXTRA_BITS={ADDRESS_NUMBER-3-COLADDR_NUMBER-3{1'b0}};
// localparam EXTRA_BITS={COLADDR_NUMBER-3-NUM_XFER_BITS{1'b0}};
wire xfer_limited_by_mem_page;
reg xfer_limited_by_mem_page_r;
assign xfer_limited_by_mem_page= mem_page_left < {EXTRA_BITS,lim_by_xfer};
/// Recalcualting jusrt after starting request - preparing for the next one. Also happens after parameter change.
/// Should dpepend only on the parameters updated separately (curr_x, curr_y)
always @(posedge mclk) begin // TODO: Match latencies (is it needed?) Reduce consumption by CE?
if (recalc_r[0]) begin // cycle 1
frame_x <= curr_x + window_x0;
frame_y <= curr_y + window_y0;
next_y <= curr_y + 1;
row_left <= window_width - curr_x; // 14 bits - 13 bits
end
if (recalc_r[1]) begin // cycle 2
mem_page_left <= (1 << (COLADDR_NUMBER-3)) - frame_x[COLADDR_NUMBER-4:0];
lim_by_xfer <= (|row_left[FRAME_WIDTH_BITS:NUM_XFER_BITS])?(1<<NUM_XFER_BITS):row_left[NUM_XFER_BITS:0]; // 7 bits, max 'h40
xfer_num128_r<= (mem_page_left < {{COLADDR_NUMBER-3-NUM_XFER_BITS{1'b0}},lim_by_xfer})? mem_page_left[NUM_XFER_BITS:0]:lim_by_xfer[NUM_XFER_BITS:0];
// xfer_num128_m1_r <= xfer_num128_r[NUM_XFER_BITS-1:0]-1;
// xfer_num128_r<= (mem_page_left> {EXTRA_BITS, lim_by_xfer})? mem_page_left[NUM_XFER_BITS:0]:lim_by_xfer[NUM_XFER_BITS:0];
// VDT bug? next line gives a warning
// xfer_num128_r<= (mem_page_left> {{COLADDR_NUMBER-3-COLADDR_NUMBER-3{1'b0}},lim_by_xfer})?mem_page_left[NUM_XFER_BITS-1:0]:lim_by_xfer[NUM_XFER_BITS-1:0];
lim_by_xfer <= (|row_left[FRAME_WIDTH_BITS:NUM_XFER_BITS])?
(1<<NUM_XFER_BITS):
row_left[NUM_XFER_BITS:0]; // 7 bits, max 'h40
end
if (recalc_r[2]) begin // cycle 3
xfer_limited_by_mem_page_r <= xfer_limited_by_mem_page && !continued_xfer;
xfer_num128_r<= continued_xfer?
{EXTRA_BITS,leftover}:
(xfer_limited_by_mem_page?
mem_page_left[NUM_XFER_BITS:0]:
lim_by_xfer[NUM_XFER_BITS:0]);
leftover <= remainder_in_xfer[NUM_XFER_BITS-1:0];
// xfer_num128_r<= (mem_page_left < {{COLADDR_NUMBER-3-NUM_XFER_BITS{1'b0}},lim_by_xfer})?
// mem_page_left[NUM_XFER_BITS:0]:
// lim_by_xfer[NUM_XFER_BITS:0];
end
if (recalc_r[3]) begin // cycle 4
last_in_row <= last_in_row_w;
end
// registers to be absorbed in DSP block
frame_y8_r <= frame_y[FRAME_HEIGHT_BITS-1:3]; // lat=2
frame_full_width_r <= frame_full_width;
start_addr_r <= start_addr;
mul_rslt <= mul_rslt_w[MPY_WIDTH-1:0]; // frame_y8_r * frame_width_r; // 7 bits will be discarded lat=3;
line_start_addr <= start_addr_r+mul_rslt; // lat=4
// TODO: Verify MPY/register timing above
if (recalc_r[5]) begin // cycle 6
row_col_r <= line_start_addr+frame_x;
end
bank_reg[0] <= frame_y[2:0]; //TODO: is it needed - a pipeline for the bank? - remove!
for (i=0;i<2; i = i+1)
bank_reg[i+1] <= bank_reg[i];
end
wire start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r;
// now have row start address, bank and row_left ;
// calculate number to read (min of row_left, maximal xfer and what is left in the DDR3 page
always @(posedge rst or posedge mclk) begin
......@@ -258,6 +296,14 @@ module mcntrl_linear_rw #(
else if (pgm_param_w || xfer_start_r[0] || chn_rst) par_mod_r<=0;
else par_mod_r <= {par_mod_r[PAR_MOD_LATENCY-2:0], 1'b1};
if (rst) chn_rst_d <= 0;
else chn_rst_d <= chn_rst;
if (rst) recalc_r<=0;
else if (chn_rst) recalc_r<=0;
// else recalc_r <= {recalc_r[PAR_MOD_LATENCY-2:0], (xfer_grant & ~chn_rst) | pgm_param_w | (chn_rst_d & ~chn_rst)};
else recalc_r <= {recalc_r[PAR_MOD_LATENCY-2:0], (xfer_start_r[0] & ~chn_rst) | pgm_param_w | (chn_rst_d & ~chn_rst)};
if (rst) busy_r <= 0;
else if (chn_rst) busy_r <= 0;
else if (frame_start) busy_r <= 1;
......@@ -267,6 +313,11 @@ module mcntrl_linear_rw #(
else xfer_done_d <= xfer_done;
if (rst) continued_xfer <= 1'b0;
else if (chn_rst) continued_xfer <= 1'b0;
else if (frame_start) continued_xfer <= 1'b0;
else if (xfer_start_r[0]) continued_xfer <= xfer_limited_by_mem_page_r; // only set after actual start if it was partial, not after parameter change
if (rst) frame_done_r <= 0;
else if (chn_rst || frame_start) frame_done_r <= 0;
else if (busy_r && last_block && xfer_done_d && (pending_xfers==0)) frame_done_r <= 1;
......@@ -289,16 +340,11 @@ module mcntrl_linear_rw #(
if (rst) page_cntr <= 0;
else if (frame_start) page_cntr <= cmd_wrmem?0:4; // What about last pages (like if only 1 page is needed)? Early frame end?
else if ( xfer_start_r[0] && !next_page) page_cntr <= page_cntr - 1;
else if (!xfer_start_r[0] && next_page) page_cntr <= page_cntr + 1;
/*
if (rst) xfer_page_r <= 0;
// else if (chn_rst || frame_start) xfer_page_r <= 0; // TODO: Check if it is better to keep xfer_page_r on frame start?
else if (chn_rst ) xfer_page_r <= 0; // TODO: Check if it is better to reset xfer_page_r on frame start? to zero?
else if (xfer_done) xfer_page_r <= xfer_page_r+1;
*/
// xfer_reset_page_r <= chn_rst || frame_start ; // TODO: Check if it is better to reset page on frame start?
// else if ( xfer_start_r[0] && !next_page) page_cntr <= page_cntr - 1;
// else if (!xfer_start_r[0] && next_page) page_cntr <= page_cntr + 1;
else if ( start_not_partial && !next_page) page_cntr <= page_cntr - 1;
else if (!start_not_partial && next_page) page_cntr <= page_cntr + 1;
xfer_reset_page_r <= chn_rst; // || frame_start ; // TODO: Check if it is better to reset page on frame start?
......@@ -318,15 +364,12 @@ module mcntrl_linear_rw #(
if (rst) pending_xfers <= 0;
else if (chn_rst || !busy_r) pending_xfers <= 0;
else if ( xfer_start_r[0] && !xfer_done) pending_xfers <= pending_xfers + 1;
else if (!xfer_start_r[0] && xfer_done) pending_xfers <= pending_xfers - 1;
// else if ( xfer_start_r[0] && !xfer_done) pending_xfers <= pending_xfers + 1;
// else if (!xfer_start_r[0] && xfer_done) pending_xfers <= pending_xfers - 1;
else if ( start_not_partial && !xfer_done) pending_xfers <= pending_xfers + 1;
else if (!start_not_partial && xfer_done) pending_xfers <= pending_xfers - 1;
// else frame_done_r <= busy_r && no_more_needed && xfer_done && (pending_xfers==0);
// if (rst) no_more_needed <= 0;
// else if (chn_rst || !busy_r) no_more_needed <= 0;
// else if (xfer_start_r[0]) no_more_needed <= last_block;
//line_unfinished_r cmd_wrmem
if (rst) line_unfinished_r[0] <= 0; //{FRAME_HEIGHT_BITS{1'b0}};
......
memctrl/mcntrl_tiled_rw.v
View file @ e3d5b404
......@@ -24,7 +24,6 @@
module mcntrl_tiled_rw#(
parameter ADDRESS_NUMBER= 15,
parameter COLADDR_NUMBER= 10,
parameter NUM_XFER_BITS= 6, // number of bits to specify transfer length
parameter FRAME_WIDTH_BITS= 13, // Maximal frame width - 8-word (16 bytes) bursts
parameter FRAME_HEIGHT_BITS= 16, // Maximal frame height
parameter MAX_TILE_WIDTH= 6, // number of bits to specify maximal tile (width-1) (6 -> 64)
......@@ -106,7 +105,7 @@ module mcntrl_tiled_rw#(
reg [MAX_TILE_WIDTH:0] lim_by_tile_width; // number of bursts left limited by the longest transfer (currently 64)
wire [COLADDR_NUMBER-3:0] remainder_tile_width; // number of bursts postponed to the next partial tile (because of the page crossing) MSB-sign
reg continued_tile; // this is a continued tile (caused by page crossing) - only once
reg [MAX_TILE_WIDTH-1:0] leftower_cols; // valid with continued_tile, number of columns left
reg [MAX_TILE_WIDTH-1:0] leftover_cols; // valid with continued_tile, number of columns left
wire pgm_param_w; // program one of the parameters, invalidate calculated results for PAR_MOD_LATENCY
reg [2:0] xfer_start_r;
reg [PAR_MOD_LATENCY-1:0] par_mod_r;
......@@ -242,7 +241,7 @@ module mcntrl_tiled_rw#(
assign cmd_extra_pages = mode_reg[3:2]; // external module needs more than 1 page
assign keep_open= mode_reg[4]; // keep banks open (will be used only if number of rows <= 8
// assign cmd_wrmem = mode_reg[5];// 0: read from memory, 1:write to memory
assign status_data= {1'b0, busy_r}; // TODO: Add second bit?
assign status_data= {frame_done, busy_r};
assign pgm_param_w= cmd_we;
assign rowcol_inc= frame_full_width;
assign num_cols_m1_w= num_cols_r-1;
......@@ -281,9 +280,9 @@ module mcntrl_tiled_rw#(
if (recalc_r[2]) begin
xfer_limited_by_mem_page_r <= xfer_limited_by_mem_page && !continued_tile;
num_cols_r<= continued_tile?
{EXTRA_BITS,leftower_cols}:
{EXTRA_BITS,leftover_cols}:
(xfer_limited_by_mem_page? mem_page_left[MAX_TILE_WIDTH:0]:lim_by_tile_width[MAX_TILE_WIDTH:0]);
leftower_cols <= remainder_tile_width[MAX_TILE_WIDTH-1:0];
leftover_cols <= remainder_tile_width[MAX_TILE_WIDTH-1:0];
// remainder_tile_width <= {EXTRA_BITS,lim_by_tile_width}-mem_page_left;
end
// VDT bug? next line gives a warning
......@@ -346,8 +345,10 @@ wire start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r;
if (rst) page_cntr <= 0;
else if (frame_start) page_cntr <= cmd_wrmem?0:4;
else if ( xfer_start_r[0] && !next_page) page_cntr <= page_cntr + 1;
else if (!xfer_start_r[0] && next_page) page_cntr <= page_cntr - 1;
// else if ( xfer_start_r[0] && !next_page) page_cntr <= page_cntr + 1;
// else if (!xfer_start_r[0] && next_page) page_cntr <= page_cntr - 1;
else if ( start_not_partial && !next_page) page_cntr <= page_cntr + 1;
else if (!start_not_partial && next_page) page_cntr <= page_cntr - 1;
if (rst) xfer_page_rst_r <= 1;
else xfer_page_rst_r <= chn_rst || (MCNTRL_TILED_FRAME_PAGE_RESET ? frame_start:1'b0);
......
x393_testbench01.sav
View file @ e3d5b404
[*]
[*] GTKWave Analyzer v3.3.58 (w)1999-2014 BSI
[*] Sun Feb 15 05:48:02 2015
[*] Mon Feb 16 00:33:31 2015
[*]
[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench01-20150214223135659.lxt"
[dumpfile_mtime] "Sun Feb 15 05:39:28 2015"
[dumpfile_size] 371031838
[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench01-20150215172101663.lxt"
[dumpfile_mtime] "Mon Feb 16 00:28:22 2015"
[dumpfile_size] 383243105
[savefile] "/home/andrey/git/x393/x393_testbench01.sav"
[timestart] 154325000
[size] 1823 1173
[pos] 1937 0
*-17.698502 154934323 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[timestart] 143284250
[size] 1823 1180
[pos] 1940 0
*-13.698502 143321875 142911875 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] x393_testbench01.
[treeopen] x393_testbench01.x393_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.chn3_buf_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.
......@@ -28,10 +27,10 @@
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_test01_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.
[sst_width] 324
[signals_width] 310
[sst_width] 264
[signals_width] 383
[sst_expanded] 1
[sst_vpaned_height] 380
[sst_vpaned_height] 383
@800200
-top_simulation
@28
......@@ -1306,7 +1305,185 @@ x393_testbench01.x393_i.mcntrl393_test01_i.suspend_chn4[0]
x393_testbench01.x393_i.mcntrl393_test01_i.suspend_chn4_r[0]
@1401200
-mcntrl393_test01
@200
-
@800200
-linear_ch2
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.busy_r[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.calc_valid[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.chn_en[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.chn_rst[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.chn_rst_d[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.cmd_a[3:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.cmd_ad[7:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.cmd_data[31:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.cmd_extra_pages[1:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.cmd_stb[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.cmd_we[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.cmd_wrmem[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.continued_xfer[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.curr_x[12:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.curr_y[15:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.frame_done[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.frame_done_r[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.frame_full_width[13:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.frame_full_width_r[13:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.frame_start[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.frame_x[12:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.frame_y8_r[12:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.frame_y[15:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.i[31:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.last_block[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.last_in_row[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.last_in_row_w[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.last_row_w[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.leftover[5:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.lim_by_xfer[6:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.line_start_addr[21:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.line_unfinished[15:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.lsw13_zero[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.mclk[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.mem_page_left[7:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.mode_reg[3:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.msw13_zero[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.msw_zero[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.mul_rslt[21:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.mul_rslt_w[26:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.need_r[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.next_page[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.next_y[16:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.page_cntr[2:0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.par_mod_r[6:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.pending_xfers[1:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.pgm_param_w[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.pre_want[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.recalc_r[6:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.remainder_in_xfer[7:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.row_col_r[21:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.row_left[13:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.rst[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.set_frame_width_w[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.set_mode_w[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.set_start_addr_w[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.set_status_w[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.set_window_start_w[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.set_window_wh_w[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.set_window_x0y0_w[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.start_addr[21:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.start_addr_r[21:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.start_not_partial[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.start_x[12:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.start_y[15:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.status_ad[7:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.status_data[1:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.status_rq[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.status_start[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.suspend[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.want_r[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.window_height[16:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.window_width[13:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.window_x0[12:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.window_y0[15:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.xfer_bank[2:0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.xfer_col[6:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.xfer_done[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.xfer_done_d[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.xfer_grant[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.xfer_limited_by_mem_page[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.xfer_limited_by_mem_page_r[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.xfer_need[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.xfer_num128[5:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.xfer_num128_r[6:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.xfer_partial[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.xfer_reset_page[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.xfer_reset_page_r[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.xfer_row[14:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.xfer_start[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.xfer_start_r[2:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn2_i.xfer_want[0]
@1000200
-linear_ch2
@200
-
@800200
-read_block_scanline
@22
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rd_i.bank[2:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rd_i.bank_in[2:0]
@28
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rd_i.clk[0]
@22
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rd_i.col[6:0]
@28
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rd_i.done[0]
@22
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rd_i.enc_cmd[31:0]
@28
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rd_i.enc_done[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rd_i.enc_wr[0]
@23
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rd_i.full_cmd[2:0]
@22
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rd_i.gen_addr[3:0]
@28
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rd_i.gen_run[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rd_i.gen_run_d[0]
@22
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rd_i.num128[5:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rd_i.num128_in[5:0]
@28
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rd_i.pre_done[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rd_i.rom_cmd[1:0]
@22
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rd_i.rom_r[9:0]
@28
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rd_i.rom_skip[1:0]
@22
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rd_i.row[14:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rd_i.row_in[14:0]
@28
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rd_i.rst[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rd_i.skip_next_page[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rd_i.skip_next_page_in[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rd_i.start[0]
@22
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rd_i.start_col[6:0]
@1000200
-read_block_scanline
@c00200
-linear_ch3
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.busy_r[0]
......@@ -1322,6 +1499,7 @@ x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.cmd_extra_pages[1:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.cmd_stb[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.cmd_we[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.cmd_wrmem[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.continued_xfer[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.curr_x[12:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.curr_y[15:0]
......@@ -1344,6 +1522,7 @@ x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.last_in_row[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.last_in_row_w[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.last_row_w[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.leftover[5:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.lim_by_xfer[6:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.line_start_addr[21:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.line_unfinished[15:0]
......@@ -1378,6 +1557,18 @@ x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.pending_xfers[1:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.pgm_param_w[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.pre_want[0]
@800022
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.recalc_r[6:0]
@28
(0)x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.recalc_r[6:0]
(1)x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.recalc_r[6:0]
(2)x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.recalc_r[6:0]
(3)x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.recalc_r[6:0]
(4)x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.recalc_r[6:0]
(5)x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.recalc_r[6:0]
(6)x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.recalc_r[6:0]
@1001200
-group_end
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.row_col_r[21:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.row_left[13:0]
......@@ -1421,13 +1612,24 @@ x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.sequencer_run_busy[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.pre_run_seq_w[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.cmd_seq_run[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.pre_run_chn_w[0]
@29
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.sel_refresh_w[0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.refresh_grant[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.grant_r[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.refresh_want[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.refresh_need[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.frame_x[12:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.frame_y[15:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.frame_y8_r[12:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.next_y[16:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.curr_x[12:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.curr_y[15:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.row_col_r[21:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.last_in_row_w[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.last_in_row[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.row_left[13:0]
@200
-
@1000200
......@@ -1439,11 +1641,14 @@ x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.xfer_col[6:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.xfer_done[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.xfer_done_d[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.xfer_grant[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.xfer_limited_by_mem_page[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.xfer_limited_by_mem_page_r[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.xfer_need[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.xfer_num128[5:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.xfer_num128_r[6:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.xfer_partial[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.xfer_reset_page[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.xfer_reset_page_r[0]
@22
......@@ -1452,9 +1657,9 @@ x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.xfer_row[14:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.xfer_start[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.xfer_start_r[2:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.xfer_want[0]
@1000200
@1401200
-linear_ch3
@c00200
@800200
-cmd1_buf
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_sel[0]
......@@ -1488,7 +1693,7 @@ x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd1_buf_i.wc
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd1_buf_i.we[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd1_buf_i.web[3:0]
@1401200
@1000200
-cmd1_buf
@200
-
......@@ -1554,7 +1759,7 @@ x393_testbench01.x393_i.mcntrl393_i.chn3_buf_i.ram_1kx32w_512x64r_i.waddr[9:0]
x393_testbench01.x393_i.mcntrl393_i.chn3_buf_i.ram_1kx32w_512x64r_i.we[0]
@1401200
-ch3_buf
@c00200
@800200
-write_block_scanline_chn
@22
x393_testbench01.write_block_scanline_chn.chn[31:0]
......@@ -1571,7 +1776,7 @@ x393_testbench01.write_block_incremtal.j[31:0]
x393_testbench01.write_block_incremtal.num_words[31:0]
x393_testbench01.write_block_incremtal.start_value[31:0]
x393_testbench01.write_block_incremtal.start_word_address[29:0]
@1401200
@1000200
-write_block_scanline_chn
@200
-
......@@ -2202,7 +2407,7 @@ x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.want_rq0[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.want_rq1[0]
@1401200
-PS_PIO
@c00200
@800200
-memcntrl16_0
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ext_buf_rchn_late[3:0]
......@@ -2311,7 +2516,6 @@ x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd0_buf_i.we
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ext_buf_rrefresh[0]
@1000200
-cmd0_buf
@1401200
-memcntrl16_0
@c00200
-max_0001
......
x393_testbench01.tf
View file @ e3d5b404
......@@ -23,12 +23,19 @@
`define DEBUG_FIFO 1
`undef WAIT_MRS
`define SET_PER_PIN_DEALYS 1 // set individual (including per-DQ pin delays)
`define PS_PIO_WAIT_COMPLETE 0 // wait until PS PIO module finished transaction before starting a new one
// Disabled already passed test to speedup simulation
//`define TEST_WRITE_LEVELLING 1
//`define TEST_READ_PATTERN 1
//`define TEST_WRITE_BLOCK 1
//`define TEST_READ_BLOCK 1
`define TEST_SCANLINE_WRITE 1
`define PS_PIO_WAIT_COMPLETE 0 // wait until PS PIO module finished transaction before starting a new one
`define TEST_SCANLINE_WRITE_WAIT 1 // wait TEST_SCANLINE_WRITE finished (frame_done)
`define TEST_SCANLINE_READ 1
module x393_testbench01 #(
`include "includes/x393_parameters.vh"
......@@ -191,7 +198,7 @@ module x393_testbench01 #(
localparam SCANLINE_WINDOW_W= 'h000b; // 176: 13-bit window width (0->'h4000)
localparam SCANLINE_WINDOW_H= 'h0009; // 9: 16-bit frame height (0->'h10000)
// localparam SCANLINE_X0Y0= 'h00050003; // X0=3*16=48, Y0=5: // low word - 13-bit window left, high word - 16-bit window top
localparam SCANLINE_X0= 'h0003; // X0=3*16=48 - 13-bit window left
localparam SCANLINE_X0= 'h7c; // 'h0003; // X0=3*16=48 - 13-bit window left
localparam SCANLINE_Y0= 'h0005; // Y0=5: 16-bit window top
// localparam SCANLINE_STARTXY= 'h0; // low word - 13-bit start X (relative to window), high word - 16-bit start y (normally 0)
localparam SCANLINE_STARTX= 'h0; // 13-bit start X (relative to window), high word (normally 0)
......@@ -364,7 +371,7 @@ always #(CLKIN_PERIOD/2) CLK <= ~CLK;
write_contol_register(MCNTRL_SCANLINE_CHN3_ADDR + MCNTRL_SCANLINE_WINDOW_STARTXY, SCANLINE_STARTX+(SCANLINE_STARTY<<16));
write_contol_register(MCNTRL_SCANLINE_CHN3_ADDR + MCNTRL_SCANLINE_MODE, {28'b0,SCANLINE_EXTRA_PAGES,2'b11});// set mode register: {extra_pages[1:0],enable,!reset}
configure_channel_priority(3,0); // lowest priority channel 1
configure_channel_priority(3,0); // lowest priority channel 3
enable_memcntrl_channels(16'h000b); // channels 0,1,3 are enabled
// localparam TEST01_START_FRAME= 1;
// localparam TEST01_NEXT_PAGE= 2;
......@@ -374,17 +381,8 @@ always #(CLKIN_PERIOD/2) CLK <= ~CLK;
for (ii=0;ii<TEST_INITIAL_BURST;ii=ii+1) begin
write_block_scanline_chn(3, (ii & 3), SCANLINE_WINDOW_W << 2, SCANLINE_X0,SCANLINE_Y0+ii); // now assumes that width is <= than maximal xfer
end
// write_block_scanline_chn(3,0, SCANLINE_WINDOW_W << 2, SCANLINE_X0,SCANLINE_Y0+0); // now assumes that width is <= than maximal xfer
// write_block_scanline_chn(3,1, SCANLINE_WINDOW_W << 2, SCANLINE_X0,SCANLINE_Y0+1);
// write_block_scanline_chn(3,2, SCANLINE_WINDOW_W << 2, SCANLINE_X0,SCANLINE_Y0+2);
// write_block_scanline_chn(3,3, SCANLINE_WINDOW_W << 2, SCANLINE_X0,SCANLINE_Y0+3);
// write_contol_register(MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN3_MODE, TEST01_NEXT_PAGE);
// write_contol_register(MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN3_MODE, TEST01_NEXT_PAGE);
// write_contol_register(MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN3_MODE, TEST01_NEXT_PAGE);
// write_contol_register(MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN3_MODE, TEST01_NEXT_PAGE);
// now need to repeat - test ready, then next page
for (ii=0;ii<SCANLINE_WINDOW_H;ii = ii+1) begin
for (ii=0;ii<SCANLINE_WINDOW_H;ii = ii+1) begin // here assuming 1 page per line
if (ii >= TEST_INITIAL_BURST) begin // wait page ready and fill page after first 4 are filled
wait_status_condition (
MCNTRL_TEST01_STATUS_REG_CHN3_ADDR,
......@@ -397,8 +395,42 @@ always #(CLKIN_PERIOD/2) CLK <= ~CLK;
end
write_contol_register(MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN3_MODE, TEST01_NEXT_PAGE);
end
`ifdef TEST_SCANLINE_WRITE_WAIT
wait_status_condition ( // may also be read directly from the same bit of mctrl_linear_rw (address=5) status
MCNTRL_TEST01_STATUS_REG_CHN3_ADDR,
MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN3_STATUS_CNTRL,
DEFAULT_STATUS_MODE,
2 << STATUS_2LSB_SHFT, // bit 24 - busy, bit 25 - frame done
2 << STATUS_2LSB_SHFT, // mask for the 4-bit page number
0); // equal to
`endif
`endif
`ifdef TEST_SCANLINE_READ
// program to the
write_contol_register(MCNTRL_SCANLINE_CHN2_ADDR + MCNTRL_SCANLINE_STARTADDR, FRAME_START_ADDRESS); // RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0)
write_contol_register(MCNTRL_SCANLINE_CHN2_ADDR + MCNTRL_SCANLINE_FRAME_FULL_WIDTH, FRAME_FULL_WIDTH);
write_contol_register(MCNTRL_SCANLINE_CHN2_ADDR + MCNTRL_SCANLINE_WINDOW_WH, SCANLINE_WINDOW_W + (SCANLINE_WINDOW_H<<16));
write_contol_register(MCNTRL_SCANLINE_CHN2_ADDR + MCNTRL_SCANLINE_WINDOW_X0Y0, SCANLINE_X0+ (SCANLINE_Y0<<16));
write_contol_register(MCNTRL_SCANLINE_CHN2_ADDR + MCNTRL_SCANLINE_WINDOW_STARTXY, SCANLINE_STARTX+(SCANLINE_STARTY<<16));
write_contol_register(MCNTRL_SCANLINE_CHN2_ADDR + MCNTRL_SCANLINE_MODE, {28'b0,SCANLINE_EXTRA_PAGES,2'b11});// set mode register: {extra_pages[1:0],enable,!reset}
configure_channel_priority(2,0); // lowest priority channel 2
enable_memcntrl_channels(16'h000f); // channels 0,1,2,3 are enabled
write_contol_register(MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN2_MODE, TEST01_START_FRAME);
for (ii=0;ii<SCANLINE_WINDOW_H;ii = ii+1) begin // here assuming 1 page per line
wait_status_condition (
MCNTRL_TEST01_STATUS_REG_CHN2_ADDR,
MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN2_STATUS_CNTRL,
DEFAULT_STATUS_MODE,
(ii) << 16, // -TEST_INITIAL_BURST)<<16, // 4-bit page number
'hf << 16, // mask for the 4-bit page number
1); // not equal to
// read block (if needed), for now just sikip
write_contol_register(MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN2_MODE, TEST01_NEXT_PAGE);
end
`endif
#40000;
$finish;
end
......
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