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Commit e2153595 authored by Andrey Filippov's avatar Andrey Filippov
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working on dtt

parent 6a91d1aa
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Showing with 382 additions and 89 deletions
dct_tests_01.sav
View file @ e2153595
[*]
[*] GTKWave Analyzer v3.3.78 (w)1999-2016 BSI
[*] Tue Dec 13 19:43:18 2016
[*] Tue Dec 5 02:26:14 2017
[*]
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[dumpfile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/simulation/dct_tests_01-20171130150416223.fst"
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[dumpfile_size] 105262
[savefile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/dct_tests_01.sav"
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[treeopen] dct_tests_01.
[treeopen] dct_tests_01.dct_iv8_1d_i.
[treeopen] dct_tests_01.dct_iv8_1d_i.dsp_ma_preadd_c_1_i.
......@@ -19,11 +19,14 @@
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[color] 2
dct_tests_01.start
dct_tests_01.start2
dct_tests_01.y_dv
dct_tests_01.y_pre_we
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......@@ -91,7 +95,8 @@ dct_tests_01.phase_y[3:0]
dct_tests_01.y_dct[23:0]
dct_tests_01.y_out[23:0]
dct_tests_01.dct_iv8_1d_i.y_index[2:0]
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......@@ -203,7 +208,7 @@ dct_tests_01.dct_iv8_1d_i.dsp_post_add_1
dct_tests_01.dct_iv8_1d_i.dsp_accum_1
@22
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dct_tests_01.dct_iv8_1d_i.dsp_ma_preadd_c_1_i.ain[24:0]
......@@ -235,7 +240,7 @@ dct_tests_01.dct_iv8_1d_i.dsp_ma_preadd_c_1_i.p_reg_cond[47:0]
dct_tests_01.dct_iv8_1d_i.dsp_ma_preadd_c_1_i.p_reg[47:0]
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......@@ -274,7 +279,7 @@ dct_tests_01.dct_iv8_1d_i.dsp_p_2[47:0]
dct_tests_01.dct_iv8_1d_i.phase_cnt[3:0]
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......@@ -286,7 +291,7 @@ dct_tests_01.dct_iv8_1d_i.dsp_ma_preadd_c_2_i.ad_reg[24:0]
dct_tests_01.dct_iv8_1d_i.dsp_ma_preadd_c_2_i.p_reg[47:0]
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dct_tests_01.dct_iv8_1d_i.en
......@@ -393,10 +398,53 @@ dct_tests_01.d_out_2d[23:0]
dct_tests_01.dv_2dr
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......
dct_tests_02.sav 0 → 100644
View file @ e2153595
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dsp/dtt_iv8_1d.v
View file @ e2153595
......@@ -66,7 +66,7 @@ module dtt_iv8_1d#(
input clk,
input rst,
input en,
input dst_in, // 0 - dct, 1 - dst. @ start/restart
input dst_in, // 0 - dct, 1 - dst. @ start only, no restart
input [WIDTH -1:0] d_in, // X2-X7-X3-X4-X5-X6-X0-X1-*-X3-X5-X4-*-X6-X7-*
input start, // one cycle before first X6 input
output [OUT_WIDTH -1:0] dout,
......@@ -75,6 +75,7 @@ module dtt_iv8_1d#(
// In DST mode the sequence is the same (to be inverted), but
// Y0, Y2, Y4 and Y6 are negated
output en_out, // valid at the same time slot as pre2_start_out (goes active with pre2_start_out), 2 ahead of data
output dst_out, // valid with en_out
output reg [2:0] y_index // for simulation - valid with dout - index of the data output
);
......@@ -140,7 +141,10 @@ module dtt_iv8_1d#(
reg en_out_r2;
reg dst_pre; // keeps dst_in value for second stage
reg dst_out; // controls source of dsp_neg_m_2 mux
reg dst_2; // controls source of dsp_neg_m_2 mux
reg dst_out_r; // // 2 ahead of data out
assign dst_out = dst_out_r;
assign en_out = en_out_r;
......@@ -162,14 +166,14 @@ module dtt_iv8_1d#(
en_out_r2 <= en_out_r;
if (en_out_r2) begin
case (phase_cnt[3:1])
3'h0: y_index <= 0;
3'h1: y_index <= 7;
3'h2: y_index <= 4;
3'h3: y_index <= 3;
3'h4: y_index <= 1;
3'h5: y_index <= 6;
3'h6: y_index <= 2;
3'h7: y_index <= 5;
3'h0: y_index <= dst_out_r ? 7 : 0;
3'h1: y_index <= dst_out_r ? 0 : 7;
3'h2: y_index <= dst_out_r ? 3 : 4;
3'h3: y_index <= dst_out_r ? 4 : 3;
3'h4: y_index <= dst_out_r ? 6 : 1;
3'h5: y_index <= dst_out_r ? 1 : 6;
3'h6: y_index <= dst_out_r ? 5 : 2;
3'h7: y_index <= dst_out_r ? 2 : 5;
endcase
end else begin
y_index <= 'bx;
......@@ -193,11 +197,14 @@ module dtt_iv8_1d#(
else if (start || restart) run_in <= 1;
else if (phase_cnt==15) run_in <= 0;
if (start || restart) dst_pre <= dst_in;
// if (start || restart) dst_pre <= dst_in;
if (start) dst_pre <= dst_in;
if (phase_cnt == 12) dst_2 <= dst_pre;
if (phase_cnt == 14) dst_out_r <= dst_2;
if (phase_cnt == 12) dst_out <= dst_pre;
dsp_neg_m_2 <= dst_out ? dsp_neg_m_2_dst : dsp_neg_m_2_dct;
dsp_neg_m_2 <= dst_2 ? dsp_neg_m_2_dst : dsp_neg_m_2_dct;
if (rst) run_out <= 0;
else if (phase_cnt == 13) run_out <= run_in;
......@@ -280,7 +287,7 @@ module dtt_iv8_1d#(
dsp_selb_2 <= p00 | p03 | p05 | p06 | p08 | p11 | p13 | p14 ;
// dsp_neg_m_2 <= p03 | p06 | p12 | p15 ;
dsp_neg_m_2_dct <= p02 | p05 | p11 | p14 ;
dsp_neg_m_2_dst <= p00 | p01 | p02 | p05 | p06 | p07 | p08 | p09 | p11 | p14 ;
dsp_neg_m_2_dst <= p00 | p01 | p02 | p05 | p06 | p07 | p08 | p09 | p11 | p12 | p13 | p14 ;
dsp_accum_2 <= p00 | p02 | p04 | p06 | p08 | p10 | p12 | p14 ;
end
......
dsp/dtt_iv_8x8.v
View file @ e2153595
......@@ -70,6 +70,7 @@ module dtt_iv_8x8#(
output reg pre_first_out, //!< 1 cycle ahead of the first output in a 64 block
output reg dv, //!< data output valid. WAS: Will go high on the 94-th cycle after the start
output signed [OUT_WIDTH-1:0] d_out, //!< output data
output reg [1:0] mode_out, //!< copy of mode input, valid @ pre_first_out
output reg pre_busy); //!< start should come each 64-th cycle (next after pre_last_in), and not after pre_busy)
// 1. Two 16xINPUT_WIDTH memories to feed two of the 'horizontal' 1-dct - they should provide outputs shifted by 1 clock
......@@ -128,7 +129,7 @@ module dtt_iv_8x8#(
reg [6:0] transpose_rcntr; // transpose read memory counter, [6] == 1 when the last page is being finished
reg [2:0] transpose_out_run;
wire transpose_out_start = transpose_in_run && (transpose_cntr[6:0] == 7'h34); // 7'h33 is actual minimum
wire transpose_out_start = transpose_in_run && (transpose_cntr[6:0] == 7'h35); // 7'h33 is actual minimum
reg [1:0] transpose_r_page;
reg signed [TRANSPOSE_WIDTH-1:0] transpose_reg; // internal BRAM register
......@@ -200,20 +201,39 @@ module dtt_iv_8x8#(
reg signed [OUT_WIDTH-1:0] dctv_out_reg_2;
reg [2:0] dctv_out_debug_reg_2; // SuppressThisWarning VEditor - simulation only
reg [1:0] mode_in; //
reg [1:0] mode_v; //
// reg [1:0] mode_in; //
// reg [1:0] mode_in; //
// reg modev_in; // delayed mode_in[0]
reg [1:0] mode_h; // registered at start, [1] used for hor (first) pass
reg [1:0] mode_h_late; // mode_h registered @ pre_last_in
// reg [1:0] mode_hv; // passing vertical mode wit the same dealy as horizontal
reg [1:0] mode_v; // mode_h_late registered @ transpose_out_start ([0]used for vert pass)
// mode_out mode_v registered @ pre_first_out_w
// wire [1:0] pre2_start_outh; // 2 cycles before horizontal output data is valid
// wire [1:0] pre2_start_outv; // 2 cycles before vertical output data is valid
wire [1:0] pre2_dsth; // 2 cycles before horizontal output data is valid, 0 dct, 1 - dst
wire [1:0] pre2_dstv; // 2 cycles before vertical output data is valid, 0 dct, 1 - dst
reg pre_dsth; // 1 cycles before horizontal output data is valid, 0 dct, 1 - dst
reg pre_dstv; // 1 cycles before vertical output data is valid, 0 dct, 1 - dst
wire pre_first_out_w = dctv_out_ra_1[6:0] == 1;
wire [OUT_WIDTH-1:0] debug_dctv_dout = dctv_out_sel? dctv_dout1: dctv_dout0;
assign d_out = dctv_out_reg_2;
assign pre_last_in = pre_last_in_r;
always @ (posedge clk) begin
if (rst) x_run <= 0;
else if (start) x_run <= 1;
else if (&x_wa[5:0]) x_run <= 0;
if (start) mode_in <= mode;
if (start) mode_h <= mode;
if (pre_last_in) mode_h_late <= mode_h;
if (transpose_out_start) mode_v <= mode_h_late;
if (pre_first_out_w) mode_out <= mode_v;
if (!x_run) x_wa <= 0;
else x_wa <= x_wa + 1;
......@@ -250,6 +270,9 @@ module dtt_iv_8x8#(
dcth_start_0_r <= dcth_start_0_w;
dcth_start_1_r <= dcth_start_1_w;
pre_dsth <= dcth_en_out0 ? pre2_dsth[0] : pre2_dsth[1];
if (rst) transpose_in_run <= 0;
else if (transpose_start) transpose_in_run <= 1;
else if (transpose_cntr [6:0] == 7'h46) transpose_in_run <= 0; // check actual?
......@@ -261,22 +284,22 @@ module dtt_iv_8x8#(
else if (transpose_in_run && (&transpose_cntr[5:0])) transpose_w_page <= transpose_w_page + 1;
case (transpose_cntr[3:0])
4'h0: transpose_wa_low <= 0;
4'h1: transpose_wa_low <= 1;
4'h2: transpose_wa_low <= 7;
4'h3: transpose_wa_low <= 6;
4'h4: transpose_wa_low <= 4;
4'h5: transpose_wa_low <= 2;
4'h6: transpose_wa_low <= 3;
4'h7: transpose_wa_low <= 5;
4'h8: transpose_wa_low <= 1;
4'h9: transpose_wa_low <= 0;
4'ha: transpose_wa_low <= 6;
4'hb: transpose_wa_low <= 7;
4'hc: transpose_wa_low <= 2;
4'hd: transpose_wa_low <= 4;
4'he: transpose_wa_low <= 5;
4'hf: transpose_wa_low <= 3;
4'h0: transpose_wa_low <= 0 ^ {3{pre_dsth}};
4'h1: transpose_wa_low <= 1 ^ {3{pre_dsth}};
4'h2: transpose_wa_low <= 7 ^ {3{pre_dsth}};
4'h3: transpose_wa_low <= 6 ^ {3{pre_dsth}};
4'h4: transpose_wa_low <= 4 ^ {3{pre_dsth}};
4'h5: transpose_wa_low <= 2 ^ {3{pre_dsth}};
4'h6: transpose_wa_low <= 3 ^ {3{pre_dsth}};
4'h7: transpose_wa_low <= 5 ^ {3{pre_dsth}};
4'h8: transpose_wa_low <= 1 ^ {3{pre_dsth}};
4'h9: transpose_wa_low <= 0 ^ {3{pre_dsth}};
4'ha: transpose_wa_low <= 6 ^ {3{pre_dsth}};
4'hb: transpose_wa_low <= 7 ^ {3{pre_dsth}};
4'hc: transpose_wa_low <= 2 ^ {3{pre_dsth}};
4'hd: transpose_wa_low <= 4 ^ {3{pre_dsth}};
4'he: transpose_wa_low <= 5 ^ {3{pre_dsth}};
4'hf: transpose_wa_low <= 3 ^ {3{pre_dsth}};
endcase
transpose_wa_high <= {transpose_w_page, transpose_cntr[5:4], transpose_cntr[0]} - {transpose_wa_decr,1'b0};
transpose_we <= {transpose_we[0],dcth_en_out0 | dcth_en_out1};
......@@ -321,6 +344,8 @@ module dtt_iv_8x8#(
else if (dctv_start_1_w) dctv_en1 <= 1;
else if (dctv_phin[6]) dctv_en1 <= 0; // maybe get rid of this signal and send satrt for each 8?
pre_dstv <= dctv_en_out0 ? pre2_dstv[0] : pre2_dstv[1];
if (t_we0 || t_we1) $display("%d %d",transpose_rcntr-2, transpose_out) ;
//write vertical dct input reorder memory
......@@ -337,9 +362,6 @@ module dtt_iv_8x8#(
dctv_start_0_r <= dctv_start_0_w;
dctv_start_1_r <= dctv_start_1_w;
if (dctv_start_0_w) mode_v[0] <= mode_in[0];
if (dctv_start_1_w) mode_v[1] <= mode_in[0];
dctv_debug_xin0 <= t_debug_ram0[t_ra0[2:0]];
dctv_debug_xin1 <= t_debug_ram1[t_ra1[2:0]];
......@@ -356,22 +378,22 @@ module dtt_iv_8x8#(
dctv_out_sel <= dctv_out_cntr[0];
case (dctv_out_cntr[3:0])
4'h0: dctv_out_wa_1 <= 0;
4'h1: dctv_out_wa_1 <= 9;
4'h2: dctv_out_wa_1 <= 7;
4'h3: dctv_out_wa_1 <= 14;
4'h4: dctv_out_wa_1 <= 4;
4'h5: dctv_out_wa_1 <= 10;
4'h6: dctv_out_wa_1 <= 3;
4'h7: dctv_out_wa_1 <= 13;
4'h8: dctv_out_wa_1 <= 1;
4'h9: dctv_out_wa_1 <= 8;
4'ha: dctv_out_wa_1 <= 6;
4'hb: dctv_out_wa_1 <= 15;
4'hc: dctv_out_wa_1 <= 2;
4'hd: dctv_out_wa_1 <= 12;
4'he: dctv_out_wa_1 <= 5;
4'hf: dctv_out_wa_1 <= 11;
4'h0: dctv_out_wa_1 <= 0 ^ {3{pre_dstv}};
4'h1: dctv_out_wa_1 <= 9 ^ {3{pre_dstv}};
4'h2: dctv_out_wa_1 <= 7 ^ {3{pre_dstv}};
4'h3: dctv_out_wa_1 <= 14 ^ {3{pre_dstv}};
4'h4: dctv_out_wa_1 <= 4 ^ {3{pre_dstv}};
4'h5: dctv_out_wa_1 <= 10 ^ {3{pre_dstv}};
4'h6: dctv_out_wa_1 <= 3 ^ {3{pre_dstv}};
4'h7: dctv_out_wa_1 <= 13 ^ {3{pre_dstv}};
4'h8: dctv_out_wa_1 <= 1 ^ {3{pre_dstv}};
4'h9: dctv_out_wa_1 <= 8 ^ {3{pre_dstv}};
4'ha: dctv_out_wa_1 <= 6 ^ {3{pre_dstv}};
4'hb: dctv_out_wa_1 <= 15 ^ {3{pre_dstv}};
4'hc: dctv_out_wa_1 <= 2 ^ {3{pre_dstv}};
4'hd: dctv_out_wa_1 <= 12 ^ {3{pre_dstv}};
4'he: dctv_out_wa_1 <= 5 ^ {3{pre_dstv}};
4'hf: dctv_out_wa_1 <= 11 ^ {3{pre_dstv}};
endcase
// write first stage of output reordering
......@@ -393,7 +415,7 @@ module dtt_iv_8x8#(
dctv_out_we_2 <= dctv_out_run_1;
dctv_out_wa_2 <= dctv_out_ra_1_w[1:0];
// write first stage of output reordering
// write last stage of output reordering
if (dctv_out_we_2) dctv_out_ram_2[dctv_out_wa_2] <= dctv_out_reg_1;
if (dctv_out_we_2) dctv_out_debug_ram_2[dctv_out_wa_2] <= dctv_out_debug_reg_1;
......@@ -408,7 +430,7 @@ module dtt_iv_8x8#(
if (dctv_out_run_2) dctv_out_reg_2 <= dctv_out_ram_2[dctv_out_ra_2[1:0]];
if (dctv_out_run_2) dctv_out_debug_reg_2 <= dctv_out_debug_ram_2[dctv_out_ra_2[1:0]];
pre_first_out <= dctv_out_ra_1[6:0] == 2;
pre_first_out <= pre_first_out_w;
dv <= dctv_out_run_2;
end
......@@ -516,12 +538,13 @@ module dtt_iv_8x8#(
.clk (clk), // input
.rst (rst), // input
.en (dcth_en0), // input
.dst_in (mode_in[1]) , // 0 - dct, 1 - dst. @ start/restart
.dst_in (mode_h[1]) , // 0 - dct, 1 - dst. @ start/restart
.d_in (dcth_xin0), // input[23:0]
.start (dcth_start_0_r), // input
.dout (dcth_dout0), // output[23:0]
.pre2_start_out (), // output reg
.pre2_start_out (), // pre2_start_outh[0]), // output reg
.en_out (dcth_en_out0), // output reg
.dst_out (pre2_dsth[0]), // output valid with en_out
.y_index (dcth_yindex0) // output[2:0] reg
);
......@@ -549,12 +572,13 @@ module dtt_iv_8x8#(
.clk (clk), // input
.rst (rst), // input
.en (dcth_en1), // input
.dst_in (mode_in[1]) , // 0 - dct, 1 - dst. @ start/restart
.dst_in (mode_h[1]), // 0 - dct, 1 - dst. @ start/restart
.d_in (dcth_xin1), // input[23:0]
.start (dcth_start_1_r), // input
.dout (dcth_dout1), // output[23:0]
.pre2_start_out (), // output reg
.pre2_start_out (), // pre2_start_outh[1]), // output reg
.en_out (dcth_en_out1), // output reg
.dst_out (pre2_dsth[1]), // output valid with en_out
.y_index (dcth_yindex1) // output[2:0] reg
);
......@@ -587,8 +611,9 @@ module dtt_iv_8x8#(
.d_in (dctv_xin0), // input[23:0]
.start (dctv_start_0_r), // input
.dout (dctv_dout0), // output[23:0]
.pre2_start_out (), // output reg
.pre2_start_out (), // pre2_start_outv[0]), // output reg
.en_out (dctv_en_out0), // output reg
.dst_out (pre2_dstv[0]), // output valid with en_out
.y_index (dctv_yindex0) // output[2:0] reg
);
......@@ -616,12 +641,13 @@ module dtt_iv_8x8#(
.clk (clk), // input
.rst (rst), // input
.en (dctv_en1), // input
.dst_in (mode_v[1]) , // 0 - dct, 1 - dst. @ start/restart
.dst_in (mode_v[0]) , // 0 - dct, 1 - dst. @ start/restart
.d_in (dctv_xin1), // input[23:0]
.start (dctv_start_1_r), // input
.dout (dctv_dout1), // output[23:0]
.pre2_start_out (), // output reg
.pre2_start_out (), // pre2_start_outv[1]), // output reg
.en_out (dctv_en_out1), // output reg
.dst_out (pre2_dstv[1]), // output valid with en_out
.y_index (dctv_yindex1) // output[2:0] reg
);
......
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