added ifndef wrappers for attributes

memctrl/mcntrl_linear_rw.v

@@ -91,7 +91,10 @@ module  mcntrl_linear_rw #(
 // WARNING: [Synth 8-3936] Found unconnected internal register 'frame_y_reg' and it is trimmed from '16' to '3' bits. [memctrl/mcntrl_linear_rw.v:268]
 // Throblem seems to be that frame_y8_r_reg (load of trimmed bits of the frame_y_reg) is (as intended) absorbed into DSP48. The lower 3 bits are used
 // outside of the DSP 48.  "dont_touch" seems to work here
- (* keep = "true" *) reg   [FRAME_HEIGHT_BITS-1:0] frame_y;     // current line number referenced to the frame top
+  `ifndef IGNORE_ATTR
+    (* keep = "true" *) 
+  `endif
+    reg   [FRAME_HEIGHT_BITS-1:0] frame_y;     // current line number referenced to the frame top
     reg    [FRAME_WIDTH_BITS-1:0] frame_x;     // current column number referenced to the frame left
     reg   [FRAME_HEIGHT_BITS-4:0] frame_y8_r;  // (13 bits) current row with bank removed, latency2 (to be absorbed when inferred DSP multipler)
     reg      [FRAME_WIDTH_BITS:0] frame_full_width_r;  // (14 bit) register to be absorbed by MPY

memctrl/mcntrl_tiled_rw.v

@@ -103,7 +103,10 @@ module  mcntrl_tiled_rw#(
 //WARNING: [Synth 8-3936] Found unconnected internal register 'frame_y_reg' and it is trimmed from '16' to '3' bits. [memctrl/mcntrl_tiled_rw.v:307]
 // Throblem seems to be that frame_y8_r_reg (load of trimmed bits of the frame_y_reg) is (as intended) absorbed into DSP48. The lower 3 bits are used
 // outside of the DSP 48.  "dont_touch" seems to work here
-(* keep = "true" *) reg   [FRAME_HEIGHT_BITS-1:0] frame_y;     // current line number referenced to the frame top
+`ifndef IGNORE_ATTR
+  (* keep = "true" *) 
+`endif
+reg   [FRAME_HEIGHT_BITS-1:0] frame_y;     // current line number referenced to the frame top
     reg    [FRAME_WIDTH_BITS-1:0] frame_x;     // current column number referenced to the frame left
     reg   [FRAME_HEIGHT_BITS-4:0] frame_y8_r;  // (13 bits) current row with bank removed, latency2 (to be absorbed when inferred DSP multipler)
     reg      [FRAME_WIDTH_BITS:0] frame_full_width_r;  // (14 bit) register to be absorbed by MPY

memctrl/phy/byte_lane.v

@@ -60,10 +60,22 @@ wire dqs_read;
 wire  iclk;         // source-synchronous clock (BUFR from DQS)
 reg  [31:0] din_r=0;
 // Preventing register removal of equivalent registers
- (* keep = "true" *) reg  [3:0] din_dm_r=0, din_dqs_r=0, tin_dq_r=4'hf, tin_dqs_r=4'hf;
- (* keep = "true" *) reg  [7:0] dly_data_r=0; 
- (* keep = "true" *) reg        set_r=0;
- (* keep = "true" *) reg  dci_disable_dqs_r, dci_disable_dq_r;
+`ifndef IGNORE_ATTR
+  (* keep = "true" *) 
+`endif
+reg  [3:0] din_dm_r=0, din_dqs_r=0, tin_dq_r=4'hf, tin_dqs_r=4'hf;
+ `ifndef IGNORE_ATTR
+  (* keep = "true" *) 
+`endif
+reg  [7:0] dly_data_r=0; 
+`ifndef IGNORE_ATTR
+  (* keep = "true" *) 
+`endif
+reg        set_r=0;
+`ifndef IGNORE_ATTR
+  (* keep = "true" *) 
+`endif
+reg  dci_disable_dqs_r, dci_disable_dq_r;
 reg  [7:0] ld_odly=8'b0, ld_idly=8'b0;
 reg        ld_odly_dqs,ld_idly_dqs,ld_odly_dm;
 BUFR                          iclk_i    (.O(iclk),.I(dqs_read), .CLR(1'b0),.CE(1'b1)); // OK, works with constraint? Seems now work w/o

memctrl/phy/cmd_addr.v

@@ -61,8 +61,14 @@ reg  [1:0] in_we_r=2'h3, in_ras_r=2'h3, in_cas_r=2'h3, in_cke_r=2'h3, in_odt_r=2
 //reg  [1:0] in_tri_r=2'h0; // or tri-state on reset?
 reg  in_tri_r=1'b1; // or tri-state on reset?
 // Preventing register duplication
- (* keep = "true" *) reg  [7:0] dly_data_r=0; 
- (* keep = "true" *) reg        set_r=0;
+`ifndef IGNORE_ATTR
+(* keep = "true" *) 
+`endif
+reg  [7:0] dly_data_r=0; 
+`ifndef IGNORE_ATTR
+(* keep = "true" *) 
+`endif
+reg        set_r=0;
 reg  [7:0] ld_dly_cmd=8'b0;
 reg  [ADDRESS_NUMBER-1:0] ld_dly_addr=0;
 //wire  [ADDRESS_NUMBER-1:0] decode_addr;

wrap/idelay_ctrl.v

@@ -29,7 +29,9 @@ module  idelay_ctrl
     output rdy
 );
 
-(* IODELAY_GROUP = IODELAY_GRP *)
+`ifndef IGNORE_ATTR
+  (* IODELAY_GROUP = IODELAY_GRP *)
+`endif
 IDELAYCTRL idelay_ctrl_i(
     .RDY(rdy),
     .REFCLK(refclk),

wrap/idelay_fine_pipe.v

@@ -48,7 +48,10 @@ module  idelay_fine_pipe
             if (fdly_pre > 3'h4) $display ("ERROR: fine idelay value should be <5, specified %d @ %t", fdly_pre,$time);  
         end
     `endif
-(* IODELAY_GROUP = IODELAY_GRP *) IDELAYE2_FINEDELAY
+`ifndef IGNORE_ATTR
+  (* IODELAY_GROUP = IODELAY_GRP *) 
+`endif
+IDELAYE2_FINEDELAY
      #(
         .CINVCTRL_SEL("FALSE"),
         .DELAY_SRC("IDATAIN"),

wrap/idelay_nofine.v

@@ -34,7 +34,10 @@ module  idelay_nofine
     input data_in,
     output data_out
 );
-(* IODELAY_GROUP = IODELAY_GRP *) IDELAYE2
+`ifndef IGNORE_ATTR
+  (* IODELAY_GROUP = IODELAY_GRP *) 
+`endif
+IDELAYE2
      #(
         .CINVCTRL_SEL("FALSE"),
         .DELAY_SRC("IDATAIN"),

wrap/odelay_fine_pipe.v

@@ -48,7 +48,10 @@ module  odelay_fine_pipe
         end
     `endif
  
- (* IODELAY_GROUP = IODELAY_GRP *) ODELAYE2_FINEDELAY
+`ifndef IGNORE_ATTR
+  (* IODELAY_GROUP = IODELAY_GRP *) 
+`endif
+ ODELAYE2_FINEDELAY
      #(
         .CINVCTRL_SEL("FALSE"),
         .DELAY_SRC("ODATAIN"),

wrap/odelay_pipe.v

@@ -36,7 +36,10 @@ module  odelay_pipe
     output data_out
 );
  
- (* IODELAY_GROUP = IODELAY_GRP *) ODELAYE2
+`ifndef IGNORE_ATTR
+  (* IODELAY_GROUP = IODELAY_GRP *) 
+`endif
+ODELAYE2
      #(
         .CINVCTRL_SEL("FALSE"),
         .DELAY_SRC("ODATAIN"),

x393.v

@@ -51,9 +51,13 @@ module  x393 #(
 //    localparam ADDRESS_NUMBER=15;
 //    localparam COLADDR_NUMBER=10;
 // Source for reset and clock
-(* keep = "true" *)
+`ifndef IGNORE_ATTR
+  (* keep = "true" *)
+`endif
    wire    [3:0]     fclk;      // PL Clocks [3:0], output
-(* keep = "true" *)   
+`ifndef IGNORE_ATTR
+  (* keep = "true" *)   
+`endif
    wire    [3:0]     frst;      // PL Clocks [3:0], output
     
 // AXI write interface signals