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Commit de641880 authored by Andrey Filippov's avatar Andrey Filippov
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continiuing co-simulation with 353 code, verified martching data to the compressor input

parent 947d1d99
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compressor_jp/cmprs_cmd_decode.v
View file @ de641880
......@@ -153,6 +153,8 @@ module cmprs_cmd_decode#(
// cr_w, // data written to cr (1 cycle long) - just to reset legacy IRQ
// ntiles,//[17:0] - number of tiles in a frame to process
input frame_start, // @mclk
output frame_start_xclk, // frame start, parameters are copied at this pulse
// outputs sync @ posedge mclk:
output cmprs_en_mclk, // @mclk 0 resets immediately
input cmprs_en_extend, // @mclk keep compressor enabled for graceful shutdown
......@@ -162,7 +164,7 @@ module cmprs_cmd_decode#(
// cmprs_run should be off
output reg sigle_frame_buf, // memory controller uses a single frame buffer (frame_number_* == 0), use other sync
// outputs sync @ posedge xclk:
output reg cmprs_en_xclk, // enable compressor, turne off immedaitely
output reg cmprs_en_xclk, // enable compressor, turn off immedaitely
output reg cmprs_en_late_xclk, // enable stuffer, extends control fields for graceful shutdown
// cmprs_start, // single cycle when single or constant compression is turned on
// cmprs_repeat,// high in repetitive mode
......@@ -283,7 +285,7 @@ module cmprs_cmd_decode#(
if (mrst) format_mclk <= 0;
else if (format_we_r) format_mclk <= di_r[30:0];
if (mrst) color_sat_mclk <= 0;
if (mrst) color_sat_mclk <= 'h0b6090; // 'h16c120 - saturation = 2
else if (color_sat_we_r) color_sat_mclk <= di_r[23:0];
if (mrst) coring_mclk <= 0;
......@@ -292,10 +294,12 @@ module cmprs_cmd_decode#(
end
// re-clock to compressor clock
always @ (posedge xclk) if (ctrl_we_xclk) begin
always @ (posedge xclk) begin
cmprs_en_xclk <= cmprs_en_mclk_r;
cmprs_en_late_xclk <= cmprs_en_mclk_r || cmprs_en_extend;
end
always @ (posedge xclk) if (ctrl_we_xclk) begin
// cmprs_en_late_xclk <= cmprs_en_mclk_r || cmprs_en_extend;
cmprs_qpage_xclk <= cmprs_qpage_mclk;
cmprs_dcsub_xclk <= cmprs_dcsub_mclk;
cmprs_mode_xclk <= cmprs_mode_mclk;
......
compressor_jp/cmprs_frame_sync.v
View file @ de641880
......@@ -40,7 +40,7 @@ module cmprs_frame_sync#(
input cmprs_standalone, // @mclk single-cycle: generate a single frame_start_dst in unbonded (not synchronized) mode.
// cmprs_run should be off
input sigle_frame_buf, // memory controller uses a single frame buffer (frame_number_* == 0), use other sync
input vsync_late, // @xclk delayed start of frame, @xclk. In 353 it was 16 lines after VACT active
input vsync_late, // @mclk delayed start of frame, @xclk. In 353 it was 16 lines after VACT active
// source channel should already start, some delay give time for sequencer commands
// that should arrive before it
input frame_started, // @xclk started first macroblock (checking for broken frames)
......@@ -71,7 +71,7 @@ module cmprs_frame_sync#(
b) turned off enable while frame was being compressed
Abort frame lasts until flush end or timeout expire
*/
wire vsync_late_mclk; // single mclk cycle, reclocked from vsync_late
// wire vsync_late_mclk; // single mclk cycle, reclocked from vsync_late
wire frame_started_mclk;
reg bonded_mode;
reg frame_start_dst_r;
......@@ -86,12 +86,16 @@ module cmprs_frame_sync#(
reg [CMPRS_TIMEOUT_BITS-1:0] timeout;
reg cmprs_en_extend_r=0;
reg cmprs_en_d;
// reg cmprs_en_xclk;
assign frame_start_dst = frame_start_dst_r;
assign cmprs_en_extend = cmprs_en_extend_r;
assign stuffer_running_mclk = stuffer_running_mclk_r;
assign reading_frame = reading_frame_r;
// always @ (posedge xclk) begin
// cmprs_en_xclk <=cmprs_en;
// end
always @ (posedge mclk) begin
if (mrst) cmprs_en_extend_r <= 0;
else if (cmprs_en) cmprs_en_extend_r <= 1;
......@@ -107,34 +111,35 @@ module cmprs_frame_sync#(
cmprs_en_d <= cmprs_en;
broken_frame <= cmprs_en && cmprs_run && vsync_late_mclk && reading_frame_r; // single xclk pulse
broken_frame <= cmprs_en && cmprs_run && vsync_late && reading_frame_r; // single xclk pulse
aborted_frame <= cmprs_en_d && !cmprs_en && stuffer_running_mclk_r;
if (!stuffer_running_mclk_r ||!cmprs_en_extend_r) force_flush_long <= 0;
else if (broken_frame || aborted_frame) force_flush_long <= 1;
if (!cmprs_en || frame_done || (cmprs_run && vsync_late_mclk)) reading_frame_r <= 0;
if (!cmprs_en || frame_done || (cmprs_run && vsync_late)) reading_frame_r <= 0;
else if (frame_started_mclk) reading_frame_r <= 1;
frame_start_dst_r <= cmprs_en && (cmprs_run ? (vsync_late_mclk && !reading_frame_r) : cmprs_standalone);
frame_start_dst_r <= cmprs_en && (cmprs_run ? (vsync_late && !reading_frame_r) : cmprs_standalone);
if (!cmprs_en) bonded_mode <= 0;
else if (cmprs_run) bonded_mode <= 1;
else if (cmprs_standalone) bonded_mode <= 0;
if (!cmprs_en || !cmprs_run || vsync_late_mclk) frames_differ <= 0;
if (!cmprs_en || !cmprs_run || vsync_late) frames_differ <= 0;
else if (frame_done_src) frames_differ <= 1'b1;
frames_numbers_differ <= frame_number_src != frame_number;
line_numbers_sync <= (line_unfinished_src > line_unfinished);
suspend <= !bonded_mode && ((sigle_frame_buf ? frames_differ : frames_numbers_differ) || line_numbers_sync);
// suspend <= !bonded_mode && ((sigle_frame_buf ? frames_differ : frames_numbers_differ) || line_numbers_sync);
suspend <= bonded_mode && ((sigle_frame_buf ? frames_differ : frames_numbers_differ) || !line_numbers_sync);
end
pulse_cross_clock vsync_late_mclk_i (.rst(xrst), .src_clk(xclk), .dst_clk(mclk), .in_pulse(vsync_late), .out_pulse(vsync_late_mclk),.busy());
// pulse_cross_clock vsync_late_mclk_i (.rst(xrst), .src_clk(xclk), .dst_clk(mclk), .in_pulse(cmprs_en_xclk && vsync_late), .out_pulse(vsync_late_mclk),.busy());
pulse_cross_clock frame_started_i (.rst(xrst), .src_clk(xclk), .dst_clk(mclk), .in_pulse(frame_started), .out_pulse(frame_started_mclk),.busy());
endmodule
......
compressor_jp/cmprs_macroblock_buf_iface.v
View file @ de641880
......@@ -36,6 +36,7 @@ module cmprs_macroblock_buf_iface (
output next_page_chn, // single mclk (posedge): Done with the page in the buffer, memory controller may read more data
input frame_en, // if 0 - will reset logic immediately (but not page number)
input frame_start_xclk, // frame parameters are valid after this pulse
input frame_go, // start frame: if idle, will start reading data (if available),
// if running - will not restart a new frame if 0.
input [ 4:0] left_marg, // left margin (for not-yet-implemented) mono JPEG (8 lines tile row) can need 7 bits (mod 32 - tile)
......@@ -93,6 +94,7 @@ module cmprs_macroblock_buf_iface (
// reg first_mb; // from mb_pre_start[2] to mb_pre_start[1]
wire starting;
reg frame_pre_run;
reg [1:0] frame_may_start;
assign frame_en_w = frame_en && frame_go;
......@@ -106,14 +108,20 @@ module cmprs_macroblock_buf_iface (
assign last_mb = mb_last_row && mb_last_in_row;
assign starting = |mb_pre_start;
assign mb_pre_start_w = (mb_pre_end_in && (!last_mb || frame_en_w)) || (!frame_pre_run && frame_en_w && !frame_en_r && !starting);
assign frame_pre_start_w = frame_en_w && ((mb_pre_end_in && last_mb) || (!frame_pre_run && !frame_en_r && !starting));
// assign mb_pre_start_w = (mb_pre_end_in && (!last_mb || frame_en_w)) || (!frame_pre_run && frame_en_w && !frame_en_r && !starting);
// assign frame_pre_start_w = frame_en_w && ((mb_pre_end_in && last_mb) || (!frame_pre_run && !frame_en_r && !starting));
assign mb_pre_start_w = (mb_pre_end_in && (!last_mb || frame_may_start)) || ((frame_may_start==2'b1) && !frame_pre_run && !starting);
assign frame_pre_start_w = frame_may_start[0] && ((mb_pre_end_in && last_mb) || (!frame_pre_run && !frame_may_start[1] && !starting));
assign start_page = next_invalid[1:0]; // oldest page needed for this macroblock
always @ (posedge xclk) begin
if (!frame_en) frame_en_r <= 0;
else frame_en_r <= frame_en_w;
if (!frame_en_w || starting) frame_may_start[0] <= 0;
else if (frame_start_xclk) frame_may_start[0] <= 1;
frame_may_start[1] <= frame_may_start[0];
frame_pre_start_r <= frame_pre_start_w; // same time as mb_pre_start
if (!frame_en) mb_first_in_row <= 0;
......@@ -147,8 +155,10 @@ module cmprs_macroblock_buf_iface (
// calculate before starting each macroblock (will wait if buffer is not ready) (TODO: align mb_pre_start[0] to mb_pre_end[2] - same)
//mb_pre_start_w
if (!frame_en_r) mb_pre_start <= 0;
if (mb_pre_start_w) mb_pre_start <= 1;
else if (!mb_pre_start[4] || buf_ready_w) mb_pre_start <= mb_pre_start << 1;
if (mb_pre_start[1]) mbl_x_r[6:3] <= mb_first_in_row? {2'b0,left_marg[4:3]} : mbl_x_next_r[6:3];
if (mb_pre_start[2]) mbl_x_last_r[7:3] <= {1'b0,mbl_x_r[6:3]} + {2'b0,mb_w_m1[5:3]};
if (mb_pre_start[3]) begin
......@@ -163,7 +173,7 @@ module cmprs_macroblock_buf_iface (
// at the end of each macroblock - calculate start page increment (and after delay - advance invalidate_next)
// changed to after started:
// calculate next start X in page (regardless of emd of macroblock row - selection will be at macroblock start)
// calculate next start X in page (regardless of end of macroblock row - selection will be at macroblock start)
if (mb_pre_start[5]) mbl_x_inc_r[7:3] <= {1'b0,mbl_x_r[6:3]} + {3'b0,mb_hper[4:3]};
if (mb_pre_start[6]) begin
......
compressor_jp/cmprs_pixel_buf_iface.v
View file @ de641880
......@@ -44,8 +44,8 @@ module cmprs_pixel_buf_iface #(
output [ 1:0] buf_rd, // buf {regen, re}
// if running - will not restart a new frame if 0.
input [ 2:0] converter_type, // 0 - color18, 1 - color20, 2 - mono, 3 - jp4, 4 - jp4-diff, 7 - mono8 (not yet implemented)
input [ 5:0] mb_w_m1, // macroblock width minus 1 // 3 LSB not used, SHOULD BE SET to 3'b111
input [ 5:0] mb_h_m1, // macroblock horizontal period (8/16) // 3 LSB not used SHOULD BE SET to 3'b111
input [ 5:0] mb_w_m1, // macroblock width minus 1
input [ 5:0] mb_h_m1, // macroblock height minus 1
input [ 1:0] tile_width, // memory tile width (can be 128 for monochrome JPEG) Can be 32/64/128: 0 - 16, 1 - 32, 2 - 64, 3 - 128
input tile_col_width, // 0 - 16 pixels, 1 -32 pixels
// Tiles/macroblocks level (from cmprs_macroblock_buf_iface)
......@@ -55,9 +55,9 @@ module cmprs_pixel_buf_iface #(
input mb_pre_start, // 1 clock cycle before stream of addresses to the buffer
input [ 1:0] start_page, // page to read next tile from (or first of several pages)
input [ 6:0] macroblock_x, // macroblock left pixel x relative to a tile (page) Maximal page - 128 bytes wide
output [ 7:0] data_out, //
output reg [ 7:0] data_out, //
output pre_first_out, // For each macroblock in a frame
output data_valid //
output reg data_valid //
);
localparam PERIOD_COLOR18 = 384; // >18*18, limited by 6*64 (macroblocks)
localparam PERIOD_COLOR20 = 400; // limited by the 20x20 padded macroblock
......@@ -68,7 +68,7 @@ module cmprs_pixel_buf_iface #(
reg [CMPRS_BUF_EXTRA_LATENCY+3:0] buf_re=0;
reg [ 7:0] do_r;
// reg [ 7:0] do_r;
reg [11:0] bufa_r; // buffer read address (2 MSB - page number)
reg [11:0] row_sa; // row start address
reg [ 9:0] tile_sa; // tile start address for the same row (w/o page number) for continuing row
......@@ -79,9 +79,9 @@ module cmprs_pixel_buf_iface #(
reg [ 5:0] rows_left;
reg [ 6:0] tile_x; // horizontal position in a tile
reg [ 4:0] column_x; // horizontal position in a column (0..31 or 0..15)
reg last_col;
reg first_col;
reg last_row;
reg last_col; // macroblock last column
reg first_col; // macroblock first column
reg last_row; // macroblock last row
wire addr_run_end; // generate last cycle of address run
wire [ 6:0] tile_width_or; // set unused msb to all 1
......@@ -105,9 +105,8 @@ module cmprs_pixel_buf_iface #(
assign mb_pre_end = mb_pre_end_r;
assign mb_release_buf = mb_release_buf_r;
assign buf_rd = buf_re[1:0];
assign data_out = do_r;
// assign data_out = do_r;
assign pre_first_out = pre_first_out_r;
assign data_valid = buf_re[CMPRS_BUF_EXTRA_LATENCY+2];
always @(posedge xclk) begin
if (!frame_en) buf_re[0] <= 0;
......@@ -118,7 +117,7 @@ module cmprs_pixel_buf_iface #(
else buf_re[CMPRS_BUF_EXTRA_LATENCY+3:1] <= {buf_re[CMPRS_BUF_EXTRA_LATENCY+2:0]};
// Buffer data read:
if (buf_re[CMPRS_BUF_EXTRA_LATENCY+2]) do_r <= buf_di;
if (buf_re[CMPRS_BUF_EXTRA_LATENCY+2]) data_out <= buf_di;
if (!frame_en) pre_first_out_r <= 0;
else pre_first_out_r <= buf_re[CMPRS_BUF_EXTRA_LATENCY+1] && ! buf_re[CMPRS_BUF_EXTRA_LATENCY+2];
......@@ -131,10 +130,12 @@ module cmprs_pixel_buf_iface #(
if (!frame_en) buf_re[CMPRS_BUF_EXTRA_LATENCY+2:1] <= 0;
if (buf_re[0]) last_col <= 0;
// if (buf_re[0]) last_col <= 0; // ????
if (!buf_re[0]) last_col <= 0;
else last_col <= (cols_left == 1);
if (buf_re[0]) last_row <= 0;
// if (buf_re[0]) last_row <= 0;
if (!buf_re[0]) last_row <= 0;
else if (last_col) last_row <= (rows_left == 1);
first_col <= (mb_pre_start || (last_col && !last_row));
......@@ -153,12 +154,13 @@ module cmprs_pixel_buf_iface #(
if (mb_pre_start || last_col) tile_x <= {2'b0,macroblock_x[4:0]} | tile_width_or;
else if (buf_re[0]) tile_x <= (tile_x+1) | tile_width_or;
if (mb_pre_start || last_col) bufa_r[11:10] <= start_page;
if (mb_pre_start) bufa_r[11:10] <= start_page;
else if (last_col) bufa_r[11:10] <= row_sa[11:10]; // start_page;
else if (last_in_tile) bufa_r[11:10] <= bufa_r[11:10] + 1;
// Most time critical - calculation of the buffer address
if (mb_pre_start) bufa_r[9:0] <= {3'b0,macroblock_x};
else if (last_col) bufa_r[9:0] <= row_sa[9:0];
else if (last_col) bufa_r[9:0] <= row_sa[9:0]; // 'bx next cycle after AFTER mb_pre_start
else if (last_in_tile) bufa_r[9:0] <= tile_sa;
else if (buf_re[0]) bufa_r[9:0] <= bufa_r[9:0] + {last_in_col?col_inc[9:4]:6'b0,4'b1};
......@@ -166,7 +168,7 @@ module cmprs_pixel_buf_iface #(
if (!frame_en) period_cntr <= 0;
else if (mb_pre_start) begin
case (converter_type[2:0])
CMPRS_COLOR18: period_cntr <= PERIOD_COLOR18 - 1;
CMPRS_COLOR18: period_cntr <= PERIOD_COLOR18 - 1; // period = 384 - limited by 6*64, not by 18x18
CMPRS_COLOR20: period_cntr <= PERIOD_COLOR20 - 1;
CMPRS_MONO16: period_cntr <= PERIOD_MONO16 - 1;
CMPRS_JP4: period_cntr <= PERIOD_JP4 - 1;
......@@ -182,6 +184,18 @@ module cmprs_pixel_buf_iface #(
if (!frame_en) mb_release_buf_r <= 0;
else mb_release_buf_r <= (period_cntr == (CMPRS_RELEASE_EARLY+1));
data_valid <= buf_re[CMPRS_BUF_EXTRA_LATENCY+2];
end
`ifdef SIMULATION
reg [8:0] sim_dout_cntr;
always @(posedge xclk) begin
if (!data_valid) sim_dout_cntr <= 0;
else sim_dout_cntr <= sim_dout_cntr + 1;
if (data_valid) begin
$display("CMPRS INPUT %x:%x @ %t",sim_dout_cntr, data_out, $time);
end
end
`endif
endmodule
compressor_jp/cmprs_tile_mode_decode.v
View file @ de641880
......@@ -29,9 +29,9 @@ module cmprs_tile_mode_decode #(
parameter CMPRS_MONO8 = 7 // Regular JPEG monochrome with 8x8 macroblocks (not yet implemented)
)(
input [2:0] converter_type,
output reg [ 5:0] mb_w_m1, // macroblock width minus 1 // 3 LSB not used, SHOULD BE SET to 3'b111
output reg [ 5:0] mb_h_m1, // macroblock horizontal period (8/16) // 3 LSB not used SHOULD BE SET to 3'b111
output reg [ 4:0] mb_hper, // macroblock horizontal period (8/16) // 3 LSB not used TODO: assign from converter_type[2:0]
output reg [ 5:0] mb_w_m1, // macroblock width minus 1
output reg [ 5:0] mb_h_m1, // macroblock height minus 1
output reg [ 4:0] mb_hper, // macroblock horizontal period (8/16) // 3 LSB not used
output reg [ 1:0] tile_width, // memory tile width (can be 128 for monochrome JPEG) Can be 32/64/128: 0 - 16, 1 - 32, 2 - 64, 3 - 128
output reg tile_col_width // 0 - 16 pixels, 1 -32 pixels
);
......@@ -40,51 +40,51 @@ module cmprs_tile_mode_decode #(
always @(converter_type) begin
case (converter_type)
CMPRS_COLOR18: begin
mb_w_m1 <= 17; // macroblock width minus 1 // 3 LSB not used, SHOULD BE SET to 3'b111
mb_h_m1 <= 17; // macroblock horizontal period (8/16) // 3 LSB not used SHOULD BE SET to 3'b111
mb_hper <= 16; // macroblock horizontal period (8/16) // 3 LSB not used TODO: assign from converter_type[2:0]
mb_w_m1 <= 17; // macroblock width minus 1
mb_h_m1 <= 17; // macroblock height minus 1
mb_hper <= 16; // macroblock horizontal period (8/16) // 3 LSB not used
tile_width <= 1; // memory tile width (can be 128 for monochrome JPEG) Can be 32/64/128: 0 - 16, 1 - 32, 2 - 64, 3 - 128
tile_col_width <= 1; // 0 - 16 pixels, 1 -32 pixels
end
CMPRS_COLOR20: begin
mb_w_m1 <= 19; // macroblock width minus 1 // 3 LSB not used, SHOULD BE SET to 3'b111
mb_h_m1 <= 19; // macroblock horizontal period (8/16) // 3 LSB not used SHOULD BE SET to 3'b111
mb_hper <= 16; // macroblock horizontal period (8/16) // 3 LSB not used TODO: assign from converter_type[2:0]
mb_w_m1 <= 19; // macroblock width minus 1
mb_h_m1 <= 19; // macroblock height minus 1
mb_hper <= 16; // macroblock horizontal period (8/16) // 3 LSB not used
tile_width <= 1; // memory tile width (can be 128 for monochrome JPEG) Can be 32/64/128: 0 - 16, 1 - 32, 2 - 64, 3 - 128
tile_col_width <= 1; // 0 - 16 pixels, 1 -32 pixels
end
CMPRS_MONO16: begin
mb_w_m1 <= 15; // macroblock width minus 1 // 3 LSB not used, SHOULD BE SET to 3'b111
mb_h_m1 <= 15; // macroblock horizontal period (8/16) // 3 LSB not used SHOULD BE SET to 3'b111
mb_hper <= 16; // macroblock horizontal period (8/16) // 3 LSB not used TODO: assign from converter_type[2:0]
mb_w_m1 <= 15; // macroblock width minus 1
mb_h_m1 <= 15; // macroblock height minus 1
mb_hper <= 16; // macroblock horizontal period (8/16) // 3 LSB not used
tile_width <= 2; // memory tile width (can be 128 for monochrome JPEG) Can be 32/64/128: 0 - 16, 1 - 32, 2 - 64, 3 - 128
tile_col_width <= 1; // 0 - 16 pixels, 1 -32 pixels
end
CMPRS_JP4: begin
mb_w_m1 <= 15; // macroblock width minus 1 // 3 LSB not used, SHOULD BE SET to 3'b111
mb_h_m1 <= 15; // macroblock horizontal period (8/16) // 3 LSB not used SHOULD BE SET to 3'b111
mb_hper <= 16; // macroblock horizontal period (8/16) // 3 LSB not used TODO: assign from converter_type[2:0]
mb_w_m1 <= 15; // macroblock width minus 1
mb_h_m1 <= 15; // macroblock height minus 1
mb_hper <= 16; // macroblock horizontal period (8/16) // 3 LSB not used
tile_width <= 2; // memory tile width (can be 128 for monochrome JPEG) Can be 32/64/128: 0 - 16, 1 - 32, 2 - 64, 3 - 128
tile_col_width <= 1; // 0 - 16 pixels, 1 -32 pixels
end
CMPRS_JP4DIFF: begin
mb_w_m1 <= 15; // macroblock width minus 1 // 3 LSB not used, SHOULD BE SET to 3'b111
mb_h_m1 <= 15; // macroblock horizontal period (8/16) // 3 LSB not used SHOULD BE SET to 3'b111
mb_hper <= 16; // macroblock horizontal period (8/16) // 3 LSB not used TODO: assign from converter_type[2:0]
mb_w_m1 <= 15; // macroblock width minus 1
mb_h_m1 <= 15; // macroblock height minus 1
mb_hper <= 16; // macroblock horizontal period (8/16) // 3 LSB not used
tile_width <= 2; // memory tile width (can be 128 for monochrome JPEG) Can be 32/64/128: 0 - 16, 1 - 32, 2 - 64, 3 - 128
tile_col_width <= 1; // 0 - 16 pixels, 1 -32 pixels
end
CMPRS_MONO8: begin
mb_w_m1 <= 7; // macroblock width minus 1 // 3 LSB not used, SHOULD BE SET to 3'b111
mb_h_m1 <= 7; // macroblock horizontal period (8/16) // 3 LSB not used SHOULD BE SET to 3'b111
mb_hper <= 8; // macroblock horizontal period (8/16) // 3 LSB not used TODO: assign from converter_type[2:0]
mb_w_m1 <= 7; // macroblock width minus 1
mb_h_m1 <= 7; // macroblock height minus 1
mb_hper <= 8; // macroblock horizontal period (8/16) // 3 LSB not used
tile_width <= 3; // memory tile width (can be 128 for monochrome JPEG) Can be 32/64/128: 0 - 16, 1 - 32, 2 - 64, 3 - 128
tile_col_width <= 1; // 0 - 16 pixels, 1 -32 pixels
end
default: begin
mb_w_m1 <= 'bx; // macroblock width minus 1 // 3 LSB not used, SHOULD BE SET to 3'b111
mb_h_m1 <= 'bx; // macroblock horizontal period (8/16) // 3 LSB not used SHOULD BE SET to 3'b111
mb_hper <= 'bx; // macroblock horizontal period (8/16) // 3 LSB not used TODO: assign from converter_type[2:0]
mb_w_m1 <= 'bx; // macroblock width minus 1
mb_h_m1 <= 'bx; // macroblock height minus 1
mb_hper <= 'bx; // macroblock horizontal period (8/16) // 3 LSB not used
tile_width <= 'bx; // memory tile width (can be 128 for monochrome JPEG) Can be 32/64/128: 0 - 16, 1 - 32, 2 - 64, 3 - 128
tile_col_width <= 'bx; // 0 - 16 pixels, 1 -32 pixels
end
......
compressor_jp/compressor393.v
View file @ de641880
......@@ -167,7 +167,7 @@ module compressor393 # (
output [3:0] stuffer_done_mclk,
// frame input synchronization
input [3:0] vsync_late, // delayed start of frame, @xclk. In 353 it was 16 lines after VACT active
input [3:0] vsync_late, // delayed start of frame, @mclk. In 353 it was 16 lines after VACT active
// source channel should already start, some delay give time for sequencer commands
// that should arrive before it
......
compressor_jp/jp_channel.v
View file @ de641880
......@@ -156,7 +156,7 @@ module jp_channel#(
output stuffer_done_mclk,
// output [31:0] hifreq, // accumulated high frequency components in a frame sub-window
input vsync_late, // delayed start of frame, @xclk. In 353 it was 16 lines after VACT active
input vsync_late, // delayed start of frame, @mclk. In 353 it was 16 lines after VACT active
// source channel should already start, some delay give time for sequencer commands
// that should arrive before it
......@@ -177,6 +177,7 @@ module jp_channel#(
// Control signals to be defined
wire frame_en; // if 0 - will reset logic immediately (but not page number)
wire frame_start_xclk; // re-clocked, parameters are copied at this pulse
wire stuffer_en; // extended enable to allow stuffer to gracefully finish
wire frame_go=frame_en; // start frame: if idle, will start reading data (if available),
......@@ -200,9 +201,9 @@ module jp_channel#(
wire [ 1:0] cmprs_fmode; // focusing/overlay mode
//TODO: assign next 5 values from converter_type[2:0]
wire [ 5:0] mb_w_m1; // macroblock width minus 1 // 3 LSB not used, SHOULD BE SET to 3'b111
wire [ 5:0] mb_h_m1; // macroblock horizontal period (8/16) // 3 LSB not used SHOULD BE SET to 3'b111
wire [ 4:0] mb_hper; // macroblock horizontal period (8/16) // 3 LSB not used TODO: assign from converter_type[2:0]
wire [ 5:0] mb_w_m1; // macroblock width minus 1
wire [ 5:0] mb_h_m1; // macroblock height -1
wire [ 4:0] mb_hper; // macroblock horizontal period (8/16) // 3 LSB not used
wire [ 1:0] tile_width; // memory tile width (can be 128 for monochrome JPEG) Can be 32/64/128: 0 - 16, 1 - 32, 2 - 64, 3 - 128
wire tile_col_width; // 0 - 16 pixels, 1 -32 pixels
......@@ -450,6 +451,7 @@ module jp_channel#(
.coring_we (set_coring_w), // input - write color saturation values
.di (cmd_data), // input[31:0] - 32-bit data to write to control register (24LSB are used)
.frame_start (frame_start_dst), // input @mclk
.frame_start_xclk (frame_start_xclk), // re-clocked, parameters are copied during this pulse
.cmprs_en_mclk (cmprs_en_mclk), // output
.cmprs_en_extend (cmprs_en_extend), // input
.cmprs_run_mclk (cmprs_run_mclk), // output reg
......@@ -512,10 +514,10 @@ module jp_channel#(
.cmprs_standalone (cmprs_standalone), // input - @mclk single-cycle: generate a single frame_start_dst in unbonded (not synchronized) mode.
// cmprs_run should be off
.sigle_frame_buf (sigle_frame_buf), // input - memory controller uses a single frame buffer (frame_number_* == 0), use other sync
.vsync_late (vsync_late), // input - @xclk delayed start of frame, @xclk. In 353 it was 16 lines after VACT active
.vsync_late (vsync_late), // input - @mclk delayed start of frame, @xclk. In 353 it was 16 lines after VACT active
// source channel should already start, some delay give time for sequencer commands
// that should arrive before it
.frame_started (first_mb && mb_pre_start), // @xclk started first macroblock (checking fro broken frames)
.frame_started (first_mb && mb_pre_start), // @xclk started first macroblock (checking for broken frames)
.frame_start_dst (frame_start_dst), // output reg @mclk - trigger receive (tiled) memory channel (it will take care of
// single/repetitive modes itself this output either follows vsync_late (reclocks it)
// or generated in non-bonded mode (compress from memory once)
......@@ -545,11 +547,12 @@ module jp_channel#(
.page_ready_chn (page_ready_chn), // input
.next_page_chn (next_page_chn), // output
.frame_en (frame_en), // input
.frame_start_xclk (frame_start_xclk), // input@posedge xclk - parameters are copied @ this pulse
.frame_go (frame_go), // input - do not use - assign to frame_en? Running frames can be controlled by other means
.left_marg (left_marg), // input[4:0]
.n_blocks_in_row_m1 (n_blocks_in_row_m1), // input[12:0]
.n_block_rows_m1 (n_block_rows_m1), // input[12:0]
.mb_w_m1 (mb_w_m1), // input[5:0] // macroblock width minus 1 // 3 LSB not used - set them to all 1
.mb_w_m1 (mb_w_m1), // input[5:0] // macroblock width minus 1 // 3 LSB not used here
.mb_hper (mb_hper), // input[4:0] // macroblock horizontal period (8/16) // 3 LSB not used (set them 0)
.tile_width (tile_width), // input[1:0] // memory tile width. Can be 32/64/128: 0 - 16, 1 - 32, 2 - 64, 3 - 128
.mb_pre_end_in (mb_pre_end), // input
......
ddr3/ddr3.v
View file @ de641880
......@@ -669,8 +669,8 @@ module ddr3 (
// $fseek returns 0 on success, -1 on failure
if (code != 0)
begin
$display("%m: at time %t ERROR: fseek to %d failed", $time, offset);
$finish;
$display("%m: at time %t ERROR: fseek to %d failed index=%d ", $time, offset, index);
// $finish;
end
`ifdef CVC
code = $fgets(read_str, fd);
......
memctrl/mcntrl_linear_rw.v
View file @ de641880
......@@ -113,7 +113,8 @@ module mcntrl_linear_rw #(
reg [FRAME_WIDTH_BITS:0] frame_full_width_r; // (14 bit) register to be absorbed by MPY
reg [MPY_WIDTH-1:0] mul_rslt;
reg [NUM_RC_BURST_BITS-1:0] start_addr_r; // 22 bit - to be absorbed by DSP
reg [2:0] bank_reg [2:0];
// reg [2:0] bank_reg [2:0];
reg [3 * 3 - 1:0] bank_reg;
wire [FRAME_WIDTH_BITS+FRAME_HEIGHT_BITS-3:0] mul_rslt_w;
reg [FRAME_WIDTH_BITS:0] row_left; // number of 8-bursts left in the current row
reg last_in_row;
......@@ -166,7 +167,10 @@ module mcntrl_linear_rw #(
reg last_block;
reg [MCNTRL_SCANLINE_PENDING_CNTR_BITS-1:0] pending_xfers; // number of requested,. but not finished block transfers
reg [NUM_RC_BURST_BITS-1:0] row_col_r;
reg [FRAME_HEIGHT_BITS-1:0] line_unfinished_r [1:0];
// reg [2*FRAME_HEIGHT_BITS-1:0] line_unfinished_r;
reg [FRAME_HEIGHT_BITS-1:0] line_unfinished_relw_r;
reg [FRAME_HEIGHT_BITS-1:0] line_unfinished_r;
wire pre_want;
wire [1:0] status_data;
wire [3:0] cmd_a;
......@@ -322,10 +326,10 @@ module mcntrl_linear_rw #(
assign last_row_w= next_y==window_height;
assign xfer_want= want_r;
assign xfer_need= need_r;
assign xfer_bank= bank_reg[2]; // TODO: just a single reg layer
assign xfer_bank= bank_reg[3 * 2 +: 3]; // TODO: just a single reg layer
assign xfer_row= row_col_r[NUM_RC_BURST_BITS-1:COLADDR_NUMBER-3] ; // memory row
assign xfer_col= row_col_r[COLADDR_NUMBER-4:0]; // start memory column in 8-bursts
assign line_unfinished=line_unfinished_r[1];
assign line_unfinished = line_unfinished_r; // [FRAME_HEIGHT_BITS +: FRAME_HEIGHT_BITS];
assign chn_en = mode_reg[MCONTR_LINTILE_NRESET] & mode_reg[MCONTR_LINTILE_EN]; // enable requests by channel (continue ones in progress)
assign chn_rst = ~mode_reg[MCONTR_LINTILE_NRESET]; // resets command, including fifo;
assign cmd_wrmem = mode_reg[MCONTR_LINTILE_WRITE];// 0: read from memory, 1:write to memory
......@@ -364,9 +368,9 @@ module mcntrl_linear_rw #(
// line_start_page_left <= {COLADDR_NUMBER-3{1'b0}} - line_start_addr[COLADDR_NUMBER-4:0]; // 7 bits
line_start_page_left <= - line_start_addr[COLADDR_NUMBER-4:0]; // 7 bits
end
bank_reg[0] <= frame_y[2:0]; //TODO: is it needed - a pipeline for the bank? - remove!
bank_reg[0 +:3] <= frame_y[2:0]; //TODO: is it needed - a pipeline for the bank? - remove!
for (i=0;i<2; i = i+1)
bank_reg[i+1] <= bank_reg[i];
bank_reg[(i+1)*3 +:3] <= bank_reg[i * 3 +: 3];
if (recalc_r[6]) begin // cycle 7
......@@ -483,20 +487,34 @@ wire start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r;
else if ( xfer_start_r[0] && !xfer_done) pending_xfers <= pending_xfers + 1;
else if (!xfer_start_r[0] && xfer_done) pending_xfers <= pending_xfers - 1;
/*
//line_unfinished_r cmd_wrmem
if (mrst) line_unfinished_r[0] <= 0; //{FRAME_HEIGHT_BITS{1'b0}};
else if (chn_rst || frame_start_r[0]) line_unfinished_r[0] <= window_y0+start_y;
else if (xfer_start_r[2]) line_unfinished_r[0] <= window_y0+next_y[FRAME_HEIGHT_BITS-1:0]; // latency 2 from xfer_start
if (mrst) line_unfinished_r[0 +: FRAME_HEIGHT_BITS] <= 0; //{FRAME_HEIGHT_BITS{1'b0}};
else if (chn_rst || frame_start_r[0]) line_unfinished_r[0 +: FRAME_HEIGHT_BITS] <= window_y0+start_y;
else if (xfer_start_r[2]) line_unfinished_r[0 +: FRAME_HEIGHT_BITS] <= window_y0+next_y[FRAME_HEIGHT_BITS-1:0]; // latency 2 from xfer_start
if (mrst) line_unfinished_r[1] <= 0; //{FRAME_HEIGHT_BITS{1'b0}};
if (mrst) line_unfinished_r[FRAME_HEIGHT_BITS +: FRAME_HEIGHT_BITS] <= 0; //{FRAME_HEIGHT_BITS{1'b0}};
// else if (chn_rst || frame_start_r[0]) line_unfinished_r[1] <= window_y0+start_y;
else if (chn_rst || frame_start_r[2]) line_unfinished_r[1] <= window_y0+start_y; // _r[0] -> _r[2] to make it simultaneous with frame_number
else if (chn_rst || frame_start_r[2]) line_unfinished_r[FRAME_HEIGHT_BITS +: FRAME_HEIGHT_BITS] <= window_y0+start_y; // _r[0] -> _r[2] to make it simultaneous with frame_number
// in read mode advance line number ASAP
else if (xfer_start_r[2] && !cmd_wrmem) line_unfinished_r[1] <= window_y0+next_y[FRAME_HEIGHT_BITS-1:0]; // latency 2 from xfer_start
else if (xfer_start_r[2] && !cmd_wrmem) line_unfinished_r[FRAME_HEIGHT_BITS +: FRAME_HEIGHT_BITS] <= window_y0+next_y[FRAME_HEIGHT_BITS-1:0]; // latency 2 from xfer_start
// in write mode advance line number only when it is guaranteed it will be the first to actually access memory
else if (xfer_grant && cmd_wrmem) line_unfinished_r[1] <= line_unfinished_r[0];
else if (xfer_grant && cmd_wrmem) line_unfinished_r[FRAME_HEIGHT_BITS +: FRAME_HEIGHT_BITS] <= line_unfinished_r[0 +: FRAME_HEIGHT_BITS];
*/
/*
if (mrst) line_unfinished_relw_r <= 0;
else if (cmd_wrmem && (frame_start_r[1] || !chn_en)) line_unfinished_relw_r <= start_y;
else if ((!cmd_wrmem && recalc_r[1]) || xfer_start_r[2]) line_unfinished_relw_r <= next_y[FRAME_HEIGHT_BITS-1:0];
// xfer_start_r[2] and recalc_r[1] are at the same time
if (mrst || (frame_start || !chn_en)) line_unfinished_r <= {FRAME_HEIGHT_BITS{~cmd_wrmem}}; // lowest/highest value until valid
else if (recalc_r[2]) line_unfinished_r <= line_unfinished_relw_r + window_y0;
*/
if (recalc_r[0]) line_unfinished_relw_r <= curr_y + (cmd_wrmem ? 0: 1);
if (mrst || (frame_start || !chn_en)) line_unfinished_r <= {FRAME_HEIGHT_BITS{~cmd_wrmem}}; // lowest/highest value until valid
else if (recalc_r[2]) line_unfinished_r <= line_unfinished_relw_r + window_y0;
end
always @ (negedge mclk) begin
......
memctrl/mcntrl_tiled_rw.v
View file @ de641880
......@@ -129,7 +129,8 @@ module mcntrl_tiled_rw#(
reg [FRAME_WIDTH_BITS:0] frame_full_width_r; // (14 bit) register to be absorbed by MPY
reg [MPY_WIDTH-1:0] mul_rslt;
reg [NUM_RC_BURST_BITS-1:0] start_addr_r; // 22 bit - to be absorbed by DSP
reg [2:0] bank_reg [2:0];
// reg [2:0] bank_reg [2:0];
reg [3 * 3 - 1:0] bank_reg;
wire [FRAME_WIDTH_BITS+FRAME_HEIGHT_BITS-3:0] mul_rslt_w;
// wire [2:0] cur_bank;
reg [FRAME_WIDTH_BITS:0] row_left; // number of 8-bursts left in the current row
......@@ -180,7 +181,9 @@ module mcntrl_tiled_rw#(
reg [NUM_RC_BURST_BITS-1:0] row_col_r;
// reg [FRAME_HEIGHT_BITS-1:0] line_unfinished_r0;
// reg [FRAME_HEIGHT_BITS-1:0] line_unfinished_r1;
reg [FRAME_HEIGHT_BITS-1:0] line_unfinished_r [1:0];
// reg [2*FRAME_HEIGHT_BITS-1:0] line_unfinished_r;
reg [FRAME_HEIGHT_BITS-1:0] line_unfinished_relw_r;
reg [FRAME_HEIGHT_BITS-1:0] line_unfinished_r;
wire pre_want;
wire [1:0] status_data;
......@@ -203,7 +206,7 @@ module mcntrl_tiled_rw#(
// wire msw13_zero=!(|cmd_data[FRAME_WIDTH_BITS+15:16]); // MSW 13 (FRAME_WIDTH_BITS) low bits are all 0 - set carry bit
wire msw_zero= !(|cmd_data[31:16]); // MSW all bits are 0 - set carry bit
wire tile_width_zero= !(|cmd_data[ 0+:MAX_TILE_WIDTH]);
// wire tile_height_zero=!(|cmd_data[ 8+:MAX_TILE_HEIGHT]);
wire tile_height_zero=!(|cmd_data[ 8+:MAX_TILE_HEIGHT]);
wire tile_vstep_zero= !(|cmd_data[16+:MAX_TILE_HEIGHT]);
// reg [5:0] mode_reg;//mode register: {write_mode,keep_open,extra_pages[1:0],enable,!reset}
......@@ -223,7 +226,8 @@ module mcntrl_tiled_rw#(
reg [MAX_TILE_WIDTH:0] tile_cols; // full number of columns in a tile
// reg [MAX_TILE_HEIGHT:0] tile_rows; // full number of rows in a tile
reg [MAX_TILE_HEIGHT-1:0] tile_rows; // full number of rows in a tile
// reg [MAX_TILE_HEIGHT-1:0] tile_rows; // full number of rows in a tile
reg [MAX_TILE_HEIGHT:0] tile_rows; // full number of rows in a tile
reg [MAX_TILE_HEIGHT:0] tile_vstep; // vertical step between rows of tiles
reg [MAX_TILE_WIDTH:0] num_cols_r; // full number of columns to transfer (not minus 1)
......@@ -327,7 +331,7 @@ module mcntrl_tiled_rw#(
tile_vstep <= 0;
end else if (set_tile_whs_w) begin
tile_cols <= {tile_width_zero, cmd_data[ 0+:MAX_TILE_WIDTH]};
tile_rows <= { cmd_data[ 8+:MAX_TILE_HEIGHT]};
tile_rows <= {tile_height_zero, cmd_data[ 8+:MAX_TILE_HEIGHT]};
tile_vstep <= {tile_vstep_zero, cmd_data[16+:MAX_TILE_HEIGHT]};
end
......@@ -365,10 +369,11 @@ module mcntrl_tiled_rw#(
//window_m_tile_height
assign xfer_want= want_r;
assign xfer_need= need_r;
assign xfer_bank= bank_reg[2]; // TODO: just a single reg layer
assign xfer_bank= bank_reg[2*3 +: 3]; // TODO: just a single reg layer
assign xfer_row= row_col_r[NUM_RC_BURST_BITS-1:COLADDR_NUMBER-3] ; // memory row
assign xfer_col= row_col_r[COLADDR_NUMBER-4:0]; // start memory column in 8-bursts
assign line_unfinished=line_unfinished_r[1];
// assign line_unfinished = line_unfinished_r[FRAME_HEIGHT_BITS +: FRAME_HEIGHT_BITS];
assign line_unfinished = line_unfinished_r;
assign chn_en = mode_reg[MCONTR_LINTILE_NRESET] & mode_reg[MCONTR_LINTILE_EN]; // enable requests by channel (continue ones in progress)
assign chn_rst = ~mode_reg[MCONTR_LINTILE_NRESET]; // resets command, including fifo;
......@@ -416,9 +421,9 @@ module mcntrl_tiled_rw#(
row_col_r <= line_start_addr+frame_x;
line_start_page_left <= - line_start_addr[COLADDR_NUMBER-4:0]; // 7 bits
end
bank_reg[0] <= frame_y[2:0]; //TODO: is it needed - a pipeline for the bank? - remove!
for (i=0;i<2; i = i+1)
bank_reg[i+1] <= bank_reg[i];
bank_reg[0 +: 3] <= frame_y[2:0]; //TODO: is it needed - a pipeline for the bank? - remove!
for (i=0; i<2; i = i+1)
bank_reg[(i+1)*3 +: 3] <= bank_reg[i*3 +: 3];
if (recalc_r[6]) begin // cycle 7
mem_page_left <= {1'b1,line_start_page_left} - frame_x[COLADDR_NUMBER-4:0];
......@@ -535,18 +540,32 @@ wire start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r;
else if (chn_rst || frame_start_r[0]) frame_finished_r <= 0;
else if (frame_done_r) frame_finished_r <= 1;
//line_unfinished_r cmd_wrmem
if (mrst) line_unfinished_r[0] <= 0; //{FRAME_HEIGHT_BITS{1'b0}};
else if (chn_rst || frame_start_r[0]) line_unfinished_r[0] <= window_y0+start_y;
else if (xfer_start_r[2]) line_unfinished_r[0] <= window_y0+next_y[FRAME_HEIGHT_BITS-1:0]; // latency 2 from xfer_start
/*
if (mrst) line_unfinished_r[0 +: FRAME_HEIGHT_BITS] <= 0; //{FRAME_HEIGHT_BITS{1'b0}};
else if (chn_rst || frame_start_r[0]) line_unfinished_r[0 +: FRAME_HEIGHT_BITS] <= window_y0+start_y;
else if (xfer_start_r[2]) line_unfinished_r[0 +: FRAME_HEIGHT_BITS] <= window_y0+next_y[FRAME_HEIGHT_BITS-1:0]; // latency 2 from xfer_start
if (mrst) line_unfinished_r[1] <= 0; //{FRAME_HEIGHT_BITS{1'b0}};
else if (chn_rst || frame_start_r[2]) line_unfinished_r[1] <= window_y0+start_y; // _r[0] -> _r[2] to make it simultaneous with frame_number
if (mrst) line_unfinished_r[FRAME_HEIGHT_BITS +: FRAME_HEIGHT_BITS] <= 0; //{FRAME_HEIGHT_BITS{1'b0}};
else if (chn_rst || frame_start_r[2]) line_unfinished_r[FRAME_HEIGHT_BITS +: FRAME_HEIGHT_BITS] <= window_y0+start_y; // _r[0] -> _r[2] to make it simultaneous with frame_number
// in read mode advance line number ASAP
else if (xfer_start_r[2] && !cmd_wrmem) line_unfinished_r[1] <= window_y0+next_y[FRAME_HEIGHT_BITS-1:0]; // latency 2 from xfer_start
else if (xfer_start_r[2] && !cmd_wrmem) line_unfinished_r[FRAME_HEIGHT_BITS +: FRAME_HEIGHT_BITS] <= window_y0+next_y[FRAME_HEIGHT_BITS-1:0]; // latency 2 from xfer_start
// in write mode advance line number only when it is guaranteed it will be the first to actually access memory
else if (xfer_grant && cmd_wrmem) line_unfinished_r[1] <= line_unfinished_r[0];
else if (xfer_grant && cmd_wrmem) line_unfinished_r[FRAME_HEIGHT_BITS +: FRAME_HEIGHT_BITS] <= line_unfinished_r[0 +: FRAME_HEIGHT_BITS];
*/
/*
if (mrst) line_unfinished_relw_r <= 0;
else if (cmd_wrmem && (frame_start_r[1] || !chn_en)) line_unfinished_relw_r <= start_y;
else if ((!cmd_wrmem && recalc_r[1]) || xfer_start_r[2]) line_unfinished_relw_r <= next_y[FRAME_HEIGHT_BITS-1:0];
// xfer_start_r[2] and recalc_r[1] are at the same time
if (mrst || (frame_start || !chn_en)) line_unfinished_r <= {FRAME_HEIGHT_BITS{~cmd_wrmem}}; // lowest/highest value until valid
else if (recalc_r[2]) line_unfinished_r <= line_unfinished_relw_r + window_y0;
*/
if (recalc_r[0]) line_unfinished_relw_r <= curr_y + (cmd_wrmem ? 0: tile_rows);
if (mrst || (frame_start || !chn_en)) line_unfinished_r <= {FRAME_HEIGHT_BITS{~cmd_wrmem}}; // lowest/highest value until valid
else if (recalc_r[2]) line_unfinished_r <= line_unfinished_relw_r + window_y0;
end
always @ (negedge mclk) begin
......
sensor/lens_flat393.v
View file @ de641880
......@@ -253,13 +253,13 @@ module lens_flat393 #(
end
// Replacing MULT18X18SIO of x353, registers on both inputs, outputs
reg [17:0] mul1_a;
reg [17:0] mul1_b;
reg [35:0] mul1_p;
reg [17:0] mul2_a;
reg [17:0] mul2_b;
reg signed [17:0] mul1_a;
reg signed [17:0] mul1_b;
reg signed [35:0] mul1_p;
reg signed [17:0] mul2_a;
reg signed [17:0] mul2_b;
// wire [17:0] mul2_b = mult_first_scaled[17:0]; // TODO - delay to have a register!
reg [35:0] mul2_p;
reg signed [35:0] mul2_p;
always @ (posedge pclk) begin
if (hact_d[7]) mul1_a <= (FXY[18]==FXY[17])?FXY[17:0]:(FXY[18]?18'h20000:18'h1ffff);
if (hact_d[7]) mul1_b <= {1'b0,scales_ram[{sub_frame_late,~color[1:0]}]};
......
sensor/sens_gamma.v
View file @ de641880
......@@ -84,7 +84,7 @@ module sens_gamma #(
reg [3:0] set_tdata_ram;
reg [17:0] tdata;
// wire set_taddr_data_w;
reg [12:0] taddr; // to high bits - select channnel (in buffered mode), in nion-buffered - 1 bit less, only 10 bits each table
reg [12:0] taddr; // two high bits - select channnel (in buffered mode), in non-buffered - 1 bit less, only 10 bits each table
reg [SENS_GAMMA_MODE_WIDTH-1:0] mode=0;
reg [SENS_GAMMA_MODE_WIDTH-1:0] mode_mclk=0;
......@@ -336,6 +336,9 @@ module sens_gamma #(
.LOG2WIDTH_WR (4),
.LOG2WIDTH_RD (4),
.DUMMY (0)
`ifdef PRELOAD_BRAMS
`include "includes/linear1028rgb.dat.vh"
`endif
) gamma_table0_i (
.rclk (pclk), // input
.raddr (table_raddr), // input[11:0]
......@@ -354,6 +357,9 @@ module sens_gamma #(
.LOG2WIDTH_WR (4),
.LOG2WIDTH_RD (4),
.DUMMY (!((SENS_NUM_SUBCHN > 1) && ((SENS_NUM_SUBCHN > 2) || SENS_GAMMA_BUFFER)))
`ifdef PRELOAD_BRAMS
`include "includes/linear1028rgb.dat.vh"
`endif
) gamma_table1_i (
.rclk (pclk), // input
.raddr (table_raddr), // input[11:0]
......@@ -372,6 +378,9 @@ module sens_gamma #(
.LOG2WIDTH_WR (4),
.LOG2WIDTH_RD (4),
.DUMMY (!(SENS_GAMMA_BUFFER && (SENS_NUM_SUBCHN > 2)))
`ifdef PRELOAD_BRAMS
`include "includes/linear1028rgb.dat.vh"
`endif
) gamma_table2_i (
.rclk (pclk), // input
.raddr (table_raddr), // input[11:0]
......@@ -390,6 +399,9 @@ module sens_gamma #(
.LOG2WIDTH_WR (4),
.LOG2WIDTH_RD (4),
.DUMMY (!(SENS_GAMMA_BUFFER && (SENS_NUM_SUBCHN > 3)))
`ifdef PRELOAD_BRAMS
`include "includes/linear1028rgb.dat.vh"
`endif
) gamma_table3_i (
.rclk (pclk), // input
.raddr (table_raddr), // input[11:0]
......
system_defines.vh
View file @ de641880
// This file may be used to define same pre-processor macros to be included into each parsed file
`ifndef SYSTEM_DEFINES
`define SYSTEM_DEFINES
`define PRELOAD_BRAMS
// Enviroment-dependent options
`ifdef IVERILOG
`define SIMULATION
......
util_modules/multipulse_cross_clock.v
View file @ de641880
......@@ -41,12 +41,14 @@ module multipulse_cross_clock#(
wire single_rq_w;
reg single_rq_r=0;
assign busy = busy_single && (|pend_cntr);
assign single_rq_w = busy_single && (|pend_cntr);
// assign busy = busy_single && (|pend_cntr);
assign busy = busy_single || (|pend_cntr);
assign single_rq_w = !busy_single && (|pend_cntr);
always @(posedge src_clk) begin
single_rq_r <= single_rq_w;
pend_cntr <= pend_cntr + (we ? num_pulses : {WIDTH{1'b0}}) + (single_rq_r ? {WIDTH{1'b1}}:{WIDTH{1'b0}});
if (rst) pend_cntr <= 0;
else pend_cntr <= pend_cntr + (we ? num_pulses : {WIDTH{1'b0}}) + (single_rq_r ? {WIDTH{1'b1}}:{WIDTH{1'b0}});
end
pulse_cross_clock #(
......
wrap/ram18_var_w_var_r.v
View file @ de641880
......@@ -96,6 +96,9 @@ module ram18_var_w_var_r
input [ 3:0] web, // write byte enable
input [(1 << LOG2WIDTH_WR)-1:0] data_in // data out
);
`ifdef PRELOAD_BRAMS
`include "includes/ram18_declare_init.vh"
`endif
generate
if (DUMMY)
ram18_dummy #(
......@@ -106,6 +109,9 @@ module ram18_var_w_var_r
else if ((LOG2WIDTH_WR == 5) && (LOG2WIDTH_RD == 5))
ram18_32w_32r #(
.REGISTERS (REGISTERS)
`ifdef PRELOAD_BRAMS
`include "includes/ram18_pass_init.vh"
`endif
) ram_i (
.rclk (rclk), // input
.raddr (raddr), // input[8:0]
......@@ -122,6 +128,9 @@ module ram18_var_w_var_r
ram18_32w_lt32r #(
.REGISTERS (REGISTERS),
.LOG2WIDTH_RD (LOG2WIDTH_RD)
`ifdef PRELOAD_BRAMS
`include "includes/ram18_pass_init.vh"
`endif
) ram_i (
.rclk (rclk), // input
.raddr (raddr), // input[(>8):0]
......@@ -138,6 +147,9 @@ module ram18_var_w_var_r
ram18_lt32w_32r #(
.REGISTERS (REGISTERS),
.LOG2WIDTH_WR (LOG2WIDTH_WR)
`ifdef PRELOAD_BRAMS
`include "includes/ram18_pass_init.vh"
`endif
) ram_i (
.rclk (rclk), // input
.raddr (raddr), // input[8:0]
......@@ -155,6 +167,9 @@ module ram18_var_w_var_r
.REGISTERS (REGISTERS),
.LOG2WIDTH_WR (LOG2WIDTH_WR),
.LOG2WIDTH_RD (LOG2WIDTH_RD)
`ifdef PRELOAD_BRAMS
`include "includes/ram18_pass_init.vh"
`endif
) ram_i (
.rclk (rclk), // input
.raddr (raddr), // input[(>8):0]
......@@ -189,6 +204,9 @@ module ram18_32w_32r
input [ 3:0] web, // write byte enable
input [31:0] data_in // data out
);
`ifdef PRELOAD_BRAMS
`include "includes/ram18_declare_init.vh"
`endif
localparam PWIDTH_WR=36;
localparam PWIDTH_RD=36;
......@@ -209,6 +227,9 @@ module ram18_32w_32r
.SIM_COLLISION_CHECK ("ALL"), // Valid: "ALL", "GENERATE_X_ONLY", "NONE", and "WARNING_ONLY"
.INIT_FILE ("NONE"), // "NONE" or filename with initialization data
.SIM_DEVICE ("7SERIES") // Simulation device family - "VIRTEX6", "VIRTEX5" and "7_SERIES" // "7SERIES"
`ifdef PRELOAD_BRAMS
`include "includes/ram18_pass_init.vh"
`endif
) RAMB36E1_i
(
// Port A (Read port in SDP mode):
......@@ -260,6 +281,9 @@ module ram18_lt32w_lt32r
input [ 3:0] web, // write byte enable
input [(1 << LOG2WIDTH_WR)-1:0] data_in // data out
);
`ifdef PRELOAD_BRAMS
`include "includes/ram18_declare_init.vh"
`endif
localparam PWIDTH_WR = (LOG2WIDTH_WR > 2)? (9 << (LOG2WIDTH_WR - 3)): (1 << LOG2WIDTH_WR);
localparam PWIDTH_RD = (LOG2WIDTH_RD > 2)? (9 << (LOG2WIDTH_RD - 3)): (1 << LOG2WIDTH_RD);
localparam WIDTH_WR = 1 << LOG2WIDTH_WR;
......@@ -288,7 +312,9 @@ module ram18_lt32w_lt32r
.SIM_COLLISION_CHECK ("ALL"), // Valid: "ALL", "GENERATE_X_ONLY", "NONE", and "WARNING_ONLY"
.INIT_FILE ("NONE"), // "NONE" or filename with initialization data
.SIM_DEVICE ("7SERIES") // Simulation device family - "VIRTEX6", "VIRTEX5" and "7_SERIES" // "7SERIES"
`ifdef PRELOAD_BRAMS
`include "includes/ram18_pass_init.vh"
`endif
) RAMB36E1_i
(
// Port A (Read port in SDP mode):
......@@ -338,6 +364,9 @@ module ram18_lt32w_32r
input [ 3:0] web, // write byte enable
input [(1 << LOG2WIDTH_WR)-1:0] data_in // data out
);
`ifdef PRELOAD_BRAMS
`include "includes/ram18_declare_init.vh"
`endif
localparam PWIDTH_WR = (LOG2WIDTH_WR > 2)? (9 << (LOG2WIDTH_WR - 3)): (1 << LOG2WIDTH_WR);
localparam PWIDTH_RD = 36;
localparam WIDTH_WR = 1 << LOG2WIDTH_WR;
......@@ -362,6 +391,9 @@ module ram18_lt32w_32r
.SIM_COLLISION_CHECK ("ALL"), // Valid: "ALL", "GENERATE_X_ONLY", "NONE", and "WARNING_ONLY"
.INIT_FILE ("NONE"), // "NONE" or filename with initialization data
.SIM_DEVICE ("7SERIES") // Simulation device family - "VIRTEX6", "VIRTEX5" and "7_SERIES" // "7SERIES"
`ifdef PRELOAD_BRAMS
`include "includes/ram18_pass_init.vh"
`endif
) RAMB36E1_i
(
// Port A (Read port in SDP mode):
......@@ -412,6 +444,9 @@ module ram18_32w_lt32r
input [ 3:0] web, // write byte enable
input [31:0] data_in // data out
);
`ifdef PRELOAD_BRAMS
`include "includes/ram18_declare_init.vh"
`endif
localparam PWIDTH_WR = 36;
localparam PWIDTH_RD = (LOG2WIDTH_RD > 2)? (9 << (LOG2WIDTH_RD - 3)): (1 << LOG2WIDTH_RD);
localparam WIDTH_RD = 1 << LOG2WIDTH_RD;
......@@ -434,6 +469,9 @@ module ram18_32w_lt32r
.SIM_COLLISION_CHECK ("ALL"), // Valid: "ALL", "GENERATE_X_ONLY", "NONE", and "WARNING_ONLY"
.INIT_FILE ("NONE"), // "NONE" or filename with initialization data
.SIM_DEVICE ("7SERIES") // Simulation device family - "VIRTEX6", "VIRTEX5" and "7_SERIES" // "7SERIES"
`ifdef PRELOAD_BRAMS
`include "includes/ram18_pass_init.vh"
`endif
) RAMB36E1_i
(
// Port A (Read port in SDP mode):
......
wrap/ram18p_var_w_var_r.v
View file @ de641880
......@@ -92,6 +92,9 @@ module ram18p_var_w_var_r
input [ 3:0] web, // write byte enable
input [(9 << (LOG2WIDTH_WR-3))-1:0] data_in // data out
);
`ifdef PRELOAD_BRAMS
`include "includes/ram18_declare_init.vh"
`endif
generate
if (DUMMY)
ram18p_dummy #(
......@@ -102,6 +105,9 @@ module ram18p_var_w_var_r
else if ((LOG2WIDTH_WR == 5) && (LOG2WIDTH_RD == 5))
ram18p_32w_32r #(
.REGISTERS (REGISTERS)
`ifdef PRELOAD_BRAMS
`include "includes/ram18_pass_init.vh"
`endif
) ram_i (
.rclk (rclk), // input
.raddr (raddr), // input[8:0]
......@@ -118,6 +124,9 @@ module ram18p_var_w_var_r
ram18p_32w_lt32r #(
.REGISTERS (REGISTERS),
.LOG2WIDTH_RD (LOG2WIDTH_RD)
`ifdef PRELOAD_BRAMS
`include "includes/ram18_pass_init.vh"
`endif
) ram_i (
.rclk (rclk), // input
.raddr (raddr), // input[(>8):0]
......@@ -134,6 +143,9 @@ module ram18p_var_w_var_r
ram18p_lt32w_32r #(
.REGISTERS (REGISTERS),
.LOG2WIDTH_WR (LOG2WIDTH_WR)
`ifdef PRELOAD_BRAMS
`include "includes/ram18_pass_init.vh"
`endif
) ram_i (
.rclk (rclk), // input
.raddr (raddr), // input[8:0]
......@@ -151,6 +163,9 @@ module ram18p_var_w_var_r
.REGISTERS (REGISTERS),
.LOG2WIDTH_WR (LOG2WIDTH_WR),
.LOG2WIDTH_RD (LOG2WIDTH_RD)
`ifdef PRELOAD_BRAMS
`include "includes/ram18_pass_init.vh"
`endif
) ram_i (
.rclk (rclk), // input
.raddr (raddr), // input[(>8):0]
......@@ -185,6 +200,9 @@ module ram18p_32w_32r
input [ 3:0] web, // write byte enable
input [35:0] data_in // data out
);
`ifdef PRELOAD_BRAMS
`include "includes/ram18_declare_init.vh"
`endif
localparam PWIDTH_WR=72;
localparam PWIDTH_RD=72;
......@@ -205,6 +223,9 @@ module ram18p_32w_32r
.SIM_COLLISION_CHECK ("ALL"), // Valid: "ALL", "GENERATE_X_ONLY", "NONE", and "WARNING_ONLY"
.INIT_FILE ("NONE"), // "NONE" or filename with initialization data
.SIM_DEVICE ("7SERIES") // Simulation device family - "VIRTEX6", "VIRTEX5" and "7_SERIES" // "7SERIES"
`ifdef PRELOAD_BRAMS
`include "includes/ram18_pass_init.vh"
`endif
) RAMB36E1_i
(
// Port A (Read port in SDP mode):
......@@ -256,6 +277,9 @@ module ram18p_lt32w_lt32r
input [ 3:0] web, // write byte enable
input [(9 << (LOG2WIDTH_WR-3))-1:0] data_in // data out
);
`ifdef PRELOAD_BRAMS
`include "includes/ram18_declare_init.vh"
`endif
localparam PWIDTH_WR = (LOG2WIDTH_WR > 2)? (9 << (LOG2WIDTH_WR - 3)): (1 << LOG2WIDTH_WR);
localparam PWIDTH_RD = (LOG2WIDTH_RD > 2)? (9 << (LOG2WIDTH_RD - 3)): (1 << LOG2WIDTH_RD);
localparam WIDTH_WR = 1 << LOG2WIDTH_WR;
......@@ -289,7 +313,9 @@ module ram18p_lt32w_lt32r
.SIM_COLLISION_CHECK ("ALL"), // Valid: "ALL", "GENERATE_X_ONLY", "NONE", and "WARNING_ONLY"
.INIT_FILE ("NONE"), // "NONE" or filename with initialization data
.SIM_DEVICE ("7SERIES") // Simulation device family - "VIRTEX6", "VIRTEX5" and "7_SERIES" // "7SERIES"
`ifdef PRELOAD_BRAMS
`include "includes/ram18_pass_init.vh"
`endif
) RAMB36E1_i
(
// Port A (Read port in SDP mode):
......@@ -339,6 +365,10 @@ module ram18p_lt32w_32r
input [ 3:0] web, // write byte enable
input [(9 << (LOG2WIDTH_WR-3))-1:0] data_in // data out
);
`ifdef PRELOAD_BRAMS
`include "includes/ram18_declare_init.vh"
`endif
localparam PWIDTH_WR = (LOG2WIDTH_WR > 2)? (9 << (LOG2WIDTH_WR - 3)): (1 << LOG2WIDTH_WR);
localparam PWIDTH_RD = 36;
localparam WIDTH_WR = 1 << LOG2WIDTH_WR;
......@@ -367,6 +397,9 @@ module ram18p_lt32w_32r
.SIM_COLLISION_CHECK ("ALL"), // Valid: "ALL", "GENERATE_X_ONLY", "NONE", and "WARNING_ONLY"
.INIT_FILE ("NONE"), // "NONE" or filename with initialization data
.SIM_DEVICE ("7SERIES") // Simulation device family - "VIRTEX6", "VIRTEX5" and "7_SERIES" // "7SERIES"
`ifdef PRELOAD_BRAMS
`include "includes/ram18_pass_init.vh"
`endif
) RAMB36E1_i
(
// Port A (Read port in SDP mode):
......@@ -417,6 +450,9 @@ module ram18p_32w_lt32r
input [ 3:0] web, // write byte enable
input [35:0] data_in // data out
);
`ifdef PRELOAD_BRAMS
`include "includes/ram18_declare_init.vh"
`endif
localparam PWIDTH_WR = 72;
localparam PWIDTH_RD = (LOG2WIDTH_RD > 2)? (9 << (LOG2WIDTH_RD - 3)): (1 << LOG2WIDTH_RD);
localparam WIDTH_RD = 1 << LOG2WIDTH_RD;
......@@ -441,6 +477,9 @@ module ram18p_32w_lt32r
.SIM_COLLISION_CHECK ("ALL"), // Valid: "ALL", "GENERATE_X_ONLY", "NONE", and "WARNING_ONLY"
.INIT_FILE ("NONE"), // "NONE" or filename with initialization data
.SIM_DEVICE ("7SERIES") // Simulation device family - "VIRTEX6", "VIRTEX5" and "7_SERIES" // "7SERIES"
`ifdef PRELOAD_BRAMS
`include "includes/ram18_pass_init.vh"
`endif
) RAMB36E1_i
(
// Port A (Read port in SDP mode):
......
wrap/ramp_var_w_var_r.v
View file @ de641880
......@@ -92,6 +92,10 @@ module ramp_var_w_var_r
input [ 7:0] web, // write byte enable
input [(9 << (LOG2WIDTH_WR-3))-1:0] data_in // data out
);
`ifdef PRELOAD_BRAMS
`include "includes/ram36_declare_init.vh"
`endif
generate
if (DUMMY)
ramp_dummy #(
......@@ -102,6 +106,9 @@ module ramp_var_w_var_r
else if ((LOG2WIDTH_WR == 6) && (LOG2WIDTH_RD == 6))
ramp_64w_64r #(
.REGISTERS (REGISTERS)
`ifdef PRELOAD_BRAMS
`include "includes/ram36_pass_init.vh"
`endif
) ram_i (
.rclk (rclk), // input
.raddr (raddr), // input[8:0]
......@@ -118,6 +125,9 @@ module ramp_var_w_var_r
ramp_64w_lt64r #(
.REGISTERS (REGISTERS),
.LOG2WIDTH_RD (LOG2WIDTH_RD)
`ifdef PRELOAD_BRAMS
`include "includes/ram36_pass_init.vh"
`endif
) ram_i (
.rclk (rclk), // input
.raddr (raddr), // input[(>8):0]
......@@ -134,6 +144,9 @@ module ramp_var_w_var_r
ramp_lt64w_64r #(
.REGISTERS (REGISTERS),
.LOG2WIDTH_WR (LOG2WIDTH_WR)
`ifdef PRELOAD_BRAMS
`include "includes/ram36_pass_init.vh"
`endif
) ram_i (
.rclk (rclk), // input
.raddr (raddr), // input[8:0]
......@@ -151,6 +164,9 @@ module ramp_var_w_var_r
.REGISTERS (REGISTERS),
.LOG2WIDTH_WR (LOG2WIDTH_WR),
.LOG2WIDTH_RD (LOG2WIDTH_RD)
`ifdef PRELOAD_BRAMS
`include "includes/ram36_pass_init.vh"
`endif
) ram_i (
.rclk (rclk), // input
.raddr (raddr), // input[(>8):0]
......@@ -184,6 +200,10 @@ module ramp_64w_64r
input [ 7:0] web, // write byte enable
input [71:0] data_in // data out
);
`ifdef PRELOAD_BRAMS
`include "includes/ram36_declare_init.vh"
`endif
localparam PWIDTH_WR=72;
localparam PWIDTH_RD=72;
......@@ -208,6 +228,9 @@ module ramp_64w_64r
.SIM_DEVICE ("7SERIES"), // Simulation device family - "VIRTEX6", "VIRTEX5" and "7_SERIES" // "7SERIES"
.EN_ECC_READ ("FALSE"), // Valid:"FALSE","TRUE" (ECC decoder circuitry)
.EN_ECC_WRITE ("FALSE") // Valid:"FALSE","TRUE" (ECC decoder circuitry)
`ifdef PRELOAD_BRAMS
`include "includes/ram36_pass_init.vh"
`endif
) RAMB36E1_i
(
// Port A (Read port in SDP mode):
......@@ -272,6 +295,10 @@ module ramp_lt64w_lt64r
input [ 7:0] web, // write byte enable
input [(9 << (LOG2WIDTH_WR-3))-1:0] data_in // data out
);
`ifdef PRELOAD_BRAMS
`include "includes/ram36_declare_init.vh"
`endif
localparam PWIDTH_WR = (LOG2WIDTH_WR > 2)? (9 << (LOG2WIDTH_WR - 3)): (1 << LOG2WIDTH_WR);
localparam PWIDTH_RD = (LOG2WIDTH_RD > 2)? (9 << (LOG2WIDTH_RD - 3)): (1 << LOG2WIDTH_RD);
localparam WIDTH_WR = 1 << LOG2WIDTH_WR;
......@@ -324,6 +351,9 @@ module ramp_lt64w_lt64r
parameter IS_RSTREGARSTREG_INVERTED = 1'b0;
parameter IS_RSTREGB_INVERTED = 1'b0;
*/
`ifdef PRELOAD_BRAMS
`include "includes/ram36_pass_init.vh"
`endif
) RAMB36E1_i
(
......@@ -387,6 +417,9 @@ module ramp_lt64w_64r
input [ 7:0] web, // write byte enable
input [(9 << (LOG2WIDTH_WR-3))-1:0] data_in // data out
);
`ifdef PRELOAD_BRAMS
`include "includes/ram36_declare_init.vh"
`endif
localparam PWIDTH_WR = (LOG2WIDTH_WR > 2)? (9 << (LOG2WIDTH_WR - 3)): (1 << LOG2WIDTH_WR);
localparam PWIDTH_RD = 72;
localparam WIDTH_WR = 1 << LOG2WIDTH_WR;
......@@ -420,6 +453,9 @@ module ramp_lt64w_64r
.EN_ECC_READ ("FALSE"), // Valid:"FALSE","TRUE" (ECC decoder circuitry)
.EN_ECC_WRITE ("FALSE") // Valid:"FALSE","TRUE" (ECC decoder circuitry)
`ifdef PRELOAD_BRAMS
`include "includes/ram36_pass_init.vh"
`endif
) RAMB36E1_i
(
// Port A (Read port in SDP mode):
......@@ -482,6 +518,9 @@ module ramp_64w_lt64r
input [ 7:0] web, // write byte enable
input [71:0] data_in // data out
);
`ifdef PRELOAD_BRAMS
`include "includes/ram36_declare_init.vh"
`endif
localparam PWIDTH_WR = 72;
localparam PWIDTH_RD = (LOG2WIDTH_RD > 2)? (9 << (LOG2WIDTH_RD - 3)): (1 << LOG2WIDTH_RD);
localparam WIDTH_RD = 1 << LOG2WIDTH_RD;
......@@ -511,6 +550,10 @@ module ramp_64w_lt64r
.EN_ECC_READ ("FALSE"), // Valid:"FALSE","TRUE" (ECC decoder circuitry)
.EN_ECC_WRITE ("FALSE") // Valid:"FALSE","TRUE" (ECC decoder circuitry)
`ifdef PRELOAD_BRAMS
`include "includes/ram36_pass_init.vh"
`endif
) RAMB36E1_i
(
// Port A (Read port in SDP mode):
......
wrap/ramt_var_w_var_r.v
View file @ de641880
......@@ -102,7 +102,9 @@ module ramt_var_w_var_r
output [(1 << LOG2WIDTH_B)-1:0] data_out_b,// data out port B
input [(1 << LOG2WIDTH_B)-1:0] data_in_b // data in port B
);
`ifdef PRELOAD_BRAMS
`include "includes/ram36_declare_init.vh"
`endif
localparam PWIDTH_A = (LOG2WIDTH_A > 2)? (9 << (LOG2WIDTH_A - 3)): (1 << LOG2WIDTH_A);
localparam PWIDTH_B = (LOG2WIDTH_B > 2)? (9 << (LOG2WIDTH_B - 3)): (1 << LOG2WIDTH_B);
localparam WIDTH_A = 1 << LOG2WIDTH_A;
......@@ -143,20 +145,9 @@ module ramt_var_w_var_r
.EN_ECC_READ ("FALSE"), // Valid:"FALSE","TRUE" (ECC decoder circuitry)
.EN_ECC_WRITE ("FALSE") // Valid:"FALSE","TRUE" (ECC decoder circuitry)
// .INIT_A(36'h0), // Output latches initialization data
// .INIT_B(36'h0), // Output latches initialization data
// .SRVAL_A(36'h0), // Output latches initialization data (copied at when RSTRAM/RSTREG activated)
// .SRVAL_B(36'h0) // Output latches initialization data (copied at when RSTRAM/RSTREG activated)
/*
parameter IS_CLKARDCLK_INVERTED = 1'b0;
parameter IS_CLKBWRCLK_INVERTED = 1'b0;
parameter IS_ENARDEN_INVERTED = 1'b0;
parameter IS_ENBWREN_INVERTED = 1'b0;
parameter IS_RSTRAMARSTRAM_INVERTED = 1'b0;
parameter IS_RSTRAMB_INVERTED = 1'b0;
parameter IS_RSTREGARSTREG_INVERTED = 1'b0;
parameter IS_RSTREGB_INVERTED = 1'b0;
*/
`ifdef PRELOAD_BRAMS
`include "includes/ram36_pass_init.vh"
`endif
) RAMB36E1_i
(
......
wrap/ramtp_var_w_var_r.v
View file @ de641880
......@@ -102,7 +102,9 @@ module ramtp_var_w_var_r
output [(9 << (LOG2WIDTH_B-3))-1:0] data_out_b,// data out port B
input [(9 << (LOG2WIDTH_B-3))-1:0] data_in_b // data in port B
);
`ifdef PRELOAD_BRAMS
`include "includes/ram36_declare_init.vh"
`endif
localparam PWIDTH_A = (LOG2WIDTH_A > 2)? (9 << (LOG2WIDTH_A - 3)): (1 << LOG2WIDTH_A);
localparam PWIDTH_B = (LOG2WIDTH_B > 2)? (9 << (LOG2WIDTH_B - 3)): (1 << LOG2WIDTH_B);
localparam WIDTH_A = 1 << LOG2WIDTH_A;
......@@ -151,21 +153,9 @@ module ramtp_var_w_var_r
.EN_ECC_READ ("FALSE"), // Valid:"FALSE","TRUE" (ECC decoder circuitry)
.EN_ECC_WRITE ("FALSE") // Valid:"FALSE","TRUE" (ECC decoder circuitry)
// .INIT_A(36'h0), // Output latches initialization data
// .INIT_B(36'h0), // Output latches initialization data
// .SRVAL_A(36'h0), // Output latches initialization data (copied at when RSTRAM/RSTREG activated)
// .SRVAL_B(36'h0) // Output latches initialization data (copied at when RSTRAM/RSTREG activated)
/*
parameter IS_CLKARDCLK_INVERTED = 1'b0;
parameter IS_CLKBWRCLK_INVERTED = 1'b0;
parameter IS_ENARDEN_INVERTED = 1'b0;
parameter IS_ENBWREN_INVERTED = 1'b0;
parameter IS_RSTRAMARSTRAM_INVERTED = 1'b0;
parameter IS_RSTRAMB_INVERTED = 1'b0;
parameter IS_RSTREGARSTREG_INVERTED = 1'b0;
parameter IS_RSTREGB_INVERTED = 1'b0;
*/
`ifdef PRELOAD_BRAMS
`include "includes/ram36_pass_init.vh"
`endif
) RAMB36E1_i
(
// Port A (Read port in SDP mode):
......
x393_testbench02.tf
View file @ de641880
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