Loading axi/cmprs_afi_mux.v +1 −1 Original line number Diff line number Diff line Loading @@ -45,7 +45,7 @@ each group of 4 bits per channel : bits [1:0] - select, bit[2] - sset (0 - nop), */ parameter CMPRS_AFIMUX_SA_LEN= 'h8, // .. 'hf /* 27-bit "chunk" addresses and lengths. 1 chunk = 32 bytes, so 27 bit covers all 2^32 adderss range 27-bit "chunk" addresses and lengths. 1 chunk = 32 bytes, so 27 bit covers all 2^32 address range 8 .. 11 - per-channel start adddresses, 12 .. 15 - per-channel buffer lengths (will roll over to start address) (0..3 - start addresses, 4..7 - lengths) Loading axi/mult_saxi_wr.v +2 −2 Original line number Diff line number Diff line Loading @@ -127,7 +127,7 @@ module mult_saxi_wr #( wire [127:0] data_in; wire [3:0] pre_valid; reg [3:0] valid; reg [BRAM_A_WDTH-1:0] buf_wa; // multiplexed buffer write adderss reg [BRAM_A_WDTH-1:0] buf_wa; // multiplexed buffer write address reg [31:0] buf_wd; // multiplexed buffer write data reg buf_we; // multiplexed buffer write enable Loading @@ -136,7 +136,7 @@ module mult_saxi_wr #( wire en_out_arb; wire [1:0] re_cur_chn; reg [BRAM_A_WDTH-1:0] buf_ra; // multiplexed buffer write adderss reg [BRAM_A_WDTH-1:0] buf_ra; // multiplexed buffer write address wire [31:0] inter_buf_data; // multiplexed buffer write data reg [2:0] buf_re; // multiplexed buffer write enable Loading compressor_jp/jp_channel.v +1 −1 Original line number Diff line number Diff line Loading @@ -228,7 +228,7 @@ module jp_channel#( // wire [11:0] buf_ra; // buffer read address (2 MSB - page number) wire [ 1:0] buf_rd; // buf {regen, re} wire [ 7:0] buf_pxd; // 8-bit pixel data from the memory buffer wire [11:0] buf_ra; // Memory buffer read adderss wire [11:0] buf_ra; // Memory buffer read address // signals connecting modules: chn_rd_buf_i and ???: wire [ 7:0] mb_data_out; // Macroblock data out in scanline order wire mb_pre_first_out; // Macroblock data out strobe - 1 cycle just before data valid Loading helpers/convert_data_to_params.py +2 −2 Original line number Diff line number Diff line Loading @@ -85,8 +85,8 @@ def print_params(data,out_file_name): print (", .INITP_%02X (256'h%064X)"%(i,v), file=out_file) #print ('Number of arguments: %d'%(len(sys.argv))) #print ('Argument List:%s'%(str(sys.argv))) with open(sys.argv[1]) as file: tokens=file.read().split() with open(sys.argv[1]) as f: tokens=f.read().split() # print(lines) #print (lines.split()) values=[] Loading includes/x393_parameters.vh +1 −1 Original line number Diff line number Diff line Loading @@ -630,7 +630,7 @@ parameter RTC_ADDR= 'h704, // 'h707 parameter CAMSYNC_ADDR = 'h708, // 'h70f parameter RTC_STATUS_REG_ADDR = 'h31, // (1 loc) address where status can be read out (currently just sequence # and alternating bit) parameter RTC_SEC_USEC_ADDR = 'h32, // ..'h33 address where seconds of the snapshot can be read (microseconds - next adderss) parameter RTC_SEC_USEC_ADDR = 'h32, // ..'h33 address where seconds of the snapshot can be read (microseconds - next address) parameter RTC_MASK = 'h7fc, parameter CAMSYNC_MASK = 'h7f8, parameter CAMSYNC_MODE = 'h0, Loading Loading
axi/cmprs_afi_mux.v +1 −1 Original line number Diff line number Diff line Loading @@ -45,7 +45,7 @@ each group of 4 bits per channel : bits [1:0] - select, bit[2] - sset (0 - nop), */ parameter CMPRS_AFIMUX_SA_LEN= 'h8, // .. 'hf /* 27-bit "chunk" addresses and lengths. 1 chunk = 32 bytes, so 27 bit covers all 2^32 adderss range 27-bit "chunk" addresses and lengths. 1 chunk = 32 bytes, so 27 bit covers all 2^32 address range 8 .. 11 - per-channel start adddresses, 12 .. 15 - per-channel buffer lengths (will roll over to start address) (0..3 - start addresses, 4..7 - lengths) Loading
axi/mult_saxi_wr.v +2 −2 Original line number Diff line number Diff line Loading @@ -127,7 +127,7 @@ module mult_saxi_wr #( wire [127:0] data_in; wire [3:0] pre_valid; reg [3:0] valid; reg [BRAM_A_WDTH-1:0] buf_wa; // multiplexed buffer write adderss reg [BRAM_A_WDTH-1:0] buf_wa; // multiplexed buffer write address reg [31:0] buf_wd; // multiplexed buffer write data reg buf_we; // multiplexed buffer write enable Loading @@ -136,7 +136,7 @@ module mult_saxi_wr #( wire en_out_arb; wire [1:0] re_cur_chn; reg [BRAM_A_WDTH-1:0] buf_ra; // multiplexed buffer write adderss reg [BRAM_A_WDTH-1:0] buf_ra; // multiplexed buffer write address wire [31:0] inter_buf_data; // multiplexed buffer write data reg [2:0] buf_re; // multiplexed buffer write enable Loading
compressor_jp/jp_channel.v +1 −1 Original line number Diff line number Diff line Loading @@ -228,7 +228,7 @@ module jp_channel#( // wire [11:0] buf_ra; // buffer read address (2 MSB - page number) wire [ 1:0] buf_rd; // buf {regen, re} wire [ 7:0] buf_pxd; // 8-bit pixel data from the memory buffer wire [11:0] buf_ra; // Memory buffer read adderss wire [11:0] buf_ra; // Memory buffer read address // signals connecting modules: chn_rd_buf_i and ???: wire [ 7:0] mb_data_out; // Macroblock data out in scanline order wire mb_pre_first_out; // Macroblock data out strobe - 1 cycle just before data valid Loading
helpers/convert_data_to_params.py +2 −2 Original line number Diff line number Diff line Loading @@ -85,8 +85,8 @@ def print_params(data,out_file_name): print (", .INITP_%02X (256'h%064X)"%(i,v), file=out_file) #print ('Number of arguments: %d'%(len(sys.argv))) #print ('Argument List:%s'%(str(sys.argv))) with open(sys.argv[1]) as file: tokens=file.read().split() with open(sys.argv[1]) as f: tokens=f.read().split() # print(lines) #print (lines.split()) values=[] Loading
includes/x393_parameters.vh +1 −1 Original line number Diff line number Diff line Loading @@ -630,7 +630,7 @@ parameter RTC_ADDR= 'h704, // 'h707 parameter CAMSYNC_ADDR = 'h708, // 'h70f parameter RTC_STATUS_REG_ADDR = 'h31, // (1 loc) address where status can be read out (currently just sequence # and alternating bit) parameter RTC_SEC_USEC_ADDR = 'h32, // ..'h33 address where seconds of the snapshot can be read (microseconds - next adderss) parameter RTC_SEC_USEC_ADDR = 'h32, // ..'h33 address where seconds of the snapshot can be read (microseconds - next address) parameter RTC_MASK = 'h7fc, parameter CAMSYNC_MASK = 'h7f8, parameter CAMSYNC_MODE = 'h0, Loading