Skip to content

X
x393
Commit d9f09d9d authored by Andrey Filippov's avatar Andrey Filippov
Browse files
Options

added more Python modules to control hardware, some bug fixes

parent b13c86d4
Expand all Show whitespace changes
Inline Side-by-side
Showing with 879 additions and 133 deletions
axi/cmprs_afi_mux.v
View file @ d9f09d9d
......@@ -45,7 +45,7 @@ each group of 4 bits per channel : bits [1:0] - select, bit[2] - sset (0 - nop),
*/
parameter CMPRS_AFIMUX_SA_LEN= 'h8, // .. 'hf
/*
27-bit "chunk" addresses and lengths. 1 chunk = 32 bytes, so 27 bit covers all 2^32 adderss range
27-bit "chunk" addresses and lengths. 1 chunk = 32 bytes, so 27 bit covers all 2^32 address range
8 .. 11 - per-channel start adddresses,
12 .. 15 - per-channel buffer lengths (will roll over to start address)
(0..3 - start addresses, 4..7 - lengths)
......
axi/mult_saxi_wr.v
View file @ d9f09d9d
......@@ -127,7 +127,7 @@ module mult_saxi_wr #(
wire [127:0] data_in;
wire [3:0] pre_valid;
reg [3:0] valid;
reg [BRAM_A_WDTH-1:0] buf_wa; // multiplexed buffer write adderss
reg [BRAM_A_WDTH-1:0] buf_wa; // multiplexed buffer write address
reg [31:0] buf_wd; // multiplexed buffer write data
reg buf_we; // multiplexed buffer write enable
......@@ -136,7 +136,7 @@ module mult_saxi_wr #(
wire en_out_arb;
wire [1:0] re_cur_chn;
reg [BRAM_A_WDTH-1:0] buf_ra; // multiplexed buffer write adderss
reg [BRAM_A_WDTH-1:0] buf_ra; // multiplexed buffer write address
wire [31:0] inter_buf_data; // multiplexed buffer write data
reg [2:0] buf_re; // multiplexed buffer write enable
......
compressor_jp/jp_channel.v
View file @ d9f09d9d
......@@ -228,7 +228,7 @@ module jp_channel#(
// wire [11:0] buf_ra; // buffer read address (2 MSB - page number)
wire [ 1:0] buf_rd; // buf {regen, re}
wire [ 7:0] buf_pxd; // 8-bit pixel data from the memory buffer
wire [11:0] buf_ra; // Memory buffer read adderss
wire [11:0] buf_ra; // Memory buffer read address
// signals connecting modules: chn_rd_buf_i and ???:
wire [ 7:0] mb_data_out; // Macroblock data out in scanline order
wire mb_pre_first_out; // Macroblock data out strobe - 1 cycle just before data valid
......
helpers/convert_data_to_params.py
View file @ d9f09d9d
......@@ -85,8 +85,8 @@ def print_params(data,out_file_name):
print (", .INITP_%02X (256'h%064X)"%(i,v), file=out_file)
#print ('Number of arguments: %d'%(len(sys.argv)))
#print ('Argument List:%s'%(str(sys.argv)))
with open(sys.argv[1]) as file:
tokens=file.read().split()
with open(sys.argv[1]) as f:
tokens=f.read().split()
# print(lines)
#print (lines.split())
values=[]
......
includes/x393_parameters.vh
View file @ d9f09d9d
......@@ -630,7 +630,7 @@
parameter RTC_ADDR= 'h704, // 'h707
parameter CAMSYNC_ADDR = 'h708, // 'h70f
parameter RTC_STATUS_REG_ADDR = 'h31, // (1 loc) address where status can be read out (currently just sequence # and alternating bit)
parameter RTC_SEC_USEC_ADDR = 'h32, // ..'h33 address where seconds of the snapshot can be read (microseconds - next adderss)
parameter RTC_SEC_USEC_ADDR = 'h32, // ..'h33 address where seconds of the snapshot can be read (microseconds - next address)
parameter RTC_MASK = 'h7fc,
parameter CAMSYNC_MASK = 'h7f8,
parameter CAMSYNC_MODE = 'h0,
......
py393/test_mcntrl.py
View file @ d9f09d9d
......@@ -62,7 +62,8 @@ import x393_camsync
import x393_gpio
import x393_cmprs_afi
import x393_cmprs
import x393_frame_sequencer
import x393_sensor
import vrlg
__all__ = []
__version__ = 0.1
......@@ -328,21 +329,23 @@ USAGE
print("vrlg.VERBOSE__TYPE="+str(vrlg.VERBOSE__TYPE))
print("vrlg.VERBOSE__RAW="+str(vrlg.VERBOSE__RAW))
x393mem= x393_mem.X393Mem(verbose,args.simulated) #add dry run parameter
x393utils= x393_utils.X393Utils(verbose,args.simulated,args.localparams)
x393tasks= x393_axi_control_status.X393AxiControlStatus(verbose,args.simulated)
x393Pio= x393_pio_sequences.X393PIOSequences(verbose,args.simulated)
x393Timing= x393_mcntrl_timing.X393McntrlTiming(verbose,args.simulated)
x393Buffers= x393_mcntrl_buffers.X393McntrlBuffers(verbose,args.simulated)
x393Tests= x393_mcntrl_tests.X393McntrlTests(verbose,args.simulated)
x393Eyepatterns= x393_mcntrl_eyepatterns.X393McntrlEyepattern(verbose,args.simulated)
x393Adjust= x393_mcntrl_adjust.X393McntrlAdjust(verbose,args.simulated,args.localparams)
X393Membridge= x393_mcntrl_membridge.X393McntrlMembridge(verbose,args.simulated)
x393SensCmprs= x393_sens_cmprs.X393SensCmprs(verbose,args.simulated,args.localparams)
x393Camsync= x393_camsync.X393Camsync(verbose,args.simulated,args.localparams)
x393GPIO= x393_gpio.X393GPIO(verbose,args.simulated,args.localparams)
x393CmprsAfi= x393_cmprs_afi.X393CmprsAfi(verbose,args.simulated,args.localparams)
x393Cmprs= x393_cmprs.X393Cmprs(verbose,args.simulated,args.localparams)
x393mem = x393_mem.X393Mem(verbose,args.simulated) #add dry run parameter
x393utils = x393_utils.X393Utils(verbose,args.simulated,args.localparams)
x393tasks = x393_axi_control_status.X393AxiControlStatus(verbose,args.simulated)
x393Pio = x393_pio_sequences.X393PIOSequences(verbose,args.simulated)
x393Timing = x393_mcntrl_timing.X393McntrlTiming(verbose,args.simulated)
x393Buffers = x393_mcntrl_buffers.X393McntrlBuffers(verbose,args.simulated)
x393Tests = x393_mcntrl_tests.X393McntrlTests(verbose,args.simulated)
x393Eyepatterns = x393_mcntrl_eyepatterns.X393McntrlEyepattern(verbose,args.simulated)
x393Adjust = x393_mcntrl_adjust.X393McntrlAdjust(verbose,args.simulated,args.localparams)
X393Membridge = x393_mcntrl_membridge.X393McntrlMembridge(verbose,args.simulated)
x393SensCmprs = x393_sens_cmprs.X393SensCmprs(verbose,args.simulated,args.localparams)
x393Camsync = x393_camsync.X393Camsync(verbose,args.simulated,args.localparams)
x393GPIO = x393_gpio.X393GPIO(verbose,args.simulated,args.localparams)
x393CmprsAfi = x393_cmprs_afi.X393CmprsAfi(verbose,args.simulated,args.localparams)
x393Cmprs = x393_cmprs.X393Cmprs(verbose,args.simulated,args.localparams)
x393FrameSequencer = x393_frame_sequencer.X393FrameSequencer(verbose,args.simulated,args.localparams)
x393Sensor = x393_sensor.X393Sensor(verbose,args.simulated,args.localparams)
'''
print ("----------------------")
print("x393_mem.__dict__="+str(x393_mem.__dict__))
......@@ -372,6 +375,8 @@ USAGE
extractTasks(x393_gpio.X393GPIO, x393GPIO)
extractTasks(x393_cmprs_afi.X393CmprsAfi, x393CmprsAfi)
extractTasks(x393_cmprs.X393Cmprs, x393Cmprs)
extractTasks(x393_frame_sequencer.X393FrameSequencer, x393FrameSequencer)
extractTasks(x393_sensor.X393Sensor, x393Sensor)
for cmdLine in commands:
print ('Running task: '+str(cmdLine))
......
py393/x393_axi_control_status.py
View file @ d9f09d9d
......@@ -318,85 +318,6 @@ class X393AxiControlStatus(object):
self.program_status (vrlg.MCNTRL_TEST01_ADDR, vrlg.MCNTRL_TEST01_CHN4_STATUS_CNTRL,mode,seq_num)#; //MCNTRL_TEST01_STATUS_REG_CHN4_ADDR= 'h3e,
self.program_status (vrlg.MEMBRIDGE_ADDR, vrlg.MEMBRIDGE_STATUS_CNTRL, mode,seq_num)#; //MCNTRL_TEST01_STATUS_REG_CHN4_ADDR= 'h3e,
def program_status_sensor_i2c( self,
num_sensor,
mode, # input [1:0] mode;
seq_num): # input [5:0] seq_num;
"""
Set status generation mode for selected sensor port i2c control
@param num_sensor - number of the sensor port (0..3)
@param mode - status generation mode:
0: disable status generation,
1: single status request,
2: auto status, keep specified seq number,
4: auto, inc sequence number
@param seq_number - 6-bit sequence number of the status message to be sent
"""
self.program_status (vrlg.SENSOR_GROUP_ADDR + num_sensor * vrlg.SENSOR_BASE_INC + vrlg.SENSI2C_CTRL_RADDR,
vrlg.SENSI2C_STATUS,
mode,
seq_num)# //MCONTR_PHY_STATUS_REG_ADDR= 'h0,
def program_status_sensor_io( self,
num_sensor,
mode, # input [1:0] mode;
seq_num): # input [5:0] seq_num;
"""
Set status generation mode for selected sensor port io subsystem
@param num_sensor - number of the sensor port (0..3)
@param mode - status generation mode:
0: disable status generation,
1: single status request,
2: auto status, keep specified seq number,
4: auto, inc sequence number
@param seq_number - 6-bit sequence number of the status message to be sent
"""
self.program_status (vrlg.SENSOR_GROUP_ADDR + num_sensor * vrlg.SENSOR_BASE_INC + vrlg.SENSIO_RADDR,
vrlg.SENSIO_STATUS,
mode,
seq_num)# //MCONTR_PHY_STATUS_REG_ADDR= 'h0,
def program_status_compressor(self,
cmprs_chn,
mode, # input [1:0] mode;
seq_num): # input [5:0] seq_num;
"""
Set status generation mode for selected compressor channel
@param cmprs_chn - number of the compressor channel (0..3)
@param mode - status generation mode:
0: disable status generation,
1: single status request,
2: auto status, keep specified seq number,
4: auto, inc sequence number
@param seq_number - 6-bit sequence number of the status message to be sent
"""
self.program_status (vrlg.CMPRS_GROUP_ADDR + cmprs_chn * vrlg.CMPRS_BASE_INC,
vrlg.CMPRS_STATUS_CNTRL,
mode,
seq_num)# //MCONTR_PHY_STATUS_REG_ADDR= 'h0,
'''
def program_status_gpio(self,
mode, # input [1:0] mode;
seq_num): # input [5:0] seq_num;
"""
Set status generation mode for GPIO port
@param mode - status generation mode:
0: disable status generation,
1: single status request,
2: auto status, keep specified seq number,
4: auto, inc sequence number
@param seq_number - 6-bit sequence number of the status message to be sent
"""
self.program_status (vrlg.GPIO_ADDR,
vrlg.GPIO_SET_STATUS,
mode,
seq_num)# //MCONTR_PHY_STATUS_REG_ADDR= 'h0,
'''
def enable_cmda(self,
en): # input en;
"""
......
py393/x393_cmprs.py
View file @ d9f09d9d
......@@ -57,6 +57,26 @@ class X393Cmprs(object):
except:
pass
def program_status_compressor(self,
cmprs_chn,
mode, # input [1:0] mode;
seq_num): # input [5:0] seq_num;
"""
Set status generation mode for selected compressor channel
@param cmprs_chn - number of the compressor channel (0..3)
@param mode - status generation mode:
0: disable status generation,
1: single status request,
2: auto status, keep specified seq number,
4: auto, inc sequence number
@param seq_number - 6-bit sequence number of the status message to be sent
"""
self.x393_axi_tasks.program_status (
vrlg.CMPRS_GROUP_ADDR + cmprs_chn * vrlg.CMPRS_BASE_INC,
vrlg.CMPRS_STATUS_CNTRL,
mode,
seq_num)# //MCONTR_PHY_STATUS_REG_ADDR= 'h0,
def func_compressor_format (self,
num_macro_cols_m1,
num_macro_rows_m1,
......
py393/x393_frame_sequencer.py 0 → 100644
View file @ d9f09d9d
from __future__ import division
from __future__ import print_function
'''
# Copyright (C) 2015, Elphel.inc.
# Class to control 10393 Frame sequencer that allows storing and applying
# register writes synchronized by the sensors frame sync
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http:#www.gnu.org/licenses/>.
@author: Andrey Filippov
@copyright: 2015 Elphel, Inc.
@license: GPLv3.0+
@contact: andrey@elphel.coml
@deffield updated: Updated
'''
__author__ = "Andrey Filippov"
__copyright__ = "Copyright 2015, Elphel, Inc."
__license__ = "GPL"
__version__ = "3.0+"
__maintainer__ = "Andrey Filippov"
__email__ = "andrey@elphel.com"
__status__ = "Development"
#import sys
#import pickle
from x393_mem import X393Mem
import x393_axi_control_status
import x393_utils
#import time
import vrlg
class X393FrameSequencer(object):
DRY_MODE= True # True
DEBUG_MODE=1
x393_mem=None
x393_axi_tasks=None #x393X393AxiControlStatus
x393_utils=None
verbose=1
def __init__(self, debug_mode=1,dry_mode=True, saveFileName=None):
self.DEBUG_MODE= debug_mode
self.DRY_MODE= dry_mode
self.x393_mem= X393Mem(debug_mode,dry_mode)
self.x393_axi_tasks= x393_axi_control_status.X393AxiControlStatus(debug_mode,dry_mode)
self.x393_utils= x393_utils.X393Utils(debug_mode,dry_mode, saveFileName) # should not overwrite save file path
try:
self.verbose=vrlg.VERBOSE
except:
pass
def ctrl_cmd_frame_sequencer (self,
num_sensor,
reset = False,
start = False,
stop = False):
"""
Control frame sequence
@param num_sensor - sensor channel number
@param reset - reset sequencer (also stops)
@param start - start sequencer
@param stop - stop sequencer
"""
data = 0;
if reset:
data |= 1 << vrlg.CMDFRAMESEQ_RST_BIT
if start:
data |= 1 << (vrlg.CMDFRAMESEQ_RUN_BIT -1)
if start or stop:
data |= 1 << vrlg.CMDFRAMESEQ_RUN_BIT
self.x393_axi_tasks.write_contol_register(
vrlg.CMDFRAMESEQ_ADDR_BASE + num_sensor * vrlg.CMDFRAMESEQ_ADDR_INC + vrlg.CMDFRAMESEQ_CTRL,
data)
def write_cmd_frame_sequencer (self,
num_sensor,
relative,
frame_addr,
addr,
data):
"""
Schedule/execute frame sequence command (register write)
@param num_sensor - sensor channel number
@param relative - False - use absolute address (0..15), True - use relative (to current frame) address - 0..14
writes to relative address 0 are considered ASAP and do not wait for the frame sync
@param frame_addr - 4-bit frame address (relative or absolute), relative must be < 15
@param addr; // command address (register to which command should be applied), 32 word (not byte) address, relative to maxi0 space
@param data; // command data to write
"""
frame_addr &= 0xf
if relative and (frame_addr == 0xf):
raise Exception ("task write_cmd_frame_sequencer(): relative address 0xf is invalid, it is reserved for module control")
reg_addr = vrlg.CMDFRAMESEQ_ADDR_BASE + num_sensor * vrlg.CMDFRAMESEQ_ADDR_INC + (vrlg.CMDFRAMESEQ_ABS,vrlg.CMDFRAMESEQ_REL)[relative] + frame_addr
self.x393_axi_tasks.write_contol_register( reg_addr, addr) # two writes to the same location - first is the register address
self.x393_axi_tasks.write_contol_register( reg_addr, data) # second is data to write to that register
py393/x393_gpio.py
View file @ d9f09d9d
......@@ -125,9 +125,9 @@ class X393GPIO(object):
data = 0
for i, e in enumerate (ext):
if not e is None:
if (e == 0) or (e.upper() == "0") or (e.upper() == "L"):
if (e is False) or (e == 0) or (e.upper() == "0") or (e.upper() == "L"):
data |= 1 << (2*i)
elif (e == 1) or (e.upper() == "1") or (e.upper() == "H"):
elif (e is True) or (e == 1) or (e.upper() == "1") or (e.upper() == "H"):
data |= 2 << (2*i)
elif e.upper() == "I":
data |= 3 << (2*i)
......
py393/x393_mcntrl_adjust.py
View file @ d9f09d9d
......@@ -3763,7 +3763,7 @@ class X393McntrlAdjust(object):
else:
raise Exception ("set_delays_with_reinit failed to read with safe delays for phase=%d after re-initializing device, wl_rslt=%s"%
(phase,str(wl_rslt)))
return cmda_odly_early[phase] # safe command/adderss delay
return cmda_odly_early[phase] # safe command/address delay
def cmd_phase_step(phase):
def measure_block(dly,
......
py393/x393_mcntrl_membridge.py
View file @ d9f09d9d
......@@ -182,7 +182,7 @@ class X393McntrlMembridge(object):
def membridge_setup (self,
len64, # input [28:0] len64; # number of 64-bit words to transfer
width64, # input [28:0] width64; # frame width in 64-bit words
start64, # input [28:0] start64; # relative start adderss of the transfer (set to 0 when writing lo_addr64)
start64, # input [28:0] start64; # relative start address of the transfer (set to 0 when writing lo_addr64)
lo_addr64 = None, # input [28:0] lo_addr64; # low address of the system memory range, in 64-bit words
size64 = None, # input [28:0] size64; # size of the system memory range in 64-bit words
cache = 0x3,
......
py393/x393_pio_sequences.py
View file @ d9f09d9d
......@@ -129,7 +129,7 @@ class X393PIOSequences(object):
x393_mcontr_encode_cmd
'''
def func_encode_cmd(self, # function [31:0]
addr, # input [14:0] addr; // 15-bit row/column adderss
addr, # input [14:0] addr; // 15-bit row/column address
bank, # input [2:0] bank; // bank (here OK to be any)
rcw, # input [2:0] rcw; // RAS/CAS/WE, positive logic
odt_en, # input odt_en; // enable ODT
......@@ -145,7 +145,7 @@ class X393PIOSequences(object):
buf_rst): # input buf_rst; // connect to external buffer (but only if not paused)
"""
Encode data into memory controller sequencer word
<addr> 15-bit row/column adderss
<addr> 15-bit row/column address
<bank> 3-bit bank address
<rcw> 3-bit combined {RAS,CAS,WE}, positive logic
<odt_en> enable ODT
......@@ -161,7 +161,7 @@ class X393PIOSequences(object):
<buf_rst> reset external buffer page address to 0, increment page number
"""
return (
((addr & 0x7fff) << 17) | # addr[14:0], // 15-bit row/column adderss
((addr & 0x7fff) << 17) | # addr[14:0], // 15-bit row/column address
((bank & 0x7) << 14) | # bank [2:0], // bank
((rcw & 0x7) << 11) | # rcw[2:0], // RAS/CAS/WE
((0,1)[odt_en] << 10) | # odt_en, // enable ODT
......@@ -829,7 +829,7 @@ class X393PIOSequences(object):
reset_dll, # input reset_dll;
verbose=0):
"""
Setup sequence (at paramter-defined adderss) to write MR0, MR1, MR2 and MR3 mode registers of DDR3 memory
Setup sequence (at paramter-defined address) to write MR0, MR1, MR2 and MR3 mode registers of DDR3 memory
<reset_dll> reset memory DLL when running this sequence
<verbose> print data being written (default: False)
"""
......
py393/x393_sensor.py 0 → 100644
View file @ d9f09d9d
This diff is collapsed.
timing/rtc393.v
View file @ d9f09d9d
......@@ -25,7 +25,7 @@
module rtc393 #(
parameter RTC_ADDR = 'h704, //..'h707
parameter RTC_STATUS_REG_ADDR = 'h31, // address where status can be read out (currently just sequence # and alternating bit)
parameter RTC_SEC_USEC_ADDR = 'h32, //'h33 address where seconds of the snapshot can be read (microseconds - next adderss)
parameter RTC_SEC_USEC_ADDR = 'h32, //'h33 address where seconds of the snapshot can be read (microseconds - next address)
parameter RTC_MASK = 'h7fc,
parameter RTC_MHZ = 25, // RTC input clock in MHz (should be interger number)
......
timing/timing393.v
View file @ d9f09d9d
......@@ -24,7 +24,7 @@ module timing393 #(
parameter RTC_ADDR= 'h704, // 'h707
parameter CAMSYNC_ADDR = 'h708, // 'h70f
parameter RTC_STATUS_REG_ADDR = 'h31, // (1 loc) address where status can be read out (currently just sequence # and alternating bit)
parameter RTC_SEC_USEC_ADDR = 'h32, // ..'h33 address where seconds of the snapshot can be read (microseconds - next adderss)
parameter RTC_SEC_USEC_ADDR = 'h32, // ..'h33 address where seconds of the snapshot can be read (microseconds - next address)
parameter RTC_MASK = 'h7fc,
parameter CAMSYNC_MASK = 'h7f8,
parameter CAMSYNC_MODE = 'h0,
......
x393.v
View file @ d9f09d9d
......@@ -285,7 +285,7 @@ module x393 #(
wire status_compressor_start; //
// TODO: Add sequencer status (16+2) bits of current frame number. Ose 'h31 as the adderss, 'h702 (701..703 were empty) to program
// TODO: Add sequencer status (16+2) bits of current frame number. Ose 'h31 as the address, 'h702 (701..703 were empty) to program
wire [7:0] status_sequencer_ad; // Other status byte-wide address/data
wire status_sequencer_rq; // Other status request
wire status_sequencer_start; // S uppressThisWarning VEditor ****** Other status packet transfer start (currently with 0 latency from status_root_rq)
......
x393_testbench02.tf
View file @ d9f09d9d
......@@ -2391,7 +2391,7 @@ task setup_sensor_channel;
set_sensor_histogram_saxi (
1'b1, // input en;
1'b1, // input nrst;
1'b1, // input confirm_write; // wait for the write confirmed befoer swicthing channels
1'b1, // input confirm_write; // wait for the write confirmed before switching channels
4'h3); // input [3:0] cache_mode; // default should be 4'h3
/*
......@@ -2812,7 +2812,7 @@ task test_i2c_353;
1'b1, // input set_bytes; // [11] if 1, use bytes (below), 0 - nop
2'h3, // input [SENSI2C_CMD_BYTES_PBITS -1 : 0] bytes; // [10:9] set command bytes to send after slave address (0..3)
1'b1, // input set_dly; // [8] if 1, use dly (0 - ignore)
8'h0a, // input [SENSI2C_CMD_DLY_PBITS - 1 : 0] dly; // [7:0] - duration of quater i2c cycle (if 0, [3:0] control SCL+SDA)
8'h0a, // input [SENSI2C_CMD_DLY_PBITS - 1 : 0] dly; // [7:0] - duration of quarter i2c cycle (if 0, [3:0] control SCL+SDA)
2'b0, // input [SENSI2C_CMD_SCL_WIDTH -1 : 0] scl_ctl; // [1:0] : 0: NOP, 1: 1'b0->SCL, 2: 1'b1->SCL, 3: 1'bz -> SCL
2'b0); // input [SENSI2C_CMD_SDA_WIDTH -1 : 0] sda_ctl; // [3:2] : 0: NOP, 1: 1'b0->SDA, 2: 1'b1->SDA, 3: 1'bz -> SDA
repeat (10) @ (posedge CLK); // wait for initialization to be done TODO: use status
......@@ -2848,7 +2848,7 @@ task test_i2c_353;
endtask
//x393_axi_control_status.py
//x393_sensor.py
task program_status_sensor_i2c;
input [1:0] num_sensor;
input [1:0] mode;
......@@ -2861,7 +2861,7 @@ task program_status_sensor_i2c;
end
endtask
//x393_axi_control_status.py
//x393_sensor.py
task program_status_sensor_io;
input [1:0] num_sensor;
input [1:0] mode;
......@@ -2874,7 +2874,7 @@ task program_status_sensor_io;
end
endtask
//x393_axi_control_status.py
//x393_cmprs.py
task program_status_compressor;
input [1:0] num_sensor;
input [1:0] mode;
......@@ -2968,7 +2968,7 @@ task set_sensor_i2c_command;
input set_bytes; // [11] if 1, use bytes (below), 0 - nop
input [SENSI2C_CMD_BYTES_PBITS -1 : 0] bytes; // [10:9] set command bytes to send after slave address (0..3)
input set_dly; // [8] if 1, use dly (0 - ignore)
input [SENSI2C_CMD_DLY_PBITS - 1 : 0] dly; // [7:0] - duration of quater i2c cycle (if 0, [3:0] control SCL+SDA)
input [SENSI2C_CMD_DLY_PBITS - 1 : 0] dly; // [7:0] - duration of quarter i2c cycle (if 0, [3:0] control SCL+SDA)
input [SENSI2C_CMD_SCL_WIDTH -1 : 0] scl_ctl; // [1:0] : 0: NOP, 1: 1'b0->SCL, 2: 1'b1->SCL, 3: 1'bz -> SCL
input [SENSI2C_CMD_SDA_WIDTH -1 : 0] sda_ctl; // [3:2] : 0: NOP, 1: 1'b0->SDA, 2: 1'b1->SDA, 3: 1'bz -> SDA
......@@ -3299,7 +3299,7 @@ endtask
task set_sensor_histogram_saxi;
input en;
input nrst;
input confirm_write; // wait for the write confirmed befoer swicthing channels
input confirm_write; // wait for the write confirmed before switching channels
input [3:0] cache_mode; // default should be 4'h3
reg [31:0] data;
begin
......@@ -3373,7 +3373,7 @@ function [STATUS_DEPTH-1:0] func_status_addr_rtc_usec; // sec is in the next add
endfunction
*/
// camsync tasks
//x393_camsync.py
// x393_camsync.py
task set_camsync_mode;
input en; // 1 - enable, 0 - reset module
input [1:0] en_snd; // <2 - NOP, 2 - disable, 3 - enable sending timestamp with sync pulse
......@@ -3394,7 +3394,7 @@ task set_camsync_mode;
end
endtask
//x393_camsync.py
// x393_camsync.py
task set_camsync_inout; // set specified input bit, keep other ones
input is_out; // 0 - input selection, 1 - output selection
input integer bit_number; // 0..9 - bit to use
......@@ -3408,6 +3408,7 @@ task set_camsync_inout; // set specified input bit, keep other ones
end
endtask
// x393_camsync.py
task reset_camsync_inout; // disable all inputs
input is_out; // 0 - input selection, 1 - output selection
begin
......@@ -3416,6 +3417,7 @@ task reset_camsync_inout; // disable all inputs
end
endtask
// x393_camsync.py
task set_camsync_period;
input [31:0] period; // 0 - input selection, 1 - output selection
begin
......@@ -3423,6 +3425,7 @@ task set_camsync_period;
end
endtask
// x393_camsync.py
task set_camsync_delay;
input [1:0] sub_chn;
input [31:0] dly; // 0 - input selection, 1 - output selection
......@@ -3433,6 +3436,7 @@ endtask
// command sequencer control
// Functions used by sensor-related tasks
// x393_frame_sequencer.py
task ctrl_cmd_frame_sequencer;
input [1:0] num_sensor; // sensor channel number
input reset; // reset sequencer (also stops)
......@@ -3450,16 +3454,17 @@ task ctrl_cmd_frame_sequencer;
end
endtask
// x393_frame_sequencer.py
task write_cmd_frame_sequencer;
input [1:0] num_sensor; // sensor channel number
input relative; // 0 - absolute (address = 0..f), 1 - relative (address= 0..e)
input [3:0] frame_addr; // frame address (relative ort absolute)
input [3:0] frame_addr; // frame address (relative or absolute)
input [AXI_WR_ADDR_BITS-1:0] addr; // command address (register to which command should be applied)
input [31:0] data; // command data
reg [29:0] reg_addr;
begin
if (relative && (&frame_addr)) $display("task write_cmd_frame_sequencer(): relative adderss 'hf is invalid, it is reserved for module control");
if (relative && (&frame_addr)) $display("task write_cmd_frame_sequencer(): relative address 'hf is invalid, it is reserved for module control");
else begin
reg_addr = CMDFRAMESEQ_ADDR_BASE + num_sensor * CMDFRAMESEQ_ADDR_INC + (relative ? CMDFRAMESEQ_REL : CMDFRAMESEQ_ABS) + frame_addr;
write_contol_register(reg_addr, {{32-AXI_WR_ADDR_BITS{1'b0}}, addr});
......@@ -3467,7 +3472,7 @@ task write_cmd_frame_sequencer;
end
end
endtask
// x393_sensor.py
function [SENSOR_MODE_WIDTH-1:0] func_sensor_mode;
input [3:0] hist_en; // [0..3] 1 - enable histogram modules, disable after processing the started frame
input [3:0] hist_nrst; // [4..7] 0 - immediately reset histogram module
......@@ -3485,13 +3490,14 @@ function [SENSOR_MODE_WIDTH-1:0] func_sensor_mode;
endfunction
// x393_sensor.py
function [31 : 0] func_sensor_i2c_command;
input rst_cmd; // [14] reset all FIFO (takes 16 clock pulses), also - stops i2c until run command
input [SENSI2C_CMD_RUN_PBITS : 0] run_cmd; // [13:12]3 - run i2c, 2 - stop i2c (needed before software i2c), 1,0 - no change to run state
input set_bytes; // [11] if 1, use bytes (below), 0 - nop
input [SENSI2C_CMD_BYTES_PBITS -1 : 0] bytes; // [10:9] set command bytes to send after slave address (0..3)
input set_dly; // [8] if 1, use dly (0 - ignore)
input [SENSI2C_CMD_DLY_PBITS - 1 : 0] dly; // [7:0] - duration of quater i2c cycle (if 0, [3:0] control SCL+SDA)
input [SENSI2C_CMD_DLY_PBITS - 1 : 0] dly; // [7:0] - duration of quarter i2c cycle (if 0, [3:0] control SCL+SDA)
input [SENSI2C_CMD_SCL_WIDTH -1 : 0] scl_ctl; // [17:16] : 0: NOP, 1: 1'b0->SCL, 2: 1'b1->SCL, 3: 1'bz -> SCL
input [SENSI2C_CMD_SDA_WIDTH -1 : 0] sda_ctl; // [19:18] : 0: NOP, 1: 1'b0->SDA, 2: 1'b1->SDA, 3: 1'bz -> SDA
......@@ -3513,6 +3519,7 @@ endfunction
// x393_sensor.py
function [31 : 0] func_sensor_io_ctl;
input [1:0] mrst; // <2: keep MRST, 2 - MRST low (active), 3 - high (inactive)
input [1:0] arst; // <2: keep ARST, 2 - ARST low (active), 3 - high (inactive)
......@@ -3533,11 +3540,12 @@ function [31 : 0] func_sensor_io_ctl;
tmp [SENS_CTRL_EXT_CLK +: 2] = clk_sel;
tmp [SENS_CTRL_LD_DLY] = set_delays;
tmp [SENS_CTRL_QUADRANTS_EN] = set_guadrants;
tmp [SENS_CTRL_EXT_CLK +: SENS_CTRL_QUADRANTS_WIDTH] = quadrants;
tmp [SENS_CTRL_QUADRANTS +: SENS_CTRL_QUADRANTS_WIDTH] = quadrants;
func_sensor_io_ctl = tmp;
end
endfunction
// x393_sensor.py
function [31 : 0] func_sensor_jtag_ctl;
input [1:0] pgmen; // <2: keep PGMEN, 2 - PGMEN low (inactive), 3 - high (active) enable JTAG control
input [1:0] prog; // <2: keep prog, 2 - prog low (active), 3 - high (inactive) ("program" pin control)
......@@ -3548,9 +3556,8 @@ function [31 : 0] func_sensor_jtag_ctl;
reg [31 : 0] tmp;
begin
tmp = 0;
tmp [SENS_JTAG_TDI +: 2] = pgmen;
tmp [SENS_JTAG_TMS +: 2] = prog;
tmp [SENS_JTAG_PGMEN +: 2] = pgmen;
tmp [SENS_JTAG_PROG +: 2] = prog;
tmp [SENS_JTAG_TCK +: 2] = tck;
tmp [SENS_JTAG_TMS +: 2] = tms;
tmp [SENS_JTAG_TDI +: 2] = tdi;
......@@ -3558,6 +3565,7 @@ function [31 : 0] func_sensor_jtag_ctl;
end
endfunction
// x393_sensor.py
function [31 : 0] func_sensor_gamma_ctl;
input [1:0] bayer;
input table_page;
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment