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Commit d7392a0f authored by Andrey Filippov's avatar Andrey Filippov
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tested imx-5 and external syncs with event logger, version 32'h03934019

parent faa42107
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cocotb/x393_cocotb_lwir_06.sav
View file @ d7392a0f
[*]
[*] GTKWave Analyzer v3.3.103 (w)1999-2019 BSI
[*] Sat Feb 11 21:53:42 2023
[*] Tue Feb 14 19:38:19 2023
[*]
[dumpfile] "/home/elphel/git/x393/simulation/x393_dut-20230211143708385.fst"
[dumpfile_mtime] "Sat Feb 11 21:53:30 2023"
[dumpfile_size] 141595306
[dumpfile] "/home/elphel/git/x393/simulation/x393_dut-20230213165222653.fst"
[dumpfile_mtime] "Tue Feb 14 00:48:28 2023"
[dumpfile_size] 777646791
[savefile] "/home/elphel/git/x393/cocotb/x393_cocotb_lwir_06.sav"
[timestart] 0
[size] 1920 1171
[pos] -1920 47
*-23.998985 81560000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[size] 1744 1144
[pos] 1920 74
*-27.278334 63200000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] x393_dut.
[treeopen] x393_dut.i_simul_imx5.
[treeopen] x393_dut.x393_i.
......@@ -29,11 +29,12 @@
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sens_103993_i.sens_103993_l3_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.sens_103993_i.
[treeopen] x393_dut.x393_i.timing393_i.
[treeopen] x393_dut.x393_i.timing393_i.camsync393_i.
[sst_width] 325
[signals_width] 278
[sst_expanded] 1
[sst_vpaned_height] 773
[sst_vpaned_height] 365
@800200
-simul_imx5
@28
......@@ -112,6 +113,21 @@ x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.trig
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.trig_in
(4)x393_dut.x393_i.gpio_pins[9:0]
(5)x393_dut.x393_i.gpio_pins[9:0]
@800022
x393_dut.x393_i.gpio_pins[9:0]
@28
(0)x393_dut.x393_i.gpio_pins[9:0]
(1)x393_dut.x393_i.gpio_pins[9:0]
(2)x393_dut.x393_i.gpio_pins[9:0]
(3)x393_dut.x393_i.gpio_pins[9:0]
(4)x393_dut.x393_i.gpio_pins[9:0]
(5)x393_dut.x393_i.gpio_pins[9:0]
(6)x393_dut.x393_i.gpio_pins[9:0]
(7)x393_dut.x393_i.gpio_pins[9:0]
(8)x393_dut.x393_i.gpio_pins[9:0]
(9)x393_dut.x393_i.gpio_pins[9:0]
@1001200
-group_end
@c00022
x393_dut.x393_i.gpio_camsync_en[9:0]
@28
......@@ -582,9 +598,17 @@ x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.eof
@800200
-event_logger
@28
x393_dut.x393_i.event_logger_i.xrst
x393_dut.x393_i.event_logger_i.we_config_rst
x393_dut.x393_i.event_logger_i.we_config_rst_xclk
x393_dut.x393_i.event_logger_i.config_rst_mclk
x393_dut.x393_i.event_logger_i.config_rst
@22
x393_dut.x393_i.event_logger_i.enable_syn_mclk[4:0]
@28
x393_dut.x393_i.event_logger_i.i_rs232_rcv.xclk
x393_dut.x393_i.event_logger_i.cmd_we
@c00023
@c00022
x393_dut.x393_i.event_logger_i.ctrl_addr[6:0]
@28
(0)x393_dut.x393_i.event_logger_i.ctrl_addr[6:0]
......@@ -594,7 +618,7 @@ x393_dut.x393_i.event_logger_i.ctrl_addr[6:0]
(4)x393_dut.x393_i.event_logger_i.ctrl_addr[6:0]
(5)x393_dut.x393_i.event_logger_i.ctrl_addr[6:0]
(6)x393_dut.x393_i.event_logger_i.ctrl_addr[6:0]
@1401201
@1401200
-group_end
@22
x393_dut.x393_i.event_logger_i.cmd_data_r[31:0]
......@@ -811,7 +835,7 @@ x393_dut.x393_i.event_logger_i.ts_stb_chn1
x393_dut.x393_i.event_logger_i.ts_stb_chn2
x393_dut.x393_i.event_logger_i.ts_stb_chn3
x393_dut.x393_i.event_logger_i.ts_stb_chn4
@800022
@c00022
x393_dut.x393_i.event_logger_i.ts_data_chn4[7:0]
@28
(0)x393_dut.x393_i.event_logger_i.ts_data_chn4[7:0]
......@@ -822,7 +846,7 @@ x393_dut.x393_i.event_logger_i.ts_data_chn4[7:0]
(5)x393_dut.x393_i.event_logger_i.ts_data_chn4[7:0]
(6)x393_dut.x393_i.event_logger_i.ts_data_chn4[7:0]
(7)x393_dut.x393_i.event_logger_i.ts_data_chn4[7:0]
@1001200
@1401200
-group_end
@28
x393_dut.x393_i.event_logger_i.we_config_imu
......@@ -908,9 +932,36 @@ x393_dut.x393_i.event_logger_i.timestamps_rdata[15:0]
x393_dut.x393_i.event_logger_i.config_syn_mclk[4:0]
@28
x393_dut.x393_i.event_logger_i.config_rst_mclk
@c00022
x393_dut.x393_i.event_logger_i.config_gps[3:0]
@28
(0)x393_dut.x393_i.event_logger_i.config_gps[3:0]
(1)x393_dut.x393_i.event_logger_i.config_gps[3:0]
(2)x393_dut.x393_i.event_logger_i.config_gps[3:0]
(3)x393_dut.x393_i.event_logger_i.config_gps[3:0]
@1401200
-group_end
@1000200
-event_logger
@c00200
-rs232_rcv
@22
x393_dut.x393_i.event_logger_i.i_rs232_rcv.bitHalfPeriod[15:0]
x393_dut.x393_i.event_logger_i.i_rs232_rcv.bit_dur_cntr[15:0]
@28
x393_dut.x393_i.event_logger_i.i_rs232_rcv.xclk
@22
x393_dut.x393_i.event_logger_i.i_rs232_rcv.bit_cntr[4:0]
@28
x393_dut.x393_i.event_logger_i.i_rs232_rcv.ser_rst
x393_dut.x393_i.event_logger_i.i_rs232_rcv.ser_di
x393_dut.x393_i.event_logger_i.i_rs232_rcv.ser_do
x393_dut.x393_i.event_logger_i.i_rs232_rcv.ser_do_stb
@200
-
@1401200
-rs232_rcv
@c00200
-nmea_decoder393
@28
x393_dut.x393_i.event_logger_i.i_nmea_decoder.ser_rst
......@@ -1130,7 +1181,7 @@ x393_dut.x393_i.event_logger_i.i_imx5_decoder393.last_word_written[5:0]
-
@1401200
-imx5_decoder393
@800200
@c00200
-logger_arbiter393
@28
(2)x393_dut.x393_i.event_logger_i.i_logger_arbiter.ts_rq_in[3:0]
......@@ -1151,9 +1202,9 @@ x393_dut.x393_i.event_logger_i.i_logger_arbiter.ts_en
x393_dut.x393_i.event_logger_i.i_logger_arbiter.dv
@22
x393_dut.x393_i.event_logger_i.i_logger_arbiter.sample_counter_r[23:0]
@1000200
@1401200
-logger_arbiter393
@800200
@c00200
-imu_message393
@28
x393_dut.x393_i.event_logger_i.i_imu_message.we
......@@ -1171,7 +1222,7 @@ x393_dut.x393_i.event_logger_i.i_imu_message.raddr[4:0]
x393_dut.x393_i.event_logger_i.i_imu_message.rdata[15:0]
@200
-
@1000200
@1401200
-imu_message393
@c00200
-imu_exttime
......
fpga_version.vh
View file @ d7392a0f
......@@ -35,7 +35,10 @@
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
parameter FPGA_VERSION = 32'h03934016; // Boson640, for 103993A, started IMU
parameter FPGA_VERSION = 32'h03934019; // Boson640, logger debug disabled
// parameter FPGA_VERSION = 32'h03934018; // Boson640, debugging logger 02
// parameter FPGA_VERSION = 32'h03934017; // Boson640, debugging logger 01
// parameter FPGA_VERSION = 32'h03934016; // Boson640, for 103993A, started IMU
// parameter FPGA_VERSION = 32'h03931004; // parallel, starting IMS support // not yet used
// parameter FPGA_VERSION = 32'h03931003; // parallel, adding camsync trigger decimation - modifying decimation
// parameter FPGA_VERSION = 32'h03934015; // Boson640, for 103993A, debugging 4 removed DE deglitch - modifying decimation
......
logger/event_logger.v
View file @ d7392a0f
......@@ -113,7 +113,9 @@ module event_logger#(
output [15:0] data_out, // 16-bit data out to DMA1 (@posdge mclk)
output data_out_stb,// data out valid (@posedge mclk)
// sample_counter, // could be DMA latency, safe to use sample_counter-1
output [31:0] debug_state);
output [31:0] debug_state
// ,input [3:0] dbg_logger2023
);
localparam SELECT_IMX5 = 2'h3; // when config_imu == SELECT_IMX5 - use IMX instead of the GPS on serial input
wire [23:0] sample_counter; // TODO: read with status! could be DMA latency, safe to use sample_counter-1
......@@ -141,16 +143,15 @@ module event_logger#(
reg we_bitHalfPeriod = 0;
reg [1:0] config_imu;
reg [3:0] config_gps;
reg [1:0] config_imu; // should be 3 for IMXS-5
reg [3:0] config_gps; // should be 1 for IMX-5 (at least two lsb-s), will use ext2 for serial input (alse switches pulse1sec in ext3/ext5)
reg [4:0] config_msg;
reg config_rst;
reg [3:0] config_debug;
reg [15:0] bitHalfPeriod;// serial gps speed - number of xclk pulses in half bit period
// Temporary reusing available bit
// wire use_imx5 = config_gps[2];
reg use_imx5; // = config_gps[2]; will use config_imu == 3 (not used before)
reg use_imx5; // will use config_imu == 3 (not used before)
wire we_config_imu_xclk; // copy config_imu_mclk (@mclk) to config_imu (@xclk)
wire we_config_gps_xclk;
......@@ -258,7 +259,6 @@ module event_logger#(
assign message_trig= config_msg[4] ^ pre_message_trig;
// assign timestamp_request[1]= config_gps[3]? (config_gps[2]?nmea_sent_start:gps_ts_stb):gps_pulse1sec_single;
assign timestamp_request[1]= use_imx5 ? imx5_ts_rq : (config_gps[3]? (config_gps[2]?nmea_sent_start:gps_ts_stb):gps_pulse1sec_single);
always @ (posedge mclk) begin // no enable for channel 4 - incoming ext trigger
......@@ -374,6 +374,34 @@ module event_logger#(
.we ({cmd_status,cmd_we}) // output
);
wire [25:0] status;
//`define DEBUG_LOGGER 1
//dbg_logger2023 = {start_en, ts_external_pclk, rcv_run, trigger_condition}
`ifdef DEBUG_LOGGER
// wire start_en = dbg_logger2023[3];
// wire ts_external_pclk = dbg_logger2023[2];
// wire rcv_run = dbg_logger2023[1];
// wire trigger_condition = dbg_logger2023[0];
// imx5_ts_rq
reg [7:0] ext_di_r;
reg [7:0] ext_di_r2;
reg [10:0] toggle_bits = 0;
// wire[13:0] pulses = {ts_external_pclk, rcv_run, trigger_condition, ts_stb_chn4, (ext_di_r & ~ext_di_r2)};
// wire[10:0] pulses = {ts_stb_chn4, (ser_do & ser_do_stb), rs232_start, (ext_di_r & ~ext_di_r2)};
wire[10:0] pulses = {(ser_do & ser_do_stb), rs232_start, imx5_ts_rq, (ext_di_r & ~ext_di_r2)};
always @ (posedge xclk) begin
// ext_di_r <= ext_di;
ext_di_r <= {ser_di, 4'b0, imx5_rdy, ext_di[9], ext_di[2]};
ext_di_r2 <= ext_di_r;
if (xrst) toggle_bits <= 0;
else toggle_bits <= toggle_bits ^ pulses;
end
assign status = {toggle_bits[10:0], sample_counter[12:0], enable_gps, config_rst};
`else
assign status = {sample_counter,2'b0};
`endif
status_generate #(
.STATUS_REG_ADDR (LOGGER_STATUS_REG_ADDR),
.PAYLOAD_BITS (26),
......@@ -384,12 +412,13 @@ module event_logger#(
.srst (mrst), // input
.we (cmd_status), // input
.wd (cmd_data[7:0]), // input[7:0]
.status ({sample_counter,2'b0}), // input[25:0] // 2 LSBs - may add "real" status
.status (status), // {sample_counter,2'b0}), // input[25:0] // 2 LSBs - may add "real" status
.ad (status_ad), // output[7:0]
.rq (status_rq), // output
.start (status_start) // input
);
imu_spi393 i_imu_spi (
// .rst(rst),
.mclk (mclk), // system clock, negedge
......
py393/x393_export_c.py
View file @ d7392a0f
......@@ -2672,14 +2672,18 @@ class X393ExportC(object):
dw.append(("imu_slot", vrlg.LOGGER_CONF_IMU - vrlg.LOGGER_CONF_IMU_BITS, vrlg.LOGGER_CONF_IMU_BITS, 0, "IMU slot (3 - use IMX5 instead of GPS)"))
dw.append(("imu_set", vrlg.LOGGER_CONF_IMU, 1, 0, "Set 'imu_slot'"))
dw.append(("gps_slot", vrlg.LOGGER_CONF_GPS - vrlg.LOGGER_CONF_GPS_BITS, 2, 0, "GPS slot"))
dw.append(("gps_invert", vrlg.LOGGER_CONF_GPS - vrlg.LOGGER_CONF_GPS_BITS + 2, 1, 0, "GPS inpert 1pps signal"))
dw.append(("gps_invert", vrlg.LOGGER_CONF_GPS - vrlg.LOGGER_CONF_GPS_BITS + 2, 1, 0, "GPS ivpert 1pps signal"))
dw.append(("gps_ext", vrlg.LOGGER_CONF_GPS - vrlg.LOGGER_CONF_GPS_BITS + 3, 1, 0, "GPS sync to 1 pps signal (0 - sync to serial message)"))
dw.append(("gps_set", vrlg.LOGGER_CONF_GPS, 1, 0, "Set 'gps_*' fields"))
dw.append(("msg_input", vrlg.LOGGER_CONF_MSG - vrlg.LOGGER_CONF_MSG_BITS, 4, 0, "MSG pin: GPIO pin number to accept external signal (0xf - disable)"))
dw.append(("msg_invert", vrlg.LOGGER_CONF_MSG - vrlg.LOGGER_CONF_MSG_BITS + 4, 1, 0, "MSG input polarity - 0 - active high, 1 - active low"))
dw.append(("msg_set", vrlg.LOGGER_CONF_MSG, 1, 0, "Set 'msg_*' fields"))
dw.append(("log_sync", vrlg.LOGGER_CONF_SYN - vrlg.LOGGER_CONF_SYN_BITS, vrlg.LOGGER_CONF_SYN_BITS, 0, "Log frame sync events (bit per sensor channel)"))
dw.append(("log_sync", vrlg.LOGGER_CONF_SYN - vrlg.LOGGER_CONF_SYN_BITS, vrlg.LOGGER_CONF_SYN_BITS, 0, "Log frame sync events (bit per sensor channel, MSB - log external sync)"))
dw.append(("log_sync_set",vrlg.LOGGER_CONF_SYN, 1, 0, "Set 'log_sync' fields"))
dw.append(("log_en", vrlg.LOGGER_CONF_EN - vrlg.LOGGER_CONF_EN_BITS, vrlg.LOGGER_CONF_EN_BITS, 0, "Enable event logger (0- reset)"))
dw.append(("log_en_set", vrlg.LOGGER_CONF_EN, 1, 0, "Set 'log_enable' field"))
dw.append(("log_dbg", vrlg.LOGGER_CONF_DBG - vrlg.LOGGER_CONF_DBG_BITS, vrlg.LOGGER_CONF_DBG_BITS, 0, "IMU debug mode"))
dw.append(("log_dbg_set",vrlg.LOGGER_CONF_DBG, 1, 0, "Set 'log_dbg' field"))
return dw
def _enc_logger_data(self):
dw=[]
......
timing/camsync393.v
View file @ d7392a0f
......@@ -185,6 +185,8 @@ module camsync393 #(
output ts_rcv_stb_chn4, // 1 clock before ts_rcv_data is valid
output [7:0] ts_rcv_data_chn4 // byte-wide serialized timestamp message received or local
// ,output [3:0] dbg_logger2023
);
reg en = 0; // enable camsync module
// wire rst = mrst || !en;
......@@ -436,6 +438,8 @@ module camsync393 #(
(dly_cntr_chn1[31:0]!=0)?1'b1:1'b0,
(dly_cntr_chn0[31:0]!=0)?1'b1:1'b0};
// assign dbg_logger2023 = {start_en, ts_external_pclk, rcv_run, trigger_condition};
assign gpio_out_en = gpio_out_en_r;
//! in testmode GPIO[9] and GPIO[8] use internal signals instead of the outsync:
......
timing/timing393.v
View file @ d7392a0f
......@@ -138,6 +138,7 @@ module timing393 #(
output ts_logger_stb, // one clock pulse before sending TS data
output [7:0] ts_logger_data, // timestamp data (s0,s1,s2,s3,u0,u1,u2,u3==0)
output khz // 1 KHz 50% output
// ,output [3:0] dbg_logger2023
);
wire [3:0] frame_sync;
......@@ -329,6 +330,7 @@ module timing393 #(
.ts_rcv_data_chn3 (ts_data[3 * 8 +: 8]), // output[7:0]
.ts_rcv_stb_chn4 (ts_stb[4]), // output
.ts_rcv_data_chn4 (ts_data[4 * 8 +: 8]) // output[7:0]
// ,.dbg_logger2023 (dbg_logger2023) // ,output [3:0] dbg_logger2023
);
endmodule
......
x393.v
View file @ d7392a0f
......@@ -2520,7 +2520,7 @@ assign axi_grst = axi_rst_pre;
.dc (gpio_logger), // input[9:0]
.dc_en (gpio_logger_en) // input[9:0]
);
///wire [3:0] dbg_logger2023;
timing393 #(
.RTC_ADDR (RTC_ADDR),
.CAMSYNC_ADDR (CAMSYNC_ADDR),
......@@ -2601,6 +2601,7 @@ assign axi_grst = axi_rst_pre;
`else
.khz () // output // 1 KHz 50% output
`endif
/// ,.dbg_logger2023(dbg_logger2023) // ,output [3:0] dbg_logger2023
);
event_logger #(
......@@ -2661,6 +2662,7 @@ assign axi_grst = axi_rst_pre;
.data_out (logger_out), // output[15:0] @mclk
.data_out_stb (logger_stb), // output @mclk
.debug_state() // output[31:0]
// ,.dbg_logger2023 (dbg_logger2023) // ,input [3:0] dbg_logger2023
);
mult_saxi_wr_inbuf #(
......
x393_boson.bit
View file @ d7392a0f
No preview for this file type
x393_boson.timing_summary_impl
View file @ d7392a0f
This diff is collapsed.
x393_boson_utilization.report
View file @ d7392a0f
Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------
| Tool Version : Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017
| Date : Sun Apr 11 14:45:12 2021
| Date : Tue Feb 14 12:54:59 2023
| Host : elphel-desktop running 64-bit Ubuntu 14.04.5 LTS
| Command : report_utilization -file vivado_build/x393_boson_utilization.report
| Design : x393
......@@ -31,15 +31,15 @@ Table of Contents
+----------------------------+-------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+----------------------------+-------+-------+-----------+-------+
| Slice LUTs | 43475 | 0 | 78600 | 55.31 |
| LUT as Logic | 40095 | 0 | 78600 | 51.01 |
| LUT as Memory | 3380 | 0 | 26600 | 12.71 |
| LUT as Distributed RAM | 2834 | 0 | | |
| LUT as Shift Register | 546 | 0 | | |
| Slice Registers | 55965 | 0 | 157200 | 35.60 |
| Register as Flip Flop | 55965 | 0 | 157200 | 35.60 |
| Slice LUTs | 44058 | 0 | 78600 | 56.05 |
| LUT as Logic | 40644 | 0 | 78600 | 51.71 |
| LUT as Memory | 3414 | 0 | 26600 | 12.83 |
| LUT as Distributed RAM | 2866 | 0 | | |
| LUT as Shift Register | 548 | 0 | | |
| Slice Registers | 56108 | 0 | 157200 | 35.69 |
| Register as Flip Flop | 56108 | 0 | 157200 | 35.69 |
| Register as Latch | 0 | 0 | 157200 | 0.00 |
| F7 Muxes | 30 | 0 | 39300 | 0.08 |
| F7 Muxes | 54 | 0 | 39300 | 0.14 |
| F8 Muxes | 0 | 0 | 19650 | 0.00 |
+----------------------------+-------+-------+-----------+-------+
......@@ -57,9 +57,9 @@ Table of Contents
| 0 | _ | Reset | - |
| 0 | Yes | - | - |
| 16 | Yes | - | Set |
| 676 | Yes | - | Reset |
| 1219 | Yes | Set | - |
| 54054 | Yes | Reset | - |
| 677 | Yes | - | Reset |
| 1227 | Yes | Set | - |
| 54188 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
......@@ -69,27 +69,27 @@ Table of Contents
+-------------------------------------------+-------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------------------------------+-------+-------+-----------+-------+
| Slice | 17097 | 0 | 19650 | 87.01 |
| SLICEL | 11257 | 0 | | |
| SLICEM | 5840 | 0 | | |
| LUT as Logic | 40095 | 0 | 78600 | 51.01 |
| using O5 output only | 4 | | | |
| using O6 output only | 31207 | | | |
| using O5 and O6 | 8884 | | | |
| LUT as Memory | 3380 | 0 | 26600 | 12.71 |
| LUT as Distributed RAM | 2834 | 0 | | |
| Slice | 17145 | 0 | 19650 | 87.25 |
| SLICEL | 11293 | 0 | | |
| SLICEM | 5852 | 0 | | |
| LUT as Logic | 40644 | 0 | 78600 | 51.71 |
| using O5 output only | 3 | | | |
| using O6 output only | 31692 | | | |
| using O5 and O6 | 8949 | | | |
| LUT as Memory | 3414 | 0 | 26600 | 12.83 |
| LUT as Distributed RAM | 2866 | 0 | | |
| using O5 output only | 2 | | | |
| using O6 output only | 84 | | | |
| using O5 and O6 | 2748 | | | |
| LUT as Shift Register | 546 | 0 | | |
| using O5 output only | 276 | | | |
| using O6 output only | 108 | | | |
| using O5 and O6 | 2756 | | | |
| LUT as Shift Register | 548 | 0 | | |
| using O5 output only | 279 | | | |
| using O6 output only | 219 | | | |
| using O5 and O6 | 51 | | | |
| LUT Flip Flop Pairs | 25539 | 0 | 78600 | 32.49 |
| fully used LUT-FF pairs | 4875 | | | |
| LUT-FF pairs with one unused LUT output | 18503 | | | |
| LUT-FF pairs with one unused Flip Flop | 18221 | | | |
| Unique Control Sets | 4998 | | | |
| using O5 and O6 | 50 | | | |
| LUT Flip Flop Pairs | 25454 | 0 | 78600 | 32.38 |
| fully used LUT-FF pairs | 4849 | | | |
| LUT-FF pairs with one unused LUT output | 18445 | | | |
| LUT-FF pairs with one unused Flip Flop | 18119 | | | |
| Unique Control Sets | 5357 | | | |
+-------------------------------------------+-------+-------+-----------+-------+
* Note: Review the Control Sets Report for more information regarding control sets.
......@@ -197,29 +197,30 @@ Table of Contents
+------------------------+-------+----------------------+
| Ref Name | Used | Functional Category |
+------------------------+-------+----------------------+
| FDRE | 54054 | Flop & Latch |
| LUT3 | 11826 | LUT |
| LUT6 | 10403 | LUT |
| LUT2 | 8591 | LUT |
| LUT4 | 8302 | LUT |
| LUT5 | 8223 | LUT |
| RAMD32 | 4174 | Distributed Memory |
| FDRE | 54188 | Flop & Latch |
| LUT3 | 11920 | LUT |
| LUT6 | 10509 | LUT |
| LUT2 | 8692 | LUT |
| LUT4 | 8508 | LUT |
| LUT5 | 8334 | LUT |
| RAMD32 | 4186 | Distributed Memory |
| CARRY4 | 2805 | CarryLogic |
| LUT1 | 1634 | LUT |
| RAMS32 | 1408 | Distributed Memory |
| FDSE | 1219 | Flop & Latch |
| FDCE | 676 | Flop & Latch |
| SRL16E | 493 | Distributed Memory |
| LUT1 | 1630 | LUT |
| RAMS32 | 1412 | Distributed Memory |
| FDSE | 1227 | Flop & Latch |
| FDCE | 677 | Flop & Latch |
| SRL16E | 494 | Distributed Memory |
| SRLC32E | 104 | Distributed Memory |
| DSP48E1 | 76 | Block Arithmetic |
| RAMB18E1 | 74 | Block Memory |
| OBUFT | 69 | IO |
| RAMB36E1 | 54 | Block Memory |
| MUXF7 | 54 | MuxFx |
| IBUF | 51 | IO |
| OSERDESE2 | 43 | IO |
| ODELAYE2_FINEDELAY | 43 | IO |
| ISERDESE2 | 32 | IO |
| MUXF7 | 30 | MuxFx |
| RAMD64E | 24 | Distributed Memory |
| IBUFDS | 22 | IO |
| OBUFT_DCIEN | 18 | IO |
| IDELAYE2_FINEDELAY | 18 | IO |
......
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