merged with framepars, version 0x039300cc, fixing JPEG tail and timestamps in...

merged with framepars, version 0x039300cc, fixing JPEG tail and timestamps in various synchronization modes

merged with framepars, version 0x039300cc, fixing JPEG tail and timestamps in...
merged with framepars, version 0x039300cc, fixing JPEG tail and timestamps in various synchronization modes
d4027c5e · Andrey Filippov · 21542b07 · 87900556 · d4027c5e · d4027c5e
Commit d4027c5e authored Nov 14, 2016 by Andrey Filippov
24 changed files
--- a/cocotb/x393_cocotb_03.sav
+++ b/cocotb/x393_cocotb_03.sav
 [*]
 [*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
-[*] Fri Nov 11 01:29:13 2016
+[*] Mon Nov 14 07:51:42 2016
 [*]
-[dumpfile] "/home/eyesis/git/x393-neon/simulation/x393_dut-20161110163154297.fst"
-[dumpfile_mtime] "Thu Nov 10 23:50:11 2016"
-[dumpfile_size] 87931801
+[dumpfile] "/home/eyesis/git/x393-neon/simulation/x393_dut-20161114000442972.fst"
+[dumpfile_mtime] "Mon Nov 14 07:43:40 2016"
+[dumpfile_size] 300146089
 [savefile] "/home/eyesis/git/x393-neon/cocotb/x393_cocotb_03.sav"
-[timestart] 115612220
+[timestart] 240582030
 [size] 1814 1171
 [pos] 0 0
-*-13.676100 115658333 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+*-13.486365 240613470 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [treeopen] x393_dut.
 [treeopen] x393_dut.simul_sensor12bits_2_i.
 [treeopen] x393_dut.simul_sensor12bits_3_i.
 [treeopen] x393_dut.simul_sensor12bits_i.
 [treeopen] x393_dut.x393_i.
 [treeopen] x393_dut.x393_i.compressor393_i.
+[treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].
 [treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.
 [treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.
 [treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.
@@ -27,15 +28,19 @@
 [treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.
 [treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.huffman_stuffer_meta_i.
 [treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_27_32_i.
+[treeopen] x393_dut.x393_i.event_logger_i.
 [treeopen] x393_dut.x393_i.event_logger_i.i_imu_exttime.
 [treeopen] x393_dut.x393_i.event_logger_i.i_imu_exttime.timestamp_fifo_chn0_i.
 [treeopen] x393_dut.x393_i.event_logger_i.i_imu_spi.
+[treeopen] x393_dut.x393_i.event_logger_i.i_imu_timestamps.
 [treeopen] x393_dut.x393_i.event_logger_i.i_logger_arbiter.
 [treeopen] x393_dut.x393_i.event_logger_i.i_nmea_decoder.
 [treeopen] x393_dut.x393_i.event_logger_i.i_rs232_rcv.
 [treeopen] x393_dut.x393_i.frame_sequencer_block[0].
 [treeopen] x393_dut.x393_i.frame_sequencer_block[0].cmd_frame_sequencer_i.
 [treeopen] x393_dut.x393_i.mult_saxi_wr_i.mult_saxi_wr_pointers_i.
+[treeopen] x393_dut.x393_i.mult_saxi_wr_inbuf_i.
+[treeopen] x393_dut.x393_i.sensors393_i.
 [treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].
 [treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.
 [treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_sync_i.
@@ -49,11 +54,12 @@
 [treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.sens_sync_i.
 [treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[3].
 [treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.
-[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.sens_parallel12_i.
 [treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.sens_sync_i.
+[treeopen] x393_dut.x393_i.timing393_i.
 [treeopen] x393_dut.x393_i.timing393_i.camsync393_i.
+[treeopen] x393_dut.x393_i.timing393_i.camsync393_i.i_frsync_pclk0.
 [sst_width] 281
-[signals_width] 333
+[signals_width] 276
 [sst_expanded] 1
 [sst_vpaned_height] 486
 @820
@@ -266,7 +272,513 @@ x393_dut.x393_i.timing393_i.rtc393_i.refclk2x_mclk
 -clocks
 @c00200
 -synchronization
+-sens_sync
+@28
+x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_sync_i.trig
+x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sens_sync_i.trig
+x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.sens_sync_i.trig
+x393_dut.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.sens_sync_i.trig
+@1401200
+-sens_sync
+@28
+x393_dut.x393_i.timing393_i.camsync393_i.suppress_immediate_set_mclk
+x393_dut.x393_i.timing393_i.camsync393_i.suppress_immediate_set_pclk
+x393_dut.x393_i.timing393_i.camsync393_i.suppress_immediate
+@c00028
+x393_dut.x393_i.timing393_i.camsync393_i.start_pclk[2:0]
+@28
+(0)x393_dut.x393_i.timing393_i.camsync393_i.start_pclk[2:0]
+(1)x393_dut.x393_i.timing393_i.camsync393_i.start_pclk[2:0]
+(2)x393_dut.x393_i.timing393_i.camsync393_i.start_pclk[2:0]
+@1401200
+-group_end
+@28
+x393_dut.x393_i.timing393_i.camsync393_i.start_pclk2_masked
+x393_dut.x393_i.timing393_i.camsync393_i.set_period
+x393_dut.x393_i.timing393_i.camsync393_i.pre_start0
+x393_dut.x393_i.timing393_i.camsync393_i.start0
+x393_dut.x393_i.timing393_i.camsync393_i.start
+x393_dut.x393_i.timing393_i.camsync393_i.start_d
+x393_dut.x393_i.timing393_i.camsync393_i.start_en
+x393_dut.x393_i.timing393_i.camsync393_i.rep_en
+x393_dut.x393_i.timing393_i.camsync393_i.set_period
+@c00028
+x393_dut.x393_i.timing393_i.camsync393_i.ext_int_arm[1:0]
 @28
+(0)x393_dut.x393_i.timing393_i.camsync393_i.ext_int_arm[1:0]
+(1)x393_dut.x393_i.timing393_i.camsync393_i.ext_int_arm[1:0]
+x393_dut.x393_i.timing393_i.camsync393_i.ext_int_mode_mclk
+@1401200
+-group_end
+@800022
+x393_dut.x393_i.timing393_i.camsync393_i.trig_r[3:0]
+@28
+(0)x393_dut.x393_i.timing393_i.camsync393_i.trig_r[3:0]
+(1)x393_dut.x393_i.timing393_i.camsync393_i.trig_r[3:0]
+(2)x393_dut.x393_i.timing393_i.camsync393_i.trig_r[3:0]
+(3)x393_dut.x393_i.timing393_i.camsync393_i.trig_r[3:0]
+@1001200
+-group_end
+@c00022
+x393_dut.x393_i.timing393_i.camsync393_i.frame_sync[3:0]
+@28
+(0)x393_dut.x393_i.timing393_i.camsync393_i.frame_sync[3:0]
+(1)x393_dut.x393_i.timing393_i.camsync393_i.frame_sync[3:0]
+(2)x393_dut.x393_i.timing393_i.camsync393_i.frame_sync[3:0]
+(3)x393_dut.x393_i.timing393_i.camsync393_i.frame_sync[3:0]
+@1401200
+-group_end
+@c00022
+x393_dut.x393_i.timing393_i.camsync393_i.frsync_pclk[3:0]
+@28
+(0)x393_dut.x393_i.timing393_i.camsync393_i.frsync_pclk[3:0]
+(1)x393_dut.x393_i.timing393_i.camsync393_i.frsync_pclk[3:0]
+(2)x393_dut.x393_i.timing393_i.camsync393_i.frsync_pclk[3:0]
+(3)x393_dut.x393_i.timing393_i.camsync393_i.frsync_pclk[3:0]
+x393_dut.x393_i.timing393_i.camsync393_i.i_frsync_pclk0.src_clk
+x393_dut.x393_i.timing393_i.camsync393_i.i_frsync_pclk0.dst_clk
+x393_dut.x393_i.timing393_i.camsync393_i.en
+x393_dut.x393_i.timing393_i.camsync393_i.i_frsync_pclk0.rst
+x393_dut.x393_i.timing393_i.camsync393_i.i_frsync_pclk0.out_reg[2:0]
+@1401200
+-group_end
+@28
+x393_dut.x393_i.timing393_i.camsync393_i.start_en
+x393_dut.x393_i.timing393_i.camsync393_i.ts_incoming
+x393_dut.x393_i.timing393_i.camsync393_i.start_late_first
+x393_dut.x393_i.timing393_i.camsync393_i.start_late
+x393_dut.x393_i.timing393_i.camsync393_i.armed_internal_trigger
+x393_dut.x393_i.timing393_i.camsync393_i.start_dly
+[color] 2
+x393_dut.x393_i.timing393_i.camsync393_i.start_to_pclk
+@22
+x393_dut.x393_i.timing393_i.camsync393_i.restart_cntr[31:0]
+@28
+x393_dut.x393_i.timing393_i.camsync393_i.restart_cntr_run[1:0]
+[color] 2
+x393_dut.x393_i.timing393_i.camsync393_i.restart
+@800022
+[color] 3
+x393_dut.x393_i.timing393_i.camsync393_i.start_pclk[2:0]
+@28
+(0)x393_dut.x393_i.timing393_i.camsync393_i.start_pclk[2:0]
+(1)x393_dut.x393_i.timing393_i.camsync393_i.start_pclk[2:0]
+(2)x393_dut.x393_i.timing393_i.camsync393_i.start_pclk[2:0]
+@1001200
+-group_end
+@28
+x393_dut.x393_i.timing393_i.camsync393_i.ts_master_snap_pclk
+x393_dut.x393_i.timing393_i.camsync393_i.ts_master_snap
+x393_dut.x393_i.timing393_i.camsync393_i.ts_master_stb
+x393_dut.x393_i.timing393_i.camsync393_i.master_got
+x393_dut.x393_i.timing393_i.camsync393_i.master_got_pclk
+x393_dut.x393_i.timing393_i.camsync393_i.received_or_master
+x393_dut.x393_i.timing393_i.camsync393_i.start_early
+@800022
+x393_dut.x393_i.timing393_i.camsync393_i.frsync_pend[3:0]
+@28
+(0)x393_dut.x393_i.timing393_i.camsync393_i.frsync_pend[3:0]
+(1)x393_dut.x393_i.timing393_i.camsync393_i.frsync_pend[3:0]
+(2)x393_dut.x393_i.timing393_i.camsync393_i.frsync_pend[3:0]
+(3)x393_dut.x393_i.timing393_i.camsync393_i.frsync_pend[3:0]
+@1001200
+-group_end
+@28
+x393_dut.x393_i.timing393_i.camsync393_i.start_dly
+x393_dut.x393_i.timing393_i.camsync393_i.start_early
+x393_dut.x393_i.timing393_i.camsync393_i.received_or_master_pending
+@800022
+x393_dut.x393_i.timing393_i.camsync393_i.pending_latest[3:0]
+@28
+(0)x393_dut.x393_i.timing393_i.camsync393_i.pending_latest[3:0]
+(1)x393_dut.x393_i.timing393_i.camsync393_i.pending_latest[3:0]
+(2)x393_dut.x393_i.timing393_i.camsync393_i.pending_latest[3:0]
+(3)x393_dut.x393_i.timing393_i.camsync393_i.pending_latest[3:0]
+@1001200
+-group_end
+@800022
+x393_dut.x393_i.timing393_i.camsync393_i.ts_stb_pclk_r[3:0]
+@28
+(0)x393_dut.x393_i.timing393_i.camsync393_i.ts_stb_pclk_r[3:0]
+(1)x393_dut.x393_i.timing393_i.camsync393_i.ts_stb_pclk_r[3:0]
+(2)x393_dut.x393_i.timing393_i.camsync393_i.ts_stb_pclk_r[3:0]
+(3)x393_dut.x393_i.timing393_i.camsync393_i.ts_stb_pclk_r[3:0]
+@c00022
+x393_dut.x393_i.timing393_i.camsync393_i.ts_stb[3:0]
+@28
+(0)x393_dut.x393_i.timing393_i.camsync393_i.ts_stb[3:0]
+(1)x393_dut.x393_i.timing393_i.camsync393_i.ts_stb[3:0]
+(2)x393_dut.x393_i.timing393_i.camsync393_i.ts_stb[3:0]
+(3)x393_dut.x393_i.timing393_i.camsync393_i.ts_stb[3:0]
+@1401200
+-group_end
+@22
+x393_dut.x393_i.timing393_i.camsync393_i.chn_en[3:0]
+@28
+x393_dut.x393_i.timing393_i.camsync393_i.en
+x393_dut.x393_i.timing393_i.camsync393_i.en_pclk
+x393_dut.x393_i.timing393_i.camsync393_i.eprst
+@1001200
+-group_end
+@200
+-
+-senosrs
+@28
+x393_dut.x393_i.sensors393_i.trigger_mode
+@22
+x393_dut.x393_i.sensors393_i.trig_in[3:0]
+x393_dut.x393_i.sensors393_i.sof_out_mclk[3:0]
+@200
+-
+@28
+x393_dut.x393_i.timing393_i.camsync393_i.rcv_done
+x393_dut.x393_i.timing393_i.camsync393_i.master_got_pclk
+@c00022
+x393_dut.x393_i.timing393_i.frame_sync[3:0]
+@28
+(0)x393_dut.x393_i.timing393_i.frame_sync[3:0]
+(1)x393_dut.x393_i.timing393_i.frame_sync[3:0]
+(2)x393_dut.x393_i.timing393_i.frame_sync[3:0]
+(3)x393_dut.x393_i.timing393_i.frame_sync[3:0]
+@1401200
+-group_end
+@c00022
+x393_dut.x393_i.timing393_i.trig[3:0]
+@28
+(0)x393_dut.x393_i.timing393_i.trig[3:0]
+(1)x393_dut.x393_i.timing393_i.trig[3:0]
+(2)x393_dut.x393_i.timing393_i.trig[3:0]
+(3)x393_dut.x393_i.timing393_i.trig[3:0]
+@1401200
+-group_end
+@22
+x393_dut.x393_i.timing393_i.camsync393_i.dly_cntr_chn0[31:0]
+x393_dut.x393_i.timing393_i.camsync393_i.dly_cntr_chn1[31:0]
+x393_dut.x393_i.timing393_i.camsync393_i.dly_cntr_chn2[31:0]
+x393_dut.x393_i.timing393_i.camsync393_i.dly_cntr_chn3[31:0]
+@c00022
+x393_dut.x393_i.timing393_i.camsync393_i.dly_cntr_end[3:0]
+@28
+(0)x393_dut.x393_i.timing393_i.camsync393_i.dly_cntr_end[3:0]
+(1)x393_dut.x393_i.timing393_i.camsync393_i.dly_cntr_end[3:0]
+(2)x393_dut.x393_i.timing393_i.camsync393_i.dly_cntr_end[3:0]
+(3)x393_dut.x393_i.timing393_i.camsync393_i.dly_cntr_end[3:0]
+@1401200
+-group_end
+@c00022
+x393_dut.x393_i.timing393_i.camsync393_i.dly_cntr_run[3:0]
+@28
+(0)x393_dut.x393_i.timing393_i.camsync393_i.dly_cntr_run[3:0]
+(1)x393_dut.x393_i.timing393_i.camsync393_i.dly_cntr_run[3:0]
+(2)x393_dut.x393_i.timing393_i.camsync393_i.dly_cntr_run[3:0]
+(3)x393_dut.x393_i.timing393_i.camsync393_i.dly_cntr_run[3:0]
+@1401200
+-group_end
+@28
+x393_dut.x393_i.timing393_i.camsync393_i.start_late_first
+@800022
+x393_dut.x393_i.timing393_i.camsync393_i.trig_r[3:0]
+@28
+(0)x393_dut.x393_i.timing393_i.camsync393_i.trig_r[3:0]
+(1)x393_dut.x393_i.timing393_i.camsync393_i.trig_r[3:0]
+(2)x393_dut.x393_i.timing393_i.camsync393_i.trig_r[3:0]
+(3)x393_dut.x393_i.timing393_i.camsync393_i.trig_r[3:0]
+x393_dut.x393_i.timing393_i.camsync393_i.start_out_pulse
+@1001200
+-group_end
+@800028
+x393_dut.x393_i.timing393_i.camsync393_i.start_pclk[2:0]
+@28
+(0)x393_dut.x393_i.timing393_i.camsync393_i.start_pclk[2:0]
+(1)x393_dut.x393_i.timing393_i.camsync393_i.start_pclk[2:0]
+(2)x393_dut.x393_i.timing393_i.camsync393_i.start_pclk[2:0]
+@1001200
+-group_end
+@28
+x393_dut.x393_i.timing393_i.camsync393_i.master_got_pclk
+x393_dut.x393_i.timing393_i.camsync393_i.master_got
+@22
+x393_dut.x393_i.timing393_i.camsync393_i.local_got_pclk[3:0]
+@28
+x393_dut.x393_i.timing393_i.camsync393_i.start_en
+x393_dut.x393_i.timing393_i.camsync393_i.start_late
+x393_dut.x393_i.timing393_i.camsync393_i.pre_start_out_pulse
+x393_dut.x393_i.timing393_i.camsync393_i.start_out_pulse
+@c00022
+x393_dut.x393_i.timing393_i.camsync393_i.gpio_in[9:0]
+@28
+(0)x393_dut.x393_i.timing393_i.camsync393_i.gpio_in[9:0]
+(1)x393_dut.x393_i.timing393_i.camsync393_i.gpio_in[9:0]
+(2)x393_dut.x393_i.timing393_i.camsync393_i.gpio_in[9:0]
+(3)x393_dut.x393_i.timing393_i.camsync393_i.gpio_in[9:0]
+(4)x393_dut.x393_i.timing393_i.camsync393_i.gpio_in[9:0]
+(5)x393_dut.x393_i.timing393_i.camsync393_i.gpio_in[9:0]
+(6)x393_dut.x393_i.timing393_i.camsync393_i.gpio_in[9:0]
+(7)x393_dut.x393_i.timing393_i.camsync393_i.gpio_in[9:0]
+(8)x393_dut.x393_i.timing393_i.camsync393_i.gpio_in[9:0]
+(9)x393_dut.x393_i.timing393_i.camsync393_i.gpio_in[9:0]
+@1401200
+-group_end
+@c00022
+x393_dut.x393_i.timing393_i.camsync393_i.gpio_out[9:0]
+@28
+(0)x393_dut.x393_i.timing393_i.camsync393_i.gpio_out[9:0]
+(1)x393_dut.x393_i.timing393_i.camsync393_i.gpio_out[9:0]
+(2)x393_dut.x393_i.timing393_i.camsync393_i.gpio_out[9:0]
+(3)x393_dut.x393_i.timing393_i.camsync393_i.gpio_out[9:0]
+(4)x393_dut.x393_i.timing393_i.camsync393_i.gpio_out[9:0]
+(5)x393_dut.x393_i.timing393_i.camsync393_i.gpio_out[9:0]
+(6)x393_dut.x393_i.timing393_i.camsync393_i.gpio_out[9:0]
+(7)x393_dut.x393_i.timing393_i.camsync393_i.gpio_out[9:0]
+(8)x393_dut.x393_i.timing393_i.camsync393_i.gpio_out[9:0]
+(9)x393_dut.x393_i.timing393_i.camsync393_i.gpio_out[9:0]
+@1401200
+-group_end
+@c00022
+x393_dut.x393_i.timing393_i.camsync393_i.gpio_out_en[9:0]
+@28
+(0)x393_dut.x393_i.timing393_i.camsync393_i.gpio_out_en[9:0]
+(1)x393_dut.x393_i.timing393_i.camsync393_i.gpio_out_en[9:0]
+(2)x393_dut.x393_i.timing393_i.camsync393_i.gpio_out_en[9:0]
+(3)x393_dut.x393_i.timing393_i.camsync393_i.gpio_out_en[9:0]
+(4)x393_dut.x393_i.timing393_i.camsync393_i.gpio_out_en[9:0]
+(5)x393_dut.x393_i.timing393_i.camsync393_i.gpio_out_en[9:0]
+(6)x393_dut.x393_i.timing393_i.camsync393_i.gpio_out_en[9:0]
+(7)x393_dut.x393_i.timing393_i.camsync393_i.gpio_out_en[9:0]
+(8)x393_dut.x393_i.timing393_i.camsync393_i.gpio_out_en[9:0]
+(9)x393_dut.x393_i.timing393_i.camsync393_i.gpio_out_en[9:0]
+@1401200
+-group_end
+@28
+x393_dut.x393_i.timing393_i.camsync393_i.outsync
+x393_dut.x393_i.timing393_i.camsync393_i.out_data
+x393_dut.x393_i.timing393_i.camsync393_i.rcv_run
+x393_dut.x393_i.timing393_i.camsync393_i.start_dly
+x393_dut.x393_i.timing393_i.camsync393_i.triggered_mode_pclk
+@22
+x393_dut.x393_i.timing393_i.camsync393_i.dly_cntr_run[3:0]
+@28
+x393_dut.x393_i.timing393_i.camsync393_i.master_chn[1:0]
+x393_dut.x393_i.timing393_i.camsync393_i.set_trig_src_w
+x393_dut.x393_i.timing393_i.camsync393_i.trigger_condition
+x393_dut.x393_i.timing393_i.camsync393_i.set_period
+x393_dut.x393_i.timing393_i.camsync393_i.set_trig_dst_w
+x393_dut.x393_i.timing393_i.camsync393_i.trigger_condition_d
+x393_dut.x393_i.timing393_i.camsync393_i.pre_input_use_intern
+x393_dut.x393_i.timing393_i.camsync393_i.input_use_intern
+x393_dut.x393_i.timing393_i.camsync393_i.master_got_pclk
+x393_dut.x393_i.timing393_i.camsync393_i.ts_snd_en_pclk
+x393_dut.x393_i.timing393_i.camsync393_i.start_late
+x393_dut.x393_i.timing393_i.camsync393_i.start_late_first
+x393_dut.x393_i.timing393_i.camsync393_i.start_en
+@c00022
+x393_dut.x393_i.timing393_i.camsync393_i.dly_cntr_end[3:0]
+@28
+(0)x393_dut.x393_i.timing393_i.camsync393_i.dly_cntr_end[3:0]
+(1)x393_dut.x393_i.timing393_i.camsync393_i.dly_cntr_end[3:0]
+(2)x393_dut.x393_i.timing393_i.camsync393_i.dly_cntr_end[3:0]
+(3)x393_dut.x393_i.timing393_i.camsync393_i.dly_cntr_end[3:0]
+@1401200
+-group_end
+@c00022
+[color] 2
+x393_dut.x393_i.timing393_i.camsync393_i.trig_r[3:0]
+@28
+(0)x393_dut.x393_i.timing393_i.camsync393_i.trig_r[3:0]
+(1)x393_dut.x393_i.timing393_i.camsync393_i.trig_r[3:0]
+(2)x393_dut.x393_i.timing393_i.camsync393_i.trig_r[3:0]
+(3)x393_dut.x393_i.timing393_i.camsync393_i.trig_r[3:0]
+@1401200
+-group_end
+@22
+x393_dut.x393_i.timing393_i.camsync393_i.chn_en[3:0]
+@c00022
+x393_dut.x393_i.timing393_i.camsync393_i.ts_stb[3:0]
+@28
+(0)x393_dut.x393_i.timing393_i.camsync393_i.ts_stb[3:0]
+(1)x393_dut.x393_i.timing393_i.camsync393_i.ts_stb[3:0]
+(2)x393_dut.x393_i.timing393_i.camsync393_i.ts_stb[3:0]
+(3)x393_dut.x393_i.timing393_i.camsync393_i.ts_stb[3:0]
+@1401200
+-group_end
+@28
+x393_dut.x393_i.timing393_i.camsync393_i.ts_rcv_stb_chn0
+@22
+x393_dut.x393_i.timing393_i.camsync393_i.ts_rcv_data_chn0[7:0]
+@28
+x393_dut.x393_i.timing393_i.camsync393_i.ts_rcv_stb_chn1
+@22
+x393_dut.x393_i.timing393_i.camsync393_i.ts_rcv_data_chn1[7:0]
+@28
+x393_dut.x393_i.timing393_i.camsync393_i.ts_rcv_stb_chn2
+@c00022
+x393_dut.x393_i.timing393_i.camsync393_i.ts_rcv_data_chn2[7:0]
+@28
+(0)x393_dut.x393_i.timing393_i.camsync393_i.ts_rcv_data_chn2[7:0]
+(1)x393_dut.x393_i.timing393_i.camsync393_i.ts_rcv_data_chn2[7:0]
+(2)x393_dut.x393_i.timing393_i.camsync393_i.ts_rcv_data_chn2[7:0]
+(3)x393_dut.x393_i.timing393_i.camsync393_i.ts_rcv_data_chn2[7:0]
+(4)x393_dut.x393_i.timing393_i.camsync393_i.ts_rcv_data_chn2[7:0]
+(5)x393_dut.x393_i.timing393_i.camsync393_i.ts_rcv_data_chn2[7:0]
+(6)x393_dut.x393_i.timing393_i.camsync393_i.ts_rcv_data_chn2[7:0]
+(7)x393_dut.x393_i.timing393_i.camsync393_i.ts_rcv_data_chn2[7:0]
+@1401200
+-group_end
+@28
+x393_dut.x393_i.timing393_i.camsync393_i.ts_rcv_stb_chn3
+@c00022
+x393_dut.x393_i.timing393_i.camsync393_i.ts_rcv_data_chn3[7:0]
+@28
+(0)x393_dut.x393_i.timing393_i.camsync393_i.ts_rcv_data_chn3[7:0]
+(1)x393_dut.x393_i.timing393_i.camsync393_i.ts_rcv_data_chn3[7:0]
+(2)x393_dut.x393_i.timing393_i.camsync393_i.ts_rcv_data_chn3[7:0]
+(3)x393_dut.x393_i.timing393_i.camsync393_i.ts_rcv_data_chn3[7:0]
+(4)x393_dut.x393_i.timing393_i.camsync393_i.ts_rcv_data_chn3[7:0]
+(5)x393_dut.x393_i.timing393_i.camsync393_i.ts_rcv_data_chn3[7:0]
+(6)x393_dut.x393_i.timing393_i.camsync393_i.ts_rcv_data_chn3[7:0]
+(7)x393_dut.x393_i.timing393_i.camsync393_i.ts_rcv_data_chn3[7:0]
+@1401200
+-group_end
+@800200
+-ts_chn1
+@22
+x393_dut.x393_i.timing393_i.camsync393_i.ts_snd_sec[31:0]
+x393_dut.x393_i.timing393_i.camsync393_i.ts_rcv_sec_chn0[31:0]
+x393_dut.x393_i.timing393_i.camsync393_i.ts_rcv_sec_chn1[31:0]
+x393_dut.x393_i.timing393_i.camsync393_i.ts_rcv_sec_chn2[31:0]
+x393_dut.x393_i.timing393_i.camsync393_i.ts_rcv_sec_chn3[31:0]
+@200
+-
+@1000200
+-ts_chn1
+@28
+x393_dut.x393_i.timing393_i.camsync393_i.ts_external
+x393_dut.x393_i.timing393_i.camsync393_i.ts_external_m
+x393_dut.x393_i.timing393_i.camsync393_i.ts_external_pclk
+x393_dut.x393_i.timing393_i.camsync393_i.rcv_done
+x393_dut.x393_i.timing393_i.camsync393_i.ts_rcv_stb_chn0
+@22
+x393_dut.x393_i.timing393_i.camsync393_i.ts_rcv_usec_chn0[19:0]
+x393_dut.x393_i.timing393_i.camsync393_i.ts_rcv_sec_chn0[31:0]
+@200
+-
+@800022
+x393_dut.x393_i.timing393_i.camsync393_i.ts_snap_triggered[3:0]
+@28
+(0)x393_dut.x393_i.timing393_i.camsync393_i.ts_snap_triggered[3:0]
+(1)x393_dut.x393_i.timing393_i.camsync393_i.ts_snap_triggered[3:0]
+(2)x393_dut.x393_i.timing393_i.camsync393_i.ts_snap_triggered[3:0]
+(3)x393_dut.x393_i.timing393_i.camsync393_i.ts_snap_triggered[3:0]
+x393_dut.x393_i.timing393_i.camsync393_i.ts_snap_mclk_chn0
+@1001200
+-group_end
+@c00022
+x393_dut.x393_i.timing393_i.camsync393_i.ts_snap_triggered_mclk[3:0]
+@28
+(0)x393_dut.x393_i.timing393_i.camsync393_i.ts_snap_triggered_mclk[3:0]
+(1)x393_dut.x393_i.timing393_i.camsync393_i.ts_snap_triggered_mclk[3:0]
+(2)x393_dut.x393_i.timing393_i.camsync393_i.ts_snap_triggered_mclk[3:0]
+(3)x393_dut.x393_i.timing393_i.camsync393_i.ts_snap_triggered_mclk[3:0]
+@1401200
+-group_end
+@28
+x393_dut.x393_i.timing393_i.camsync393_i.triggered_mode
+x393_dut.x393_i.timing393_i.camsync393_i.ts_snap_mclk_chn0
+@c00022
+x393_dut.x393_i.timing393_i.camsync393_i.ts_snap_triggered[3:0]
+@28
+(0)x393_dut.x393_i.timing393_i.camsync393_i.ts_snap_triggered[3:0]
+(1)x393_dut.x393_i.timing393_i.camsync393_i.ts_snap_triggered[3:0]
+(2)x393_dut.x393_i.timing393_i.camsync393_i.ts_snap_triggered[3:0]
+(3)x393_dut.x393_i.timing393_i.camsync393_i.ts_snap_triggered[3:0]
+@1401200
+-group_end
+@28
+x393_dut.x393_i.timing393_i.camsync393_i.ts_master_stb
+x393_dut.x393_i.timing393_i.camsync393_i.ts_snd_stb_chn0
+x393_dut.x393_i.timing393_i.camsync393_i.ts_snd_stb_chn1
+x393_dut.x393_i.timing393_i.camsync393_i.ts_snd_stb_chn2
+x393_dut.x393_i.timing393_i.camsync393_i.ts_snd_stb_chn3
+x393_dut.x393_i.timing393_i.camsync393_i.master_got
+@800022
+x393_dut.x393_i.timing393_i.camsync393_i.local_got[3:0]
+@28
+(0)x393_dut.x393_i.timing393_i.camsync393_i.local_got[3:0]
+(1)x393_dut.x393_i.timing393_i.camsync393_i.local_got[3:0]
+(2)x393_dut.x393_i.timing393_i.camsync393_i.local_got[3:0]
+(3)x393_dut.x393_i.timing393_i.camsync393_i.local_got[3:0]
+@1001200
+-group_end
+@c00022
+x393_dut.x393_i.timing393_i.camsync393_i.ts_snd_sec_chn0[31:0]
+@28
+(0)x393_dut.x393_i.timing393_i.camsync393_i.ts_snd_sec_chn0[31:0]
+(1)x393_dut.x393_i.timing393_i.camsync393_i.ts_snd_sec_chn0[31:0]
+(2)x393_dut.x393_i.timing393_i.camsync393_i.ts_snd_sec_chn0[31:0]
+(3)x393_dut.x393_i.timing393_i.camsync393_i.ts_snd_sec_chn0[31:0]
+(4)x393_dut.x393_i.timing393_i.camsync393_i.ts_snd_sec_chn0[31:0]
+(5)x393_dut.x393_i.timing393_i.camsync393_i.ts_snd_sec_chn0[31:0]
+(6)x393_dut.x393_i.timing393_i.camsync393_i.ts_snd_sec_chn0[31:0]
+(7)x393_dut.x393_i.timing393_i.camsync393_i.ts_snd_sec_chn0[31:0]
+(8)x393_dut.x393_i.timing393_i.camsync393_i.ts_snd_sec_chn0[31:0]
+(9)x393_dut.x393_i.timing393_i.camsync393_i.ts_snd_sec_chn0[31:0]
+(10)x393_dut.x393_i.timing393_i.camsync393_i.ts_snd_sec_chn0[31:0]
+(11)x393_dut.x393_i.timing393_i.camsync393_i.ts_snd_sec_chn0[31:0]
+(12)x393_dut.x393_i.timing393_i.camsync393_i.ts_snd_sec_chn0[31:0]
+(13)x393_dut.x393_i.timing393_i.camsync393_i.ts_snd_sec_chn0[31:0]
+(14)x393_dut.x393_i.timing393_i.camsync393_i.ts_snd_sec_chn0[31:0]
+(15)x393_dut.x393_i.timing393_i.camsync393_i.ts_snd_sec_chn0[31:0]
+(16)x393_dut.x393_i.timing393_i.camsync393_i.ts_snd_sec_chn0[31:0]
+(17)x393_dut.x393_i.timing393_i.camsync393_i.ts_snd_sec_chn0[31:0]
+(18)x393_dut.x393_i.timing393_i.camsync393_i.ts_snd_sec_chn0[31:0]
+(19)x393_dut.x393_i.timing393_i.camsync393_i.ts_snd_sec_chn0[31:0]
+(20)x393_dut.x393_i.timing393_i.camsync393_i.ts_snd_sec_chn0[31:0]
+(21)x393_dut.x393_i.timing393_i.camsync393_i.ts_snd_sec_chn0[31:0]
+(22)x393_dut.x393_i.timing393_i.camsync393_i.ts_snd_sec_chn0[31:0]
+(23)x393_dut.x393_i.timing393_i.camsync393_i.ts_snd_sec_chn0[31:0]
+(24)x393_dut.x393_i.timing393_i.camsync393_i.ts_snd_sec_chn0[31:0]
+(25)x393_dut.x393_i.timing393_i.camsync393_i.ts_snd_sec_chn0[31:0]
+(26)x393_dut.x393_i.timing393_i.camsync393_i.ts_snd_sec_chn0[31:0]
+(27)x393_dut.x393_i.timing393_i.camsync393_i.ts_snd_sec_chn0[31:0]
+(28)x393_dut.x393_i.timing393_i.camsync393_i.ts_snd_sec_chn0[31:0]
+(29)x393_dut.x393_i.timing393_i.camsync393_i.ts_snd_sec_chn0[31:0]
+(30)x393_dut.x393_i.timing393_i.camsync393_i.ts_snd_sec_chn0[31:0]
+(31)x393_dut.x393_i.timing393_i.camsync393_i.ts_snd_sec_chn0[31:0]
+@1401200
+-group_end
+@22
+x393_dut.x393_i.timing393_i.camsync393_i.ts_snd_sec_chn1[31:0]
+x393_dut.x393_i.timing393_i.camsync393_i.ts_snd_sec_chn2[31:0]
+x393_dut.x393_i.timing393_i.camsync393_i.ts_snd_sec_chn3[31:0]
+x393_dut.x393_i.timing393_i.camsync393_i.ts_snd_sec[31:0]
+x393_dut.x393_i.timing393_i.camsync393_i.ts_snd_usec[19:0]
+@c00022
+x393_dut.x393_i.timing393_i.camsync393_i.dly_cntr_end[3:0]
+@28
+(0)x393_dut.x393_i.timing393_i.camsync393_i.dly_cntr_end[3:0]
+(1)x393_dut.x393_i.timing393_i.camsync393_i.dly_cntr_end[3:0]
+(2)x393_dut.x393_i.timing393_i.camsync393_i.dly_cntr_end[3:0]
+(3)x393_dut.x393_i.timing393_i.camsync393_i.dly_cntr_end[3:0]
+@1401200
+-group_end
+@28
+x393_dut.x393_i.timing393_i.camsync393_i.start_late
+x393_dut.x393_i.timing393_i.camsync393_i.start_out_pulse
+x393_dut.x393_i.timing393_i.camsync393_i.pre_start0
+x393_dut.x393_i.timing393_i.camsync393_i.set_trig_period_w
+x393_dut.x393_i.timing393_i.camsync393_i.start0
+x393_dut.x393_i.timing393_i.camsync393_i.start
+x393_dut.x393_i.timing393_i.camsync393_i.start_d
+@800028
+x393_dut.x393_i.timing393_i.camsync393_i.start_pclk[2:0]
+@28
+(0)x393_dut.x393_i.timing393_i.camsync393_i.start_pclk[2:0]
+(1)x393_dut.x393_i.timing393_i.camsync393_i.start_pclk[2:0]
+(2)x393_dut.x393_i.timing393_i.camsync393_i.start_pclk[2:0]
+@1001200
+-group_end
+@28
+x393_dut.x393_i.timing393_i.camsync393_i.start_to_pclk
 x393_dut.x393_i.timing393_i.camsync393_i.cmd_we
 x393_dut.x393_i.timing393_i.camsync393_i.set_mode_reg_w
 x393_dut.x393_i.timing393_i.camsync393_i.set_trig_delay0_w
@@ -317,6 +829,8 @@ x393_dut.x393_i.timing393_i.camsync393_i.ts_snd_stb_chn0
 x393_dut.x393_i.timing393_i.camsync393_i.ts_snd_stb_chn1
 x393_dut.x393_i.timing393_i.camsync393_i.ts_snd_stb_chn2
 x393_dut.x393_i.timing393_i.camsync393_i.ts_snd_stb_chn3
+[color] 2
+x393_dut.ODOMETER_PULSE
 @200
 -
 @c00022
@@ -839,23 +1353,23 @@ x393_dut.x393_i.event_logger_i.mclk
 x393_dut.x393_i.event_logger_i.mrst
 @200
 -x393
-@800022
+@c00022
 x393_dut.x393_i.sof_out_mclk[3:0]
 @28
 (0)x393_dut.x393_i.sof_out_mclk[3:0]
 (1)x393_dut.x393_i.sof_out_mclk[3:0]
 (2)x393_dut.x393_i.sof_out_mclk[3:0]
 (3)x393_dut.x393_i.sof_out_mclk[3:0]
-@1001200
+@1401200
 -group_end
-@800022
+@c00022
 x393_dut.x393_i.ts_pre_stb[3:0]
 @28
 (0)x393_dut.x393_i.ts_pre_stb[3:0]
 (1)x393_dut.x393_i.ts_pre_stb[3:0]
 (2)x393_dut.x393_i.ts_pre_stb[3:0]
 (3)x393_dut.x393_i.ts_pre_stb[3:0]
-@1001200
+@1401200
 -group_end
 @c00022
 x393_dut.x393_i.event_logger_i.ext_di[9:0]
@@ -998,7 +1512,7 @@ x393_dut.x393_i.event_logger_i.i_imu_spi.mclk
 @1401200
 -imu_spi393
 -group_end
-@800200
+@c00200
 -rs232_rcvr
 @28
 x393_dut.x393_i.axi_aclk
@@ -1128,9 +1642,9 @@ x393_dut.x393_i.event_logger_i.i_rs232_rcv.restart[1:0]
 x393_dut.x393_i.event_logger_i.i_rs232_rcv.reset_bit_duration
 @22
 x393_dut.x393_i.event_logger_i.i_rs232_rcv.bitHalfPeriod[15:0]
-@1000200
+@1401200
 -rs232_rcvr
-@800200
+@c00200
 -nmea_decoder
 @28
 x393_dut.x393_i.event_logger_i.i_nmea_decoder.start
@@ -1241,10 +1755,42 @@ x393_dut.x393_i.event_logger_i.i_nmea_decoder.nibble_count[6:0]
 -group_end
 @22
 x393_dut.x393_i.event_logger_i.i_nmea_decoder.nibble[3:0]
-@1000200
+@1401200
 -nmea_decoder
-@c00200
+@800200
 -imu_exttime
+@200
+-
+@28
+x393_dut.x393_i.event_logger_i.ts_stb_chn0
+x393_dut.x393_i.event_logger_i.ts_stb_chn1
+x393_dut.x393_i.event_logger_i.ts_stb_chn2
+x393_dut.x393_i.event_logger_i.ts_stb_chn3
+@22
+x393_dut.x393_i.event_logger_i.ts_data_chn0[7:0]
+x393_dut.x393_i.event_logger_i.ts_data_chn1[7:0]
+x393_dut.x393_i.event_logger_i.ts_data_chn2[7:0]
+x393_dut.x393_i.event_logger_i.ts_data_chn3[7:0]
+x393_dut.x393_i.event_logger_i.sof_mclk[3:0]
+x393_dut.x393_i.event_logger_i.enable_syn_mclk[3:0]
+@800022
+x393_dut.x393_i.event_logger_i.timestamps_en[3:0]
+@28
+(0)x393_dut.x393_i.event_logger_i.timestamps_en[3:0]
+(1)x393_dut.x393_i.event_logger_i.timestamps_en[3:0]
+(2)x393_dut.x393_i.event_logger_i.timestamps_en[3:0]
+(3)x393_dut.x393_i.event_logger_i.timestamps_en[3:0]
+@1001200
+-group_end
+@c00022
+x393_dut.x393_i.event_logger_i.i_imu_exttime.ts_stb[3:0]
+@28
+(0)x393_dut.x393_i.event_logger_i.i_imu_exttime.ts_stb[3:0]
+(1)x393_dut.x393_i.event_logger_i.i_imu_exttime.ts_stb[3:0]
+(2)x393_dut.x393_i.event_logger_i.i_imu_exttime.ts_stb[3:0]
+(3)x393_dut.x393_i.event_logger_i.i_imu_exttime.ts_stb[3:0]
+@1401200
+-group_end
 @28
 x393_dut.x393_i.event_logger_i.i_imu_exttime.mclk
 x393_dut.x393_i.event_logger_i.i_imu_exttime.mrst
@@ -1264,7 +1810,16 @@ x393_dut.x393_i.event_logger_i.i_imu_exttime.copy_data_r[7:0]
 x393_dut.x393_i.event_logger_i.i_imu_exttime.sel_chn[1:0]
 (1)x393_dut.x393_i.event_logger_i.i_imu_exttime.copy_selected[1:0]
 (2)x393_dut.x393_i.event_logger_i.i_imu_exttime.copy_cntr[2:0]
+@c00022
 x393_dut.x393_i.event_logger_i.i_imu_exttime.raddr[2:0]
+@28
+(0)x393_dut.x393_i.event_logger_i.i_imu_exttime.raddr[2:0]
+(1)x393_dut.x393_i.event_logger_i.i_imu_exttime.raddr[2:0]
+(2)x393_dut.x393_i.event_logger_i.i_imu_exttime.raddr[2:0]
+@1401200
+-group_end
+@28
+x393_dut.x393_i.event_logger_i.i_imu_exttime.rd_stb
 @c00022
 x393_dut.x393_i.event_logger_i.i_imu_exttime.rdata[15:0]
 @28
@@ -1288,15 +1843,6 @@ x393_dut.x393_i.event_logger_i.i_imu_exttime.rdata[15:0]
 -group_end
 @22
 x393_dut.x393_i.event_logger_i.i_imu_exttime.en_chn_mclk[3:0]
-@800022
-x393_dut.x393_i.event_logger_i.i_imu_exttime.ts_stb[3:0]
-@28
-(0)x393_dut.x393_i.event_logger_i.i_imu_exttime.ts_stb[3:0]
-(1)x393_dut.x393_i.event_logger_i.i_imu_exttime.ts_stb[3:0]
-(2)x393_dut.x393_i.event_logger_i.i_imu_exttime.ts_stb[3:0]
-(3)x393_dut.x393_i.event_logger_i.i_imu_exttime.ts_stb[3:0]
-@1001200
-group_end
 @c00022
 x393_dut.x393_i.event_logger_i.i_imu_exttime.ts_data_chn0[7:0]
 @28
@@ -1421,7 +1967,7 @@ x393_dut.x393_i.event_logger_i.i_imu_exttime.timestamp_fifo_chn0_i.rpntr[3:0]
 x393_dut.x393_i.event_logger_i.i_imu_exttime.timestamp_fifo_chn0_i.dout[7:0]
 @200
 -
-@1401200
+@1000200
 -imu_exttime
 @c00200
 -imu_spi
@@ -1513,10 +2059,29 @@ x393_dut.x393_i.event_logger_i.i_imu_spi.stall
 x393_dut.x393_i.event_logger_i.i_imu_spi.set_stall
 @1401200
 -imu_spi
-@c00200
+@800200
 -logger_arbiter
+@c00022
+x393_dut.x393_i.event_logger_i.i_logger_arbiter.ts_rq[3:0]
+@28
+(0)x393_dut.x393_i.event_logger_i.i_logger_arbiter.ts_rq[3:0]
+(1)x393_dut.x393_i.event_logger_i.i_logger_arbiter.ts_rq[3:0]
+(2)x393_dut.x393_i.event_logger_i.i_logger_arbiter.ts_rq[3:0]
+(3)x393_dut.x393_i.event_logger_i.i_logger_arbiter.ts_rq[3:0]
+@1401200
+-group_end
 @28
 x393_dut.x393_i.event_logger_i.i_logger_arbiter.rst
+@800022
+x393_dut.x393_i.event_logger_i.i_logger_arbiter.ts_grant[3:0]
+@28
+(0)x393_dut.x393_i.event_logger_i.i_logger_arbiter.ts_grant[3:0]
+(1)x393_dut.x393_i.event_logger_i.i_logger_arbiter.ts_grant[3:0]
+(2)x393_dut.x393_i.event_logger_i.i_logger_arbiter.ts_grant[3:0]
+(3)x393_dut.x393_i.event_logger_i.i_logger_arbiter.ts_grant[3:0]
+@1001200
+-group_end
+@28
 x393_dut.x393_i.event_logger_i.i_logger_arbiter.xclk
 @c00022
 x393_dut.x393_i.event_logger_i.i_logger_arbiter.rdy[3:0]
@@ -1554,8 +2119,16 @@ x393_dut.x393_i.event_logger_i.i_logger_arbiter.ts_grant[3:0]
 (3)x393_dut.x393_i.event_logger_i.i_logger_arbiter.ts_grant[3:0]
 @1401200
 -group_end
-@22
+@800022
 x393_dut.x393_i.event_logger_i.i_logger_arbiter.ts_valid[3:0]
+@28
+(0)x393_dut.x393_i.event_logger_i.i_logger_arbiter.ts_valid[3:0]
+(1)x393_dut.x393_i.event_logger_i.i_logger_arbiter.ts_valid[3:0]
+(2)x393_dut.x393_i.event_logger_i.i_logger_arbiter.ts_valid[3:0]
+(3)x393_dut.x393_i.event_logger_i.i_logger_arbiter.ts_valid[3:0]
+@1001200
+-group_end
+@22
 x393_dut.x393_i.event_logger_i.i_logger_arbiter.chn_servicing[3:0]
 @28
 x393_dut.x393_i.event_logger_i.i_logger_arbiter.ts_en
@@ -1593,7 +2166,11 @@ x393_dut.x393_i.event_logger_i.i_logger_arbiter.seq_cntr_last
 -group_end
 @28
 x393_dut.x393_i.event_logger_i.i_logger_arbiter.channel[1:0]
+x393_dut.x393_i.event_logger_i.i_logger_arbiter.ts_sel[1:0]
+x393_dut.x393_i.event_logger_i.i_logger_arbiter.ts_en_r
+x393_dut.x393_i.event_logger_i.i_logger_arbiter.wstart
 @22
+x393_dut.x393_i.event_logger_i.i_logger_arbiter.seq_cntr[4:0]
 x393_dut.x393_i.event_logger_i.i_logger_arbiter.sample_counter[23:0]
 @28
 x393_dut.x393_i.event_logger_i.i_logger_arbiter.dv
@@ -1604,9 +2181,114 @@ x393_dut.x393_i.event_logger_i.i_logger_arbiter.chn_servicing[3:0]
 @28
 x393_dut.x393_i.event_logger_i.i_logger_arbiter.wstart
 x393_dut.x393_i.event_logger_i.i_logger_arbiter.chn1hot[3:1]
-@1401200
+@1000200
 -logger_arbiter
+@800200
+-imu_timestamps
+@200
+-caller
+@22
+x393_dut.x393_i.event_logger_i.channel[1:0]
+@28
+x393_dut.x393_i.event_logger_i.timestamp_sel[1:0]
+@200
+-
+@28
+x393_dut.x393_i.event_logger_i.i_imu_timestamps.xclk
+x393_dut.x393_i.event_logger_i.i_imu_timestamps.ts_rcv
+@800022
+x393_dut.x393_i.event_logger_i.i_imu_timestamps.cntr[2:0]
+@28
+(0)x393_dut.x393_i.event_logger_i.i_imu_timestamps.cntr[2:0]
+(1)x393_dut.x393_i.event_logger_i.i_imu_timestamps.cntr[2:0]
+(2)x393_dut.x393_i.event_logger_i.i_imu_timestamps.cntr[2:0]
+@1001200
+-group_end
+@28
+x393_dut.x393_i.event_logger_i.i_imu_timestamps.rst
+x393_dut.x393_i.event_logger_i.i_imu_timestamps.pre_snap
+x393_dut.x393_i.event_logger_i.i_imu_timestamps.ts_snap
+x393_dut.x393_i.event_logger_i.i_imu_timestamps.ts_stb
+@22
+x393_dut.x393_i.event_logger_i.i_imu_timestamps.ts_data[7:0]
+@c00022
+x393_dut.x393_i.event_logger_i.i_imu_timestamps.ra[3:0]
+@28
+(0)x393_dut.x393_i.event_logger_i.i_imu_timestamps.ra[3:0]
+(1)x393_dut.x393_i.event_logger_i.i_imu_timestamps.ra[3:0]
+(2)x393_dut.x393_i.event_logger_i.i_imu_timestamps.ra[3:0]
+(3)x393_dut.x393_i.event_logger_i.i_imu_timestamps.ra[3:0]
+@1401200
+-group_end
+@22
+x393_dut.x393_i.event_logger_i.i_imu_timestamps.dout[15:0]
+@28
+x393_dut.x393_i.event_logger_i.i_imu_timestamps.ts_busy
+@800022
+x393_dut.x393_i.event_logger_i.i_imu_timestamps.ts_rq[3:0]
+@28
+(0)x393_dut.x393_i.event_logger_i.i_imu_timestamps.ts_rq[3:0]
+(1)x393_dut.x393_i.event_logger_i.i_imu_timestamps.ts_rq[3:0]
+(2)x393_dut.x393_i.event_logger_i.i_imu_timestamps.ts_rq[3:0]
+(3)x393_dut.x393_i.event_logger_i.i_imu_timestamps.ts_rq[3:0]
+@1001200
+-group_end
+@c00022
+x393_dut.x393_i.event_logger_i.i_imu_timestamps.ts_ackn[3:0]
+@28
+(0)x393_dut.x393_i.event_logger_i.i_imu_timestamps.ts_ackn[3:0]
+(1)x393_dut.x393_i.event_logger_i.i_imu_timestamps.ts_ackn[3:0]
+(2)x393_dut.x393_i.event_logger_i.i_imu_timestamps.ts_ackn[3:0]
+(3)x393_dut.x393_i.event_logger_i.i_imu_timestamps.ts_ackn[3:0]
+@1401200
+-group_end
+@22
+x393_dut.x393_i.event_logger_i.i_imu_timestamps.dout[15:0]
+@200
+-
+@1000200
+-imu_timestamps
+@c00022
+x393_dut.x393_i.event_logger_i.ext_di[9:0]
 @28
+(0)x393_dut.x393_i.event_logger_i.ext_di[9:0]
+(1)x393_dut.x393_i.event_logger_i.ext_di[9:0]
+(2)x393_dut.x393_i.event_logger_i.ext_di[9:0]
+(3)x393_dut.x393_i.event_logger_i.ext_di[9:0]
+(4)x393_dut.x393_i.event_logger_i.ext_di[9:0]
+(5)x393_dut.x393_i.event_logger_i.ext_di[9:0]
+(6)x393_dut.x393_i.event_logger_i.ext_di[9:0]
+(7)x393_dut.x393_i.event_logger_i.ext_di[9:0]
+(8)x393_dut.x393_i.event_logger_i.ext_di[9:0]
+(9)x393_dut.x393_i.event_logger_i.ext_di[9:0]
+@1401200
+-group_end
+@c00022
+x393_dut.x393_i.event_logger_i.ext_di16[15:0]
+@28
+(0)x393_dut.x393_i.event_logger_i.ext_di16[15:0]
+(1)x393_dut.x393_i.event_logger_i.ext_di16[15:0]
+(2)x393_dut.x393_i.event_logger_i.ext_di16[15:0]
+(3)x393_dut.x393_i.event_logger_i.ext_di16[15:0]
+(4)x393_dut.x393_i.event_logger_i.ext_di16[15:0]
+(5)x393_dut.x393_i.event_logger_i.ext_di16[15:0]
+(6)x393_dut.x393_i.event_logger_i.ext_di16[15:0]
+(7)x393_dut.x393_i.event_logger_i.ext_di16[15:0]
+(8)x393_dut.x393_i.event_logger_i.ext_di16[15:0]
+(9)x393_dut.x393_i.event_logger_i.ext_di16[15:0]
+(10)x393_dut.x393_i.event_logger_i.ext_di16[15:0]
+(11)x393_dut.x393_i.event_logger_i.ext_di16[15:0]
+(12)x393_dut.x393_i.event_logger_i.ext_di16[15:0]
+(13)x393_dut.x393_i.event_logger_i.ext_di16[15:0]
+(14)x393_dut.x393_i.event_logger_i.ext_di16[15:0]
+(15)x393_dut.x393_i.event_logger_i.ext_di16[15:0]
+@1401200
+-group_end
+@22
+x393_dut.x393_i.event_logger_i.config_msg[4:0]
+@28
+x393_dut.x393_i.event_logger_i.pre_message_trig
+x393_dut.x393_i.event_logger_i.message_trig
 x393_dut.x393_i.event_logger_i.gps_pulse1sec_single
 @c00022
 x393_dut.x393_i.event_logger_i.timestamp_request[3:0]
@@ -1695,6 +2377,9 @@ x393_dut.x393_i.event_logger_i.data_out_stb
 @22
 [color] 3
 x393_dut.x393_i.event_logger_i.sample_counter[23:0]
+@28
+x393_dut.GPS1SEC
+x393_dut.ODOMETER_PULSE
 @c00200
 -x393
 @22
@@ -1703,8 +2388,26 @@ x393_dut.x393_i.logger_out[15:0]
 x393_dut.x393_i.logger_stb
 @1401200
 -x393
+@800200
+-buf_xclk_mclk
+@1000200
+-buf_xclk_mclk
+@28
+x393_dut.x393_i.event_logger_i.mux_data_valid
+x393_dut.x393_i.event_logger_i.ts_en
+@22
+x393_dut.x393_i.event_logger_i.timestamps_rdata[15:0]
+x393_dut.x393_i.event_logger_i.mux_data_final[15:0]
+x393_dut.x393_i.event_logger_i.data_out[15:0]
+@28
+x393_dut.x393_i.event_logger_i.data_out_stb
+@1401200
 -event_logger
-@c00200
+@28
+x393_dut.x393_i.logger_stb
+@22
+x393_dut.x393_i.logger_out[15:0]
+@800200
 -mult_saxi_wr_inbuf
 @28
 x393_dut.x393_i.mult_saxi_wr_inbuf_i.mclk
@@ -1715,9 +2418,10 @@ x393_dut.x393_i.mult_saxi_wr_inbuf_i.data_in[15:0]
 x393_dut.x393_i.mult_saxi_wr_inbuf_i.valid
 x393_dut.x393_i.mult_saxi_wr_inbuf_i.has_burst
 x393_dut.x393_i.mult_saxi_wr_inbuf_i.read_burst
+x393_dut.x393_i.mult_saxi_wr_inbuf_i.pre_valid_chn
 @22
 x393_dut.x393_i.mult_saxi_wr_inbuf_i.data_out[31:0]
-@1401200
+@1000200
 -mult_saxi_wr_inbuf
 @c00200
 -mult_saxi_wr
@@ -2085,20 +2789,15 @@ x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.huffman_stuf
 x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_27_32_i.pre_bits_out_w[4:0]
 x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_27_32_i.early_length[5:0]
 x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_27_32_i.dlen1[5:0]
+@23
 x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_27_32_i.dlen2[5:0]
 @800028
 x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_27_32_i.stage[1:0]
 @28
 (0)x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_27_32_i.stage[1:0]
 (1)x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_27_32_i.stage[1:0]
-@800028
-x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_27_32_i.ds_stage[1:0]
-@28
-(0)x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_27_32_i.ds_stage[1:0]
-(1)x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_27_32_i.ds_stage[1:0]
 @1001200
 -group_end
-group_end
 @200
 -
 @1000200
@@ -2175,13 +2874,6 @@ x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.huffman_stuf
 @28
 (0)x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_27_32_i.stage[1:0]
 (1)x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_27_32_i.stage[1:0]
-@800029
-x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_27_32_i.ds_stage[1:0]
-@29
-(0)x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_27_32_i.ds_stage[1:0]
-(1)x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_27_32_i.ds_stage[1:0]
-@1001201
-group_end
 @1001200
 -group_end
 @200
@@ -2189,5 +2881,47 @@ x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.huffman_stuf
 @1000200
 -bit_stuffer
 -jpeg2
+@c00200
+-jpeg0
+@22
+x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.data_out[31:0]
+x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.data_out_valid
+x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.stuffer_do32[31:0]
+x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.stuffer_bytes[1:0]
+x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.stuffer_dv
+@800200
+-bit_stuffer
+@22
+x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_27_32_i.xclk
+x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_27_32_i.d_out[31:0]
+x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_27_32_i.dv
+x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_27_32_i.bytes_out[1:0]
+x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_27_32_i.flush_in
+@28
+(1)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_27_32_i.flush_stage[2:0]
+@c00022
+x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_27_32_i.flush_stage[2:0]
+@28
+(0)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_27_32_i.flush_stage[2:0]
+(1)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_27_32_i.flush_stage[2:0]
+(2)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_27_32_i.flush_stage[2:0]
+@1401200
+-group_end
+@22
+x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_27_32_i.flush_out
+x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_27_32_i.ds
+x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_27_32_i.din[26:0]
+x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_27_32_i.dlen[4:0]
+x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_27_32_i.early_length[5:0]
+x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_27_32_i.dlen1[5:0]
+x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_27_32_i.dlen2[5:0]
+x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_27_32_i.pre_bits_out_w[4:0]
+x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_27_32_i.stage[1:0]
+@200
+-
+@1000200
+-bit_stuffer
+@1401200
+-jpeg0
 [pattern_trace] 1
 [pattern_trace] 0
--- a/cocotb/x393_dut.v
+++ b/cocotb/x393_dut.v
@@ -1773,6 +1773,8 @@ assign x393_i.ps7_i.FCLKRESETN=     {RST,~RST,RST,~RST};

 `define TEST_IMU
 `define TEST_EXT_INT
+
+`define ODOMETER_PULSE_6
 assign #10 gpio_pins[7] = gpio_pins[8];
 `ifndef TEST_IMU
    assign #10 gpio_pins[9] = gpio_pins[6]; 
@@ -1922,7 +1924,9 @@ assign #10 gpio_pins[7] = gpio_pins[8];
      end
      assign gpio_pins[4]=SERIAL_BIT;
      assign gpio_pins[5]=GPS1SEC;
-//      assign gpio_pins[6]=ODOMETER_PULSE;
+`ifdef ODOMETER_PULSE_6
+      assign gpio_pins[6]=ODOMETER_PULSE;
+`endif
      assign gpio_pins[9]=ODOMETER_PULSE;
      oneshot i_oneshot  (.trigger(IMU_NMOSI),
                          .out(IMU_ACTIVE));

--- a/compressor_jp/bit_stuffer_27_32.v
+++ b/compressor_jp/bit_stuffer_27_32.v
@@ -71,7 +71,8 @@ module  bit_stuffer_27_32#(
 //    reg               flush_pend;
 //    wire              flush_ackn = flush_pend && !flush_stage[0] && !stage[0];
    // probably just a single unconditional flush_in delay (not to appear next after ds) will work
-    wire        [4:0] pre_bits_out_w = dlen2[4:0] + 5'h7; 
+//    wire        [4:0] pre_bits_out_w = dlen2[4:0] + 5'h7; 
+    wire        [5:0] pre_bits_out_w = {1'b0,dlen2[4:0]} + 6'h7; 

    assign d_out = data3[DATA3_LEN-1 -: 32];
    
@@ -165,8 +166,9 @@ module  bit_stuffer_27_32#(
            
        end

-//        dv <= (ds_stage[0] && dlen1[5]) || (flush_stage[1] && (|data3[DATA3_LEN-1 -: 32]));
-        dv <= (stage[0] && dlen1[5]) || (flush_stage[1] && (|data3[DATA3_LEN-1 -: 32])); // both ds and flush-caused (full 32-bit out if available)
+///        dv <= (stage[0] && dlen1[5]) || (flush_stage[1] && (|data3[DATA3_LEN-1 -: 32])); // both ds and flush-caused (full 32-bit out if available)
+ 
+        dv <= (stage[0] && dlen1[5]) || (flush_stage[1] && (|pre_bits_out_w[5:3])); // both ds and flush-caused (full 32-bit out if available)
 // no difference in number of cells
 //        if      (rst )                bytes_out <= 0; // if the dv was caused by 32 bits full - output 4 bytes
 //        else if (ds_stage[1])         bytes_out <= 0; // if the dv was caused by 32 bits full - output 4 bytes

--- a/fpga_version.vh
+++ b/fpga_version.vh
@@ -35,7 +35,9 @@
 * contains all the components and scripts required to completely simulate it
 * with at least one of the Free Software programs.
 */
-        parameter FPGA_VERSION =          32'h039300ca;      //parallel - and more ... -0.267/46, 80.42%
+        parameter FPGA_VERSION =          32'h039300cc;      //parallel - more jpeg tail -0.268/56, 80.24 %
+//      parameter FPGA_VERSION =          32'h039300cb;      //parallel - modifying trigger/timestamps -0.050/13 80.38%
+//      parameter FPGA_VERSION =          32'h039300ca;      //parallel - and more ... fixed -0.267/46, 80.42%
 //      parameter FPGA_VERSION =          32'h039300c9;      //parallel - trying more ...-0.123/32 79.82%
 //      parameter FPGA_VERSION =          32'h039300c8;      //parallel - trying to fix "premature..." -0.121/21, 80.2%
 //      parameter FPGA_VERSION =          32'h039300c7;      //parallel - disable SoF when channel disabled: met, 80.32%

--- a/includes/x393_simulation_parameters.vh
+++ b/includes/x393_simulation_parameters.vh
@@ -74,11 +74,18 @@
 //    parameter SENSOR_IMAGE_TYPE2 =       "NORM3",
 //    parameter SENSOR_IMAGE_TYPE3 =       "NORM4",

-    parameter SENSOR_IMAGE_TYPE0 =       "NORM1",
-    parameter SENSOR_IMAGE_TYPE1 =       "NORM2",
-    parameter SENSOR_IMAGE_TYPE2 =       "NORM3", // 4",
-    parameter SENSOR_IMAGE_TYPE3 =       "NORM3",
+//    parameter SENSOR_IMAGE_TYPE0 =       "NORM10",
+//    parameter SENSOR_IMAGE_TYPE1 =       "NORM10",
+//    parameter SENSOR_IMAGE_TYPE2 =       "NORM11", // 4",
+//    parameter SENSOR_IMAGE_TYPE3 =       "NORM12",
    
+    parameter SENSOR_IMAGE_TYPE0 =       "NORM13",
+    parameter SENSOR_IMAGE_TYPE1 =       "NORM13",
+    parameter SENSOR_IMAGE_TYPE2 =       "NORM14", // 4",
+    parameter SENSOR_IMAGE_TYPE3 =       "NORM15",
+    
+
+
    parameter SIMULATE_CMPRS_CMODE0 =     CMPRS_CBIT_CMODE_JPEG18,
    parameter SIMULATE_CMPRS_CMODE1 =     CMPRS_CBIT_CMODE_JPEG18,
    parameter SIMULATE_CMPRS_CMODE2 =     CMPRS_CBIT_CMODE_JP4,

--- a/input_data/sensor_05.dat
+++ b/input_data/sensor_05.dat
@@ -35,7 +35,7 @@
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 0f2 10e 24c 10e 1f6 375 316 19b 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 08b 15f 161 3a5 0b7 1a3 33f 30c 33f 30c 00c 208 05b 052 060 217 214 279 0f2 04f 0a3 025 0ea 278 0ea 278 133 112 3c6 076 0c7 26f 064 17f 202 2ba 08a 2f2 0f2 10e 
 13e 15d 2a3 180 047 197 174 034 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 129 3da 0f2 3e4 31e 101 167 3c9 167 3c9 0af 394 15c 063 2f3 212 306 0f8 17a 2ab 1b2 08b 0fc 276 0fc 276 0f4 243 2d7 355 3ec 1b4 07a 391 0d1 344 012 0f0 13e 15d 
-193 191 0d2 066 339 1d6 17c 1d2 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 108 036 0b0 3f7 3c3 03d 0f8 306 3dd 117 3ea 117 3ea 1ab 015 17e 310 1af 192 168 324 2fb 21d 382 2ae 3d7 219 3d7 219 24e 2a9 04a 312 07a 0bd 141 390 1d8 122 39b 2ea 193 191 
+193 191 0d2 066 339 1d6 17c 1d2 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 3f7 3c3 03d 0f8 306 3dd 117 3ea 117 3ea 1ab 015 17e 310 1af 192 168 324 2fb 21d 382 2ae 3d7 219 3d7 219 24e 2a9 04a 312 07a 0bd 141 390 1d8 122 39b 2ea 193 191 
 2f1 2aa 1da 2c1 3cb 132 02c 375 3b4 06a 2a8 08d 3c3 336 260 218 260 218 2a4 160 0f7 293 159 3fc 1f7 218 041 3e1 16f 336 351 071 351 071 000 08a 1c1 15b 194 198 23c 1fc 274 3a3 314 38e 27b 261 27b 261 241 344 11d 0ac 371 08c 3b9 27c 218 156 024 1e1 2f1 2aa 
 259 1a9 2bc 191 2ff 0ab 286 21c 2a1 2fa 0ff 37e 115 0d5 0c8 113 0c8 113 3c4 075 05b 27b 364 08d 027 3da 1fd 19f 359 00c 114 25d 114 25d 0ae 1f5 325 042 3a2 322 281 282 0e7 03e 166 02b 1e8 04e 1e8 04e 1cd 114 252 122 1d1 220 0e2 155 291 0de 2af 2d5 259 1a9 
 0c9 38c 076 1d6 1d4 140 188 2c9 37e 3b6 0ce 204 3a7 2b0 27a 232 27a 232 2fc 140 2a0 1c0 359 363 389 20a 273 332 1c4 35e 360 2ae 360 2ae 0b4 154 2ab 0c6 0d8 332 337 1b5 353 0ee 379 185 31e 0e0 31e 0e0 1f2 119 0e7 176 09b 278 1bc 11a 043 0bc 03a 2c7 0c9 38c 

--- a/input_data/sensor_06.dat
+++ b/input_data/sensor_06.dat
@@ -35,7 +35,7 @@
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 0f2 10e 24c 10e 1f6 375 316 19b 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 08b 15f 161 3a5 0b7 1a3 33f 30c 33f 30c 00c 208 05b 052 060 217 214 279 0f2 04f 0a3 025 0ea 278 0ea 278 133 112 3c6 076 0c7 26f 064 17f 202 2ba 08a 2f2 0f2 10e 
 13e 15d 2a3 180 047 197 174 034 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 129 3da 0f2 3e4 31e 101 167 3c9 167 3c9 0af 394 15c 063 2f3 212 306 0f8 17a 2ab 1b2 08b 0fc 276 0fc 276 0f4 243 2d7 355 3ec 1b4 07a 391 0d1 344 012 0f0 13e 15d 
-193 191 0d2 066 339 1d6 17c 1d2 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 108 036 0b0 3f7 3c3 03d 0f8 306 3dd 117 3ea 117 3ea 1ab 015 17e 310 1af 192 168 324 2fb 21d 382 2ae 3d7 219 3d7 219 24e 2a9 04a 312 07a 0bd 141 390 1d8 122 39b 2ea 193 191 
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 259 1a9 2bc 191 2ff 0ab 286 21c 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 027 3da 1fd 19f 359 00c 114 25d 114 25d 0ae 1f5 325 042 3a2 322 281 282 0e7 03e 166 02b 1e8 04e 1e8 04e 1cd 114 252 122 1d1 220 0e2 155 291 0de 2af 2d5 259 1a9 
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--- a/input_data/sensor_07.dat
+++ b/input_data/sensor_07.dat
@@ -35,7 +35,7 @@
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 0f2 10e 24c 10e 1f6 375 316 19b 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 08b 15f 161 3a5 0b7 1a3 33f 30c 33f 30c 00c 208 05b 052 060 217 214 279 0f2 04f 0a3 025 0ea 278 0ea 278 133 112 3c6 076 0c7 26f 064 17f 202 2ba 08a 2f2 0f2 10e 
 13e 15d 2a3 180 047 197 174 034 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 129 3da 0f2 3e4 31e 101 167 3c9 167 3c9 0af 394 15c 063 2f3 212 306 0f8 17a 2ab 1b2 08b 0fc 276 0fc 276 0f4 243 2d7 355 3ec 1b4 07a 391 0d1 344 012 0f0 13e 15d 
-193 191 0d2 066 339 1d6 17c 1d2 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 108 036 0b0 3f7 3c3 03d 0f8 306 3dd 117 3ea 117 3ea 1ab 015 17e 310 1af 192 168 324 2fb 21d 382 2ae 3d7 219 3d7 219 24e 2a9 04a 312 07a 0bd 141 390 1d8 122 39b 2ea 193 191 
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 259 1a9 2bc 191 2ff 0ab 286 21c 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 027 3da 1fd 19f 359 00c 114 25d 114 25d 0ae 1f5 325 042 3a2 322 281 282 0e7 03e 166 02b 1e8 04e 1e8 04e 1cd 114 252 122 1d1 220 0e2 155 291 0de 2af 2d5 259 1a9 
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--- a/input_data/sensor_08.dat
+++ b/input_data/sensor_08.dat
@@ -35,7 +35,7 @@
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--- a/input_data/sensor_09.dat
+++ b/input_data/sensor_09.dat
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+05b 2b8 358 253 0f2 22a 000 3c5 360 392 2ad 00a 2a7 274 0e1 1e1 0e1 1e1 15c 044 326 374 072 17b 117 1e4 157 329 3f3 295 070 361 070 361 2a1 2b1 127 194 1a3 335 000 0de 14d 0a6 368 07e 1e7 168 1e7 168 37c 09e 1eb 3ae 227 138 350 2e2 362 203 078 1d2 05b 2b8 
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+
+
+ 
--- a/input_data/sensor_10.dat
+++ b/input_data/sensor_10.dat
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+
+
+ 
--- a/input_data/sensor_11.dat
+++ b/input_data/sensor_11.dat
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+
+
+ 
--- a/input_data/sensor_12.dat
+++ b/input_data/sensor_12.dat
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+
+
+ 
--- a/input_data/sensor_13.dat
+++ b/input_data/sensor_13.dat
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+
+
+ 
--- a/input_data/sensor_14.dat
+++ b/input_data/sensor_14.dat
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+
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--- a/input_data/sensor_15.dat
+++ b/input_data/sensor_15.dat
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+3af 27e 30f 0ef 3dc 12c 3ba 258 265 243 35a 3c5 237 385 270 2f3 270 2f3 2bf 1dd 11c 152 398 1ca 2e8 032 330 360 20f 001 0eb 3af 0eb 3af 0b0 246 129 14e 335 041 39d 1c7 351 058 310 146 04f 3f1 04f 3f1 137 12f 2f9 044 124 200 3b9 167 092 032 0ac 0f6 3af 27e 
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+194 335 018 0ba 3c2 3a1 1e3 343 16d 3d5 2ae 1b1 0ba 325 218 063 218 063 305 1f3 222 265 3e6 248 138 1e9 010 2a7 283 3d0 208 2c2 208 2c2 2d2 2c6 2f1 220 247 271 2d5 2c5 05e 11a 113 263 380 2c6 380 2c6 3d6 239 121 1f4 39b 002 17a 0cc 06c 28e 3e0 081 194 335 
+095 369 363 050 0a7 207 376 040 15a 361 20d 187 35d 0d0 05a 3d3 05a 3d3 3cd 20d 277 37b 26b 16e 3a9 2e9 016 18a 0fe 2f2 0e3 162 0e3 162 069 176 086 074 20e 2d0 29b 0c8 25a 31a 337 38d 146 1a8 146 1a8 18b 18e 1c6 018 0f4 0ab 164 362 1ae 3bb 17c 043 095 369 
+39e 381 086 25a 22d 289 2b1 042 038 21a 3e5 1f2 041 3b9 2e4 267 2e4 267 3af 0dc 2ad 0ed 3d8 3d9 04c 155 3d4 142 0fa 192 148 368 148 368 259 31b 13c 166 1fe 2b5 3d2 278 14f 22f 21b 274 1d5 02f 1d5 02f 0d9 018 0cd 319 3b6 119 1ff 3e4 129 23e 318 001 39e 381 
+3b0 07e 082 3d9 154 229 095 049 308 100 137 3f2 065 0de 2b8 121 2b8 121 3a9 361 3c4 3bc 12f 289 01f 22f 04c 2cf 377 0af 036 1d3 036 1d3 1a2 0b4 213 1f4 317 31e 37a 0d4 23d 359 2c0 018 22d 35b 22d 35b 2c0 2d7 334 3f6 0e2 24b 04b 354 3dd 315 1b6 0bc 3b0 07e 
+1cb 360 058 1cd 31b 1e6 223 155 2c8 113 301 086 0cb 141 0d4 0ff 0d4 0ff 0bd 29a 2bc 0e8 36f 27e 024 275 27d 331 175 149 2ad 1a3 2ad 1a3 344 343 00b 320 259 10d 292 0de 224 399 227 179 34e 02c 34e 02c 040 2cb 1fd 3b1 176 143 148 2b1 2cb 342 254 374 1cb 360 
+2f0 128 106 136 084 2c0 059 066 079 354 245 0b0 272 1e0 23a 303 23a 303 3e9 388 095 171 397 0b9 159 329 367 368 3f4 060 1ac 3d7 1ac 3d7 03e 3c6 025 1e8 0c4 180 21c 395 204 3ed 14e 397 238 3a2 238 3a2 259 0f4 226 349 273 300 1f6 2fb 2f1 3c3 1f4 12a 2f0 128 
+01d 2d4 38d 314 28e 1b7 039 27c 11b 0c1 001 16f 25a 3bd 3e8 02b 3e8 02b 22f 32c 24f 257 2a9 238 0c0 149 009 074 3f4 2f3 235 171 235 171 192 33f 35f 34d 358 178 317 1f8 2dd 156 136 372 3eb 2bd 3eb 2bd 20b 251 0b1 3bd 0d9 081 355 132 150 19a 194 2dc 01d 2d4 
+253 165 0ee 067 238 3cb 2c1 096 1af 25b 137 3c2 183 3d6 2e0 179 2e0 179 08e 284 0ea 09a 1a3 3fc 357 1d7 165 355 275 204 147 370 147 370 03f 2ad 2ba 050 314 1f6 283 109 1af 0d4 2e0 20a 167 27e 167 27e 056 3e4 29c 20f 1a8 2c8 265 256 2e8 1c5 236 18b 253 165 
+292 1dc 227 22f 084 1fc 0f2 3b6 333 122 2e5 0ab 0ed 32d 020 3eb 020 3eb 005 292 166 13a 187 305 220 1d1 07a 10b 077 292 3e2 2d4 3e2 2d4 145 30f 336 1ef 0fa 3f8 160 1c7 37a 367 34a 05f 3ac 3e3 3ac 3e3 23a 2ac 0e9 33d 1e0 2d4 026 367 0b9 146 0d9 238 292 1dc 
+
+
+ 
--- a/logger/event_logger.v
+++ b/logger/event_logger.v
@@ -240,7 +240,7 @@ module  event_logger#(

    assign pre_message_trig = ext_di16[config_msg[3:0]];

-    assign message_trig= config_msg[4]^pre_message_trig;
+    assign message_trig= config_msg[4] ^ pre_message_trig;

    assign timestamp_request[1]=config_gps[3]? (config_gps[2]?nmea_sent_start:gps_ts_stb):gps_pulse1sec_single;
 

--- a/logger/imu_timestamps393.v
+++ b/logger/imu_timestamps393.v
@@ -51,6 +51,7 @@ module  imu_timestamps393(
    output                 [15:0] dout);// output data
    reg           ts_rcv;
    reg           ts_busy;
+    reg           ts_busy_d; 
    reg     [1:0] chn; // channel for which timestamp is bein requested/received
    wire    [3:0] rq_pri; // 1-hot prioritized timestamp request
    wire    [1:0] rq_enc; // encoded request channel
@@ -70,7 +71,7 @@ module  imu_timestamps393(
    assign rq_enc = {rq_pri[3] | rq_pri[2],
                     rq_pri[3] | rq_pri[1]};
                     
-    assign pre_snap = (|ts_rq) && !ts_busy; 
+    assign pre_snap = (|ts_rq) && !ts_busy && !ts_busy_d; 
    assign chn1hot = {chn[1] & chn[0], chn[1] & ~chn[0], ~chn[1] & chn[0], ~chn[1] & ~chn[0]};
    assign pre_ackn = ts_rcv && (cntr == 3'h6);
    
@@ -87,6 +88,8 @@ module  imu_timestamps393(
        else if (pre_snap)                 ts_busy <= 1;
        else if (ts_rcv && (cntr == 3'h6)) ts_busy <= 0; // adjust 6?
        
+        ts_busy_d <= ts_busy;
+        
        rcv_last <= ts_rcv && (cntr == 3'h6);
        
        if      (rst)       ts_rcv <= 0;

--- a/logger/logger_arbiter393.v
+++ b/logger/logger_arbiter393.v
@@ -129,8 +129,8 @@ module  logger_arbiter393(
    
        seq_cntr_last <= (seq_cntr[4:0]=='h1e);
    
-    
-        if      (wstart)              ts_en_r <=1'b1;
+        if      (rst)                 ts_en_r <=1'b0;
+        else if (wstart)              ts_en_r <=1'b1;
        else if (seq_cntr[1:0]==2'h3) ts_en_r <=1'b0;
        
        if (!ts_en_r) ts_sel_r[1:0] <= 2'h0;

--- a/py393/x393_jpeg.py
+++ b/py393/x393_jpeg.py
@@ -2401,6 +2401,496 @@ jpeg_sim_multi 4
 jpeg_sim_multi 4


+################## Simulate Parallel 13 - external trigger ####################
+./py393/test_mcntrl.py @py393/cocoargs  --simulated=localhost:7777
+measure_all "*DI"
+setup_all_sensors True None 0xf
+#set_sensor_io_ctl  all None None 1 # Set ARO low - check if it is still needed?
+
+#use EOF instead of SOF for i2c sequencer advance
+set_sensor_i2c_command  all  False  None  None  None None None None True
+
+#just testing
+set_gpio_ports  1   1 # enable software gpio pins and porta (camsync)
+set_gpio_pins 0 1 # pin 0 low, pin 1 - high
+
+set_logger_params_file "/home/eyesis/git/x393-neon/attic/imu_config.bin"
+
+
+
+##### write_control_register 0x480  0x400 # disable sensor chn 2
+
+
+
+reset_camsync_inout 1 # reset all outputs
+set_camsync_period 31 # set bit duration
+set_camsync_period  0 # disable
+set_camsync_delay 0 400
+set_camsync_delay 1 100
+set_camsync_delay 2 200
+set_camsync_delay 3 300
+#set_camsync_inout  <is_out>  <bit_number>  <active_positive>
+###set_camsync_inout  1  8  0
+###set_camsync_inout  0  7  0
+reset_camsync_inout  0 # start with internal trigger
+
+
+#set_camsync_mode  <en=None>  <en_snd=None>  <en_ts_external=None>  <triggered_mode=None>  <master_chn=None>  <chn_en=None> 
+set_camsync_mode  1 1 1 1 0 0xf
+set_camsync_period  8000 # 80 usec #and issue first trigger
+ 
+
+
+
+set_sensor_histogram_window  0  0  4  4  25 21
+set_sensor_histogram_window  1  0  4  4  41 21
+set_sensor_histogram_window  2  0  4  4  25 41
+set_sensor_histogram_window  3  0  4  4  41 41
+
+
+
+
+r
+read_control_register 0x430
+read_control_register 0x431
+write_cmd_frame_sequencer  0  1  2  0x600  0x48   # compressor q page = 1 // too late for frame 2
+set_qtables 0 0 80
+set_qtables 0 1 70
+
+#irq coming, image not changing - yes
+write_cmd_frame_sequencer  0  1  1 0x686 0x280005 #save 4 more lines than sensor has                                                                                                                                    
+write_cmd_frame_sequencer  0  1  1 0x680 0x5507 #enable abort
+#write_cmd_frame_sequencer  0  1  1 0x6c6 0x300006 #save 4 more lines that compressor has                                                                                                                                    
+
+write_cmd_frame_sequencer  0  1  2  0x600  0x5    #stop    compressor           `      
+write_cmd_frame_sequencer  0  1  2  0x680  0x5405 # stop  sensor memory         (+0) // sensor memory should be controlled first, (9 commands
+write_cmd_frame_sequencer  0  1  2  0x6c0  0x5c49 # stop compressor memory      (+0)
+
+write_cmd_frame_sequencer  0  1  3 0x686 0x240005 # correct lines                                                                                                   
+write_cmd_frame_sequencer  0  1  3  0x680  0x5507 # run sensor memory           (+1) Can not be 0
+
+write_cmd_frame_sequencer  0  1  4 0x686 0x280005 #save 4 more lines than sensor has                                                                                                                                    
+write_cmd_frame_sequencer  0  1  4 0x6c6 0x300006 #save more lines than compressor needs (sensor provides)                                                                                                                                    
+write_cmd_frame_sequencer  0  1  4  0x6c0  0x7d4b # run compressor memory       (+2)
+write_cmd_frame_sequencer  0  1  4  0x600  0x7    # run compressor              (+0)
+
+write_cmd_frame_sequencer  0  1  1  0x600  0x48   # compressor q page = 1
+write_cmd_frame_sequencer  0  1  4  0x600  0x40   # compressor q page = 0
+
+read_control_register 0x431
+read_control_register 0x430
+
+#testing histograms
+write_control_register 0x409 0xc0
+
+#set_sensor_io_dly_hispi all 0x48 0x68 0x68 0x68 0x68
+#set_sensor_io_ctl all None None None None None 1 None # load all delays?
+compressor_control  all  None  None  None None None  2
+compressor_interrupt_control all clr
+compressor_interrupt_control all en
+compressor_control  all  3
+r
+read_status 0x21
+r
+jpeg_sim_multi 4
+r
+read_status 0x21
+r
+jpeg_sim_multi 3
+r
+read_status 0x21
+r
+
+write_cmd_frame_sequencer  0  1  1 0x686 0x240005 # correct lines                                                                                                   
+write_cmd_frame_sequencer  0  1  1 0x6c6 0x200006 # correct lines                                                                                                                                    
+write_cmd_frame_sequencer  0  1  1  0x680  0x5507 # run sensor memory, update frame#, reset buffers
+write_cmd_frame_sequencer  0  1  1  0x6c0  0x7d4b # run compressor memory
+write_cmd_frame_sequencer  0  1  1  0x600  0x7    # run compressor
+
+#switch to external (wired) trigger
+
+jpeg_sim_multi 4
+
+### set_camsync_inout  0  9  0 # external/internal trigger mode
+
+
+###switch to external (wired) trigger
+##set_camsync_inout  0  7  0
+
+jpeg_sim_multi 4
+#set_camsync_mode  <en=None>  <en_snd=None>  <en_ts_external=None>  <triggered_mode=None>  <master_chn=None>  <chn_en=None> 
+jpeg_sim_multi 8
+
+###set_camsync_period  8000 # 80 usec - restart while waiting for external trigger
+jpeg_sim_multi 4
+
+jpeg_sim_multi 4
+
+################## Simulate Parallel 14 - external trigger ####################
+./py393/test_mcntrl.py @py393/cocoargs  --simulated=localhost:7777
+measure_all "*DI"
+setup_all_sensors True None 0xf
+#set_sensor_io_ctl  all None None 1 # Set ARO low - check if it is still needed?
+
+#use EOF instead of SOF for i2c sequencer advance
+set_sensor_i2c_command  all  False  None  None  None None None None True
+
+#just testing
+set_gpio_ports  1   1 # enable software gpio pins and porta (camsync)
+set_gpio_pins 0 1 # pin 0 low, pin 1 - high
+
+set_logger_params_file "/home/eyesis/git/x393-neon/attic/imu_config.bin"
+
+
+
+##### write_control_register 0x480  0x400 # disable sensor chn 2
+
+
+
+reset_camsync_inout 1 # reset all outputs
+set_camsync_period 31 # set bit duration
+set_camsync_period  10000 # 100 usec
+set_camsync_delay 0  400
+set_camsync_delay 1 1000
+set_camsync_delay 2 2000
+set_camsync_delay 3 2500
+#set_camsync_inout  <is_out>  <bit_number>  <active_positive>
+set_camsync_inout  1  8  0
+set_camsync_inout  0  7  0
+#reset_camsync_inout  0 # start with internal trigger
+
+
+#set_camsync_mode  <en=None>  <en_snd=None>  <en_ts_external=None>  <triggered_mode=None>  <master_chn=None>  <chn_en=None> 
+set_camsync_mode  1 1 1 1 0 0xf
+ 
+
+
+
+set_sensor_histogram_window  0  0  4  4  25 21
+set_sensor_histogram_window  1  0  4  4  41 21
+set_sensor_histogram_window  2  0  4  4  25 41
+set_sensor_histogram_window  3  0  4  4  41 41
+
+
+
+
+r
+read_control_register 0x430
+read_control_register 0x431
+write_cmd_frame_sequencer  0  1  2  0x600  0x48   # compressor q page = 1 // too late for frame 2
+set_qtables 0 0 80
+set_qtables 0 1 70
+
+#irq coming, image not changing - yes
+write_cmd_frame_sequencer  0  1  1 0x686 0x280005 #save 4 more lines than sensor has                                                                                                                                    
+write_cmd_frame_sequencer  0  1  1 0x680 0x5507 #enable abort
+#write_cmd_frame_sequencer  0  1  1 0x6c6 0x300006 #save 4 more lines that compressor has                                                                                                                                    
+
+write_cmd_frame_sequencer  0  1  2  0x600  0x5    #stop    compressor           `      
+write_cmd_frame_sequencer  0  1  2  0x680  0x5405 # stop  sensor memory         (+0) // sensor memory should be controlled first, (9 commands
+write_cmd_frame_sequencer  0  1  2  0x6c0  0x5c49 # stop compressor memory      (+0)
+
+write_cmd_frame_sequencer  0  1  3 0x686 0x240005 # correct lines                                                                                                   
+write_cmd_frame_sequencer  0  1  3  0x680  0x5507 # run sensor memory           (+1) Can not be 0
+
+write_cmd_frame_sequencer  0  1  4 0x686 0x280005 #save 4 more lines than sensor has                                                                                                                                    
+write_cmd_frame_sequencer  0  1  4 0x6c6 0x300006 #save more lines than compressor needs (sensor provides)                                                                                                                                    
+write_cmd_frame_sequencer  0  1  4  0x6c0  0x7d4b # run compressor memory       (+2)
+write_cmd_frame_sequencer  0  1  4  0x600  0x7    # run compressor              (+0)
+
+write_cmd_frame_sequencer  0  1  1  0x600  0x48   # compressor q page = 1
+write_cmd_frame_sequencer  0  1  4  0x600  0x40   # compressor q page = 0
+
+read_control_register 0x431
+read_control_register 0x430
+
+#testing histograms
+write_control_register 0x409 0xc0
+
+#set_sensor_io_dly_hispi all 0x48 0x68 0x68 0x68 0x68
+#set_sensor_io_ctl all None None None None None 1 None # load all delays?
+compressor_control  all  None  None  None None None  2
+compressor_interrupt_control all clr
+compressor_interrupt_control all en
+compressor_control  all  3
+r
+read_status 0x21
+r
+jpeg_sim_multi 4
+r
+read_status 0x21
+r
+jpeg_sim_multi 3
+r
+read_status 0x21
+r
+
+write_cmd_frame_sequencer  0  1  1 0x686 0x240005 # correct lines                                                                                                   
+write_cmd_frame_sequencer  0  1  1 0x6c6 0x200006 # correct lines                                                                                                                                    
+write_cmd_frame_sequencer  0  1  1  0x680  0x5507 # run sensor memory, update frame#, reset buffers
+write_cmd_frame_sequencer  0  1  1  0x6c0  0x7d4b # run compressor memory
+write_cmd_frame_sequencer  0  1  1  0x600  0x7    # run compressor
+
+#switch to external (wired) trigger
+
+jpeg_sim_multi 4
+
+set_camsync_inout  0  9  0 # external/internal trigger mode
+
+
+###switch to external (wired) trigger
+##set_camsync_inout  0  7  0
+
+jpeg_sim_multi 4
+#set_camsync_mode  <en=None>  <en_snd=None>  <en_ts_external=None>  <triggered_mode=None>  <master_chn=None>  <chn_en=None> 
+jpeg_sim_multi 8
+
+set_camsync_period  8000 # 80 usec - restart while waiting for external trigger
+jpeg_sim_multi 4
+
+jpeg_sim_multi 4
+
+################## Simulate Parallel 15 - internal trigger ####################
+./py393/test_mcntrl.py @py393/cocoargs  --simulated=localhost:7777
+measure_all "*DI"
+setup_all_sensors True None 0xf
+#set_sensor_io_ctl  all None None 1 # Set ARO low - check if it is still needed?
+
+#use EOF instead of SOF for i2c sequencer advance
+set_sensor_i2c_command  all  False  None  None  None None None None True
+
+#just testing
+set_gpio_ports  1   1 # enable software gpio pins and porta (camsync)
+set_gpio_pins 0 1 # pin 0 low, pin 1 - high
+
+set_logger_params_file "/home/eyesis/git/x393-neon/attic/imu_config.bin"
+
+##### write_control_register 0x480  0x400 # disable sensor chn 2
+
+reset_camsync_inout 1 # reset all outputs
+set_camsync_period 31 # set bit duration
+set_camsync_period  0 # disable
+set_camsync_delay 0 400
+set_camsync_delay 1 100
+set_camsync_delay 2 200
+set_camsync_delay 3 300
+#set_camsync_inout  <is_out>  <bit_number>  <active_positive>
+###set_camsync_inout  1  8  0
+###set_camsync_inout  0  7  0
+reset_camsync_inout  0 # start with internal trigger
+
+#set_camsync_mode  <en=None>  <en_snd=None>  <en_ts_external=None>  <triggered_mode=None>  <master_chn=None>  <chn_en=None> 
+set_camsync_mode  1 1 1 1 0 0xf
+set_camsync_period  0 # so next setting period will immadiately trigger
+set_camsync_period  8000 # 80 usec #and issue first trigger
+
+set_sensor_histogram_window  0  0  4  4  25 21
+set_sensor_histogram_window  1  0  4  4  41 21
+set_sensor_histogram_window  2  0  4  4  25 41
+set_sensor_histogram_window  3  0  4  4  41 41
+
+r
+read_control_register 0x430
+read_control_register 0x431
+write_cmd_frame_sequencer  0  1  2  0x600  0x48   # compressor q page = 1 // too late for frame 2
+set_qtables 0 0 80
+set_qtables 0 1 70
+
+#irq coming, image not changing - yes
+write_cmd_frame_sequencer  0  1  1 0x686 0x280005 #save 4 more lines than sensor has                                                                                                                                    
+write_cmd_frame_sequencer  0  1  1 0x680 0x5507 #enable abort
+#write_cmd_frame_sequencer  0  1  1 0x6c6 0x300006 #save 4 more lines that compressor has                                                                                                                                    
+
+write_cmd_frame_sequencer  0  1  2  0x600  0x5    #stop    compressor           `      
+write_cmd_frame_sequencer  0  1  2  0x680  0x5405 # stop  sensor memory         (+0) // sensor memory should be controlled first, (9 commands
+write_cmd_frame_sequencer  0  1  2  0x6c0  0x5c49 # stop compressor memory      (+0)
+
+write_cmd_frame_sequencer  0  1  3 0x686 0x240005 # correct lines                                                                                                   
+write_cmd_frame_sequencer  0  1  3  0x680  0x5507 # run sensor memory           (+1) Can not be 0
+
+write_cmd_frame_sequencer  0  1  4 0x686 0x280005 #save 4 more lines than sensor has                                                                                                                                    
+write_cmd_frame_sequencer  0  1  4 0x6c6 0x300006 #save more lines than compressor needs (sensor provides)                                                                                                                                    
+write_cmd_frame_sequencer  0  1  4  0x6c0  0x7d4b # run compressor memory       (+2)
+write_cmd_frame_sequencer  0  1  4  0x600  0x7    # run compressor              (+0)
+
+write_cmd_frame_sequencer  0  1  1  0x600  0x48   # compressor q page = 1
+write_cmd_frame_sequencer  0  1  4  0x600  0x40   # compressor q page = 0
+
+read_control_register 0x431
+read_control_register 0x430
+
+#testing histograms
+write_control_register 0x409 0xc0
+
+#set_sensor_io_dly_hispi all 0x48 0x68 0x68 0x68 0x68
+#set_sensor_io_ctl all None None None None None 1 None # load all delays?
+compressor_control  all  None  None  None None None  2
+compressor_interrupt_control all clr
+compressor_interrupt_control all en
+compressor_control  all  3
+r
+read_status 0x21
+r
+jpeg_sim_multi 4
+
+set_camsync_period  9000 # 90 usec # change period, skip first trigger
+
+r
+read_status 0x21
+r
+jpeg_sim_multi 3
+r
+read_status 0x21
+r
+
+write_cmd_frame_sequencer  0  1  1 0x686 0x240005 # correct lines                                                                                                   
+write_cmd_frame_sequencer  0  1  1 0x6c6 0x200006 # correct lines                                                                                                                                    
+write_cmd_frame_sequencer  0  1  1  0x680  0x5507 # run sensor memory, update frame#, reset buffers
+write_cmd_frame_sequencer  0  1  1  0x6c0  0x7d4b # run compressor memory
+write_cmd_frame_sequencer  0  1  1  0x600  0x7    # run compressor
+
+#switch to external (wired) trigger
+
+jpeg_sim_multi 4
+
+### set_camsync_inout  0  9  0 # external/internal trigger mode
+
+
+###switch to external (wired) trigger
+##set_camsync_inout  0  7  0
+
+jpeg_sim_multi 4
+#set_camsync_mode  <en=None>  <en_snd=None>  <en_ts_external=None>  <triggered_mode=None>  <master_chn=None>  <chn_en=None> 
+jpeg_sim_multi 8
+
+###set_camsync_period  8000 # 80 usec - restart while waiting for external trigger
+jpeg_sim_multi 4
+
+jpeg_sim_multi 4
+
+################## Simulate Parallel 16 - free running (all the same, but keep free running mode) ####################
+./py393/test_mcntrl.py @py393/cocoargs  --simulated=localhost:7777
+measure_all "*DI"
+setup_all_sensors True None 0xf
+#Setting ARO for free run mode? 
+set_sensor_io_ctl  all None None 1 # Set ARO low - check if it is still needed?
+
+#use EOF instead of SOF for i2c sequencer advance
+set_sensor_i2c_command  all  False  None  None  None None None None True
+
+#just testing
+set_gpio_ports  1   1 # enable software gpio pins and porta (camsync)
+set_gpio_pins 0 1 # pin 0 low, pin 1 - high
+
+set_logger_params_file "/home/eyesis/git/x393-neon/attic/imu_config.bin"
+
+##### write_control_register 0x480  0x400 # disable sensor chn 2
+
+reset_camsync_inout 1 # reset all outputs
+set_camsync_period 31 # set bit duration
+set_camsync_period  0 # disable
+set_camsync_delay 0 400
+set_camsync_delay 1 100
+set_camsync_delay 2 200
+set_camsync_delay 3 300
+#set_camsync_inout  <is_out>  <bit_number>  <active_positive>
+###set_camsync_inout  1  8  0
+###set_camsync_inout  0  7  0
+reset_camsync_inout  0 # start with internal trigger
+
+#set_camsync_mode  <en=None>  <en_snd=None>  <en_ts_external=None>  <triggered_mode=None>  <master_chn=None>  <chn_en=None>
+ 
+#### set_camsync_mode  1 1 1 1 0 0xf # keep
+     set_camsync_mode  1 1 1 0 0 0xf # keep free running mode, do not switch to triggered
+
+set_camsync_period  0 # so next setting period will immadiately trigger
+set_camsync_period  8000 # 80 usec #and issue first trigger
+
+set_sensor_histogram_window  0  0  4  4  25 21
+set_sensor_histogram_window  1  0  4  4  41 21
+set_sensor_histogram_window  2  0  4  4  25 41
+set_sensor_histogram_window  3  0  4  4  41 41
+
+r
+read_control_register 0x430
+read_control_register 0x431
+write_cmd_frame_sequencer  0  1  2  0x600  0x48   # compressor q page = 1 // too late for frame 2
+set_qtables 0 0 80
+set_qtables 0 1 70
+
+#irq coming, image not changing - yes
+write_cmd_frame_sequencer  0  1  1 0x686 0x280005 #save 4 more lines than sensor has                                                                                                                                    
+write_cmd_frame_sequencer  0  1  1 0x680 0x5507 #enable abort
+#write_cmd_frame_sequencer  0  1  1 0x6c6 0x300006 #save 4 more lines that compressor has                                                                                                                                    
+
+write_cmd_frame_sequencer  0  1  2  0x600  0x5    #stop    compressor           `      
+write_cmd_frame_sequencer  0  1  2  0x680  0x5405 # stop  sensor memory         (+0) // sensor memory should be controlled first, (9 commands
+write_cmd_frame_sequencer  0  1  2  0x6c0  0x5c49 # stop compressor memory      (+0)
+
+write_cmd_frame_sequencer  0  1  3 0x686 0x240005 # correct lines                                                                                                   
+write_cmd_frame_sequencer  0  1  3  0x680  0x5507 # run sensor memory           (+1) Can not be 0
+
+write_cmd_frame_sequencer  0  1  4 0x686 0x280005 #save 4 more lines than sensor has                                                                                                                                    
+write_cmd_frame_sequencer  0  1  4 0x6c6 0x300006 #save more lines than compressor needs (sensor provides)                                                                                                                                    
+write_cmd_frame_sequencer  0  1  4  0x6c0  0x7d4b # run compressor memory       (+2)
+write_cmd_frame_sequencer  0  1  4  0x600  0x7    # run compressor              (+0)
+
+write_cmd_frame_sequencer  0  1  1  0x600  0x48   # compressor q page = 1
+write_cmd_frame_sequencer  0  1  4  0x600  0x40   # compressor q page = 0
+
+read_control_register 0x431
+read_control_register 0x430
+
+#testing histograms
+write_control_register 0x409 0xc0
+
+#set_sensor_io_dly_hispi all 0x48 0x68 0x68 0x68 0x68
+#set_sensor_io_ctl all None None None None None 1 None # load all delays?
+compressor_control  all  None  None  None None None  2
+compressor_interrupt_control all clr
+compressor_interrupt_control all en
+compressor_control  all  3
+r
+read_status 0x21
+r
+
+#set_sensor_lens_flat_parameters  <num_sensor>  <num_sub_sensor>  <AX=None>  <AY=None>  <BX=None>  <BY=None>  <C=None>  <scales0=None>  <scales1=None>  <scales2=None>  <scales3=None>  <fatzero_in=None>  <fatzero_out=None>  <post_scale=None> 
+set_sensor_lens_flat_parameters  0  0  None None None None None 0x6000 0x6000 0x6000 0x6000
+set_sensor_lens_flat_parameters  1  0  None None None None None 0x6000 0x6000 0x6000 0x6000
+set_sensor_lens_flat_parameters  2  0  None None None None None 0x6000 0x6000 0x6000 0x6000
+set_sensor_lens_flat_parameters  3  0  None None None None None 0x6000 0x6000 0x6000 0x6000
+jpeg_sim_multi 4
+
+set_sensor_lens_flat_parameters  0  0  None None None None None 0x4000 0x4000 0x4000 0x4000
+set_sensor_lens_flat_parameters  1  0  None None None None None 0x4000 0x4000 0x4000 0x4000
+set_sensor_lens_flat_parameters  2  0  None None None None None 0x4000 0x4000 0x4000 0x4000
+set_sensor_lens_flat_parameters  3  0  None None None None None 0x4000 0x4000 0x4000 0x4000
+jpeg_sim_multi 4
+
+set_sensor_lens_flat_parameters  0  0  None None None None None 0x3000 0x3000 0x3000 0x3000
+set_sensor_lens_flat_parameters  1  0  None None None None None 0x3000 0x3000 0x3000 0x3000
+set_sensor_lens_flat_parameters  2  0  None None None None None 0x3000 0x3000 0x3000 0x3000
+set_sensor_lens_flat_parameters  3  0  None None None None None 0x3000 0x3000 0x3000 0x3000
+jpeg_sim_multi 4
+
+set_sensor_lens_flat_parameters  0  0  None None None None None 0x2000 0x2000 0x2000 0x2000
+set_sensor_lens_flat_parameters  1  0  None None None None None 0x2000 0x2000 0x2000 0x2000
+set_sensor_lens_flat_parameters  2  0  None None None None None 0x2000 0x2000 0x2000 0x2000
+set_sensor_lens_flat_parameters  3  0  None None None None None 0x2000 0x2000 0x2000 0x2000
+jpeg_sim_multi 4
+
+set_sensor_lens_flat_parameters  0  0  None None None None None 0x1e00 0x1e00 0x1e00 0x1e00
+set_sensor_lens_flat_parameters  1  0  None None None None None 0x1e00 0x1e00 0x1e00 0x1e00
+set_sensor_lens_flat_parameters  2  0  None None None None None 0x1e00 0x1e00 0x1e00 0x1e00
+set_sensor_lens_flat_parameters  3  0  None None None None None 0x1e00 0x1e00 0x1e00 0x1e00
+jpeg_sim_multi 4
+
+set_sensor_lens_flat_parameters  0  0  None None None None None 0x1d00 0x1d00 0x1d00 0x1d00
+set_sensor_lens_flat_parameters  1  0  None None None None None 0x1d00 0x1d00 0x1d00 0x1d00
+set_sensor_lens_flat_parameters  2  0  None None None None None 0x1d00 0x1d00 0x1d00 0x1d00
+set_sensor_lens_flat_parameters  3  0  None None None None None 0x1d00 0x1d00 0x1d00 0x1d00
+jpeg_sim_multi 4
+
 ################## Serial ####################
 cd /usr/local/verilog/; test_mcntrl.py @hargs
 bitstream_set_path /usr/local/verilog/x393_hispi.bit

--- a/simulation_modules/simul_sensor12bits.v
+++ b/simulation_modules/simul_sensor12bits.v
@@ -181,6 +181,14 @@ initial begin
    else if (SENSOR_IMAGE_TYPE == "NORM6")     $readmemh({`ROOTPATH,"/input_data/sensor_06.dat"},sensor_data);
    else if (SENSOR_IMAGE_TYPE == "NORM7")     $readmemh({`ROOTPATH,"/input_data/sensor_07.dat"},sensor_data);
    else if (SENSOR_IMAGE_TYPE == "NORM8")     $readmemh({`ROOTPATH,"/input_data/sensor_08.dat"},sensor_data);
+    else if (SENSOR_IMAGE_TYPE == "NORM9")     $readmemh({`ROOTPATH,"/input_data/sensor_09.dat"},sensor_data);
+    else if (SENSOR_IMAGE_TYPE == "NORM10")    $readmemh({`ROOTPATH,"/input_data/sensor_10.dat"},sensor_data);
+    else if (SENSOR_IMAGE_TYPE == "NORM11")    $readmemh({`ROOTPATH,"/input_data/sensor_11.dat"},sensor_data);
+    else if (SENSOR_IMAGE_TYPE == "NORM12")    $readmemh({`ROOTPATH,"/input_data/sensor_12.dat"},sensor_data);
+    else if (SENSOR_IMAGE_TYPE == "NORM13")    $readmemh({`ROOTPATH,"/input_data/sensor_13.dat"},sensor_data);
+    else if (SENSOR_IMAGE_TYPE == "NORM14")    $readmemh({`ROOTPATH,"/input_data/sensor_14.dat"},sensor_data);
+    else if (SENSOR_IMAGE_TYPE == "NORM15")    $readmemh({`ROOTPATH,"/input_data/sensor_15.dat"},sensor_data);
+    else if (SENSOR_IMAGE_TYPE == "NORM16")    $readmemh({`ROOTPATH,"/input_data/sensor_16.dat"},sensor_data);
    else begin
       $display ("WARNING: Unrecognized sensor image :'%s', using default 'NORM': input_data/sensor.dat",SENSOR_IMAGE_TYPE);
       $readmemh({`ROOTPATH,"/input_data/sensor.dat"},sensor_data);

--- a/timing/camsync393.v
+++ b/timing/camsync393.v
@@ -150,6 +150,13 @@ module camsync393       #(
    output                        ts_snap_mclk_chn3,     // ts_snap_mclk make a timestamp pulse  single @(posedge pclk)
    input                         ts_snd_stb_chn3,  // 1 clk before ts_snd_data is valid
    input                   [7:0] ts_snd_data_chn3, // byte-wide serialized timestamp message  
+    
+// Timestamps to be sent over the network (or provided internally)    
+    output                        ts_master_snap,   // ts_snap_mclk make a timestamp pulse  single @(posedge pclk)
+    input                         ts_master_stb,    // 1 clk before ts_snd_data is valid
+    input                   [7:0] ts_master_data,   // byte-wide serialized timestamp message  
+    
+    
    //ts_rcv_*sec (@mclk) goes to the following receivers:
                //ts_sync_*sec (synchronized to sensor clock) -> timestamp353 REMOVED
                //ts_sync_*sec (synchronized to sensor clock) -> compressor
@@ -177,8 +184,12 @@ module camsync393       #(
    reg           ts_external_m; // 1 - use external timestamp, if available. 0 - always use local ts (mode bit)
    reg           triggered_mode_r;

-    reg    [31:0] ts_snd_sec;  // [31:0] timestamp seconds to be sent over the sync line - multiplexed from master channel
-    reg    [19:0] ts_snd_usec; // [19:0] timestamp microseconds to be sent over the sync line
+//    reg    [31:0] ts_snd_sec;  // [31:0] timestamp seconds to be sent over the sync line - multiplexed from master channel
+//    reg    [19:0] ts_snd_usec; // [19:0] timestamp microseconds to be sent over the sync line
+
+    wire   [31:0] ts_snd_sec;  // [31:0] timestamp seconds to be sent over the sync line - multiplexed from master channel
+    wire   [19:0] ts_snd_usec; // [19:0] timestamp microseconds to be sent over the sync line
+

    wire   [31:0] ts_snd_sec_chn0;  // [31:0] timestamp seconds to be sent over the sync line
    wire   [19:0] ts_snd_usec_chn0; // [19:0] timestamp microseconds to be sent over the sync line
@@ -233,7 +244,10 @@ module camsync393       #(
    reg    [31:0] input_dly_chn1;  // delay value for the trigger
    reg    [31:0] input_dly_chn2;  // delay value for the trigger
    reg    [31:0] input_dly_chn3;  // delay value for the trigger
-    reg     [3:0] chn_en;          // enable channels
+    reg     [3:0] chn_en_r;
+    wire    [3:0] chn_en = chn_en_r & {4{en}};  // enable channels
+    
+    reg     [3:0] chn_en_pclk;     // enable channels
    reg     [1:0] master_chn;      // master channel (internal mode - delay used for flash) 
    reg     [9:0] gpio_active;     // output levels on the selected GPIO lines during output pulse (will be negated when inactive)
    reg           testmode;        // drive some internal signals to GPIO bits
@@ -242,6 +256,7 @@ module camsync393       #(
    reg    [31:0] repeat_period;    // restart period in repetitive mode
    reg           start,start_d;   // start single/repetitive output pulse(s)
    reg           rep_en;          // enable repetitive mode
+    reg           rep_en_pclk;
    reg           start_en;
    wire          start_to_pclk;
    reg    [2:0]  start_pclk; // start and restart
@@ -260,6 +275,7 @@ module camsync393       #(
    reg     [3:0] overdue;
 `endif    
    reg           start_dly;      // start delay (external input filtered or from internal single/rep)
+//    reg           start_early;    // start (external input filtered or from internal single/rep - early)
    reg   [31:0]  dly_cntr_chn0;       // trigger delay counter
    reg   [31:0]  dly_cntr_chn1;       // trigger delay counter
    reg   [31:0]  dly_cntr_chn2;       // trigger delay counter
@@ -303,19 +319,25 @@ module camsync393       #(
    reg           rcv_done_rq; // request to copy time stamp (if it is not ready yet)
    reg           rcv_done_rq_d;
    reg           rcv_done;  // rcv_run ended, copy timestamp if requested
-    wire          rcv_done_mclk; // rcv_done re-clocked @mclk 
+//    wire          rcv_done_mclk; // rcv_done re-clocked @mclk 
    wire          pre_rcv_error;  // pre/post magic does not match, set ts to all ff-s
    reg           rcv_error;

    reg           ts_external_pclk; // 1 - use external timestamp (combines ts_external and input_use_intern)
    reg           triggered_mode_pclk;
-    reg           armed_internal_trigger; // to prevent re-start as in internal trigger mode timestamp over for master channel trigger s the sequence
-                                          // and that timestmp is acquired fro each delayed channel (includin master) again
+    reg           armed_internal_trigger; // to prevent re-start as in internal trigger mode timestamp
+                                          // over for master channel triggers the sequence
+                                          // and that timestmp is acquired for each delayed channel (including master) again
+                                          // Is it still needed after mods or should be removed (likely)
    
    wire    [3:0] local_got; // received local timestamp (@ posedge mclk)
    wire    [3:0] local_got_pclk; // local_got reclocked @pclk
+    wire          master_got;
+    wire          master_got_pclk;
    wire    [3:0] frame_sync;
    reg     [3:0] ts_snap_triggered;     // make a timestamp pulse  single @(posedge pclk)
+    reg           ts_master_snap_pclk;       // make a timestamp pulse  single @(posedge pclk)
+    
    wire    [3:0] ts_snap_triggered_mclk;     // make a timestamp pulse  single @(posedge pclk)
    
    reg           ext_int_mode_mclk;    // triggered from external (no TS instead of the FPGA timer), generate internal network
@@ -331,8 +353,37 @@ module camsync393       #(
    reg    [6:0]  ext_int_trigger_filter_cntr;
    reg           ext_int_pre_pause;   // when repeat counter is < 6 - to speed up decoding
    reg    [1:0]  ext_int_arm;         // 0 - when repeat counter =
+    reg           ts_incoming;         // expect incoming timestamps (ts_snd_en && !input_use_intern)
+    reg           received_or_master;  // either received timestamp or master
+
+    wire   [31:0] ts_sec_received_or_master =  ts_incoming? {sr_rcv_first[25:0],  sr_rcv_second[31:26]} : ts_snd_sec[31:0];
+    wire   [19:0] ts_usec_received_or_master = ts_incoming? {rcv_error?20'hfffff:  sr_rcv_second[25:6]} : ts_snd_usec[19:0];
+    
+    reg    [3:0]  frsync_pend;                // from start_dly->start_early to frsync_pclk[i]; (start_dly too late in internal trigger mode)
+    reg           received_or_master_pending; // from start_dly->start_early to received_or_master;
+    wire   [3:0]  pending_latest = frsync_pend | {4{received_or_master_pending}};
+    reg    [3:0]  pending_latest_d;
+    reg    [3:0]  ts_stb_pclk_r;
+    reg           start_early;
+    
+    reg           suppress_immediate_set_mclk; // even single after repetitive will be suppressed (0 should be written first)
+    wire          suppress_immediate_set_pclk;
+    reg           suppress_immediate; // suppress first trigger if period was not 0 (to avoid re-started frames)
+     
+    wire          start_pclk2_masked= start_pclk[2] && !suppress_immediate; 
+     
+//    reg 
+
+    
+    
+    wire   [3:0] frsync_pclk; // time to copy timestamps from master/received to channels (will always be after it is available)  
+//    assign  chn_en = ch_en_r & {4{en}};  // enable channels
+    
    assign gpio_out_en = gpio_out_en_r;
    
+//    reg    [3:0]  ts_to_send; // per-channel discrimination between (first) timestamp to send and the second (individual, captured at frame sync)
+    
+    
 //! in testmode GPIO[9] and GPIO[8] use internal signals instead of the outsync:
 //! bit 11 - same as TRIGGER output to the sensor (signal to the sensor may be disabled externally)
 //!          then that bit will be still from internall trigger to frame valid
@@ -354,8 +405,8 @@ module camsync393       #(
    assign  restart= restart_cntr_run[1] && !restart_cntr_run[0];
    
    assign  pre_set_bit=     (|cmd_data[31:8]==0) && |cmd_data[7:1]; // 2..255
-    assign  pre_start0=       |cmd_data[31:0] && !pre_set_bit;
-    assign  pre_set_period = !pre_set_bit;
+    assign  pre_start0=       |cmd_data[31:0] && !pre_set_bit; //  1, 256...
+    assign  pre_set_period = !pre_set_bit; 

    assign {trig_chn3, trig_chn2, trig_chn1, trig_chn0} =  trig_r_mclk;

@@ -403,16 +454,16 @@ module camsync393       #(
            if (cmd_data[CAMSYNC_EXTERNAL_BIT])  ts_external_m <=    cmd_data[CAMSYNC_EXTERNAL_BIT - 1];
            if (cmd_data[CAMSYNC_TRIGGERED_BIT]) triggered_mode_r <= cmd_data[CAMSYNC_TRIGGERED_BIT - 1];
            if (cmd_data[CAMSYNC_MASTER_BIT])    master_chn <=       cmd_data[CAMSYNC_MASTER_BIT - 1 -: 2];
-//            if (cmd_data[CAMSYNC_CHN_EN_BIT])    chn_en <= cmd_data[CAMSYNC_CHN_EN_BIT - 1 -: 4];
 // Making separate enables for each channel, so channel software will not disturb other channels
-            if (cmd_data[CAMSYNC_CHN_EN_BIT-3])    chn_en[0] <=      cmd_data[CAMSYNC_CHN_EN_BIT - 7];
-            if (cmd_data[CAMSYNC_CHN_EN_BIT-2])    chn_en[1] <=      cmd_data[CAMSYNC_CHN_EN_BIT - 6];
-            if (cmd_data[CAMSYNC_CHN_EN_BIT-1])    chn_en[2] <=      cmd_data[CAMSYNC_CHN_EN_BIT - 5];
-            if (cmd_data[CAMSYNC_CHN_EN_BIT-0])    chn_en[3] <=      cmd_data[CAMSYNC_CHN_EN_BIT - 4];
-            
+            if (cmd_data[CAMSYNC_CHN_EN_BIT-3])  chn_en_r[0] <= cmd_data[CAMSYNC_CHN_EN_BIT - 7];
+            if (cmd_data[CAMSYNC_CHN_EN_BIT-2])  chn_en_r[1] <= cmd_data[CAMSYNC_CHN_EN_BIT - 6];
+            if (cmd_data[CAMSYNC_CHN_EN_BIT-1])  chn_en_r[2] <= cmd_data[CAMSYNC_CHN_EN_BIT - 5];
+            if (cmd_data[CAMSYNC_CHN_EN_BIT-0])  chn_en_r[3] <= cmd_data[CAMSYNC_CHN_EN_BIT - 4];
        end
+        
        // Do not try to use external timestamp in free run or internally triggered mode
-        ts_external <= ts_external_m && !input_use_intern && triggered_mode_r;
+///        ts_external <= ts_external_m && !input_use_intern && triggered_mode_r;
+        ts_external <= ts_external_m && triggered_mode_r; // internal will still use common timestamp made for sending
         
        if (mrst) input_use <= 0;
        if (!en) begin
@@ -468,56 +519,44 @@ module camsync393       #(

        start_en <= en && (repeat_period[31:0]!=0);
        
-        if (!en) rep_en <= 0;
+//        if      (!en)        rep_en <= 0;
+        if      (mrst)       rep_en <= 0;
        else if (set_period) rep_en <= !high_zero;
        
+        suppress_immediate_set_mclk <= set_period && rep_en && en; // even single will be suppressed if not after stopped/single  
+        
        ext_int_mode_mclk <= input_use[CAMSYNC_GPIO_EXT_IN] && !gpio_out_en_r[CAMSYNC_GPIO_EXT_OUT] &&
                             input_use[CAMSYNC_GPIO_INT_IN] &&  gpio_out_en_r[CAMSYNC_GPIO_INT_OUT]; 
        
        
    end
+    
    always @ (posedge pclk) begin
-        case (master_chn)
-            2'h0: begin
-                    ts_snd_sec <=  ts_snd_sec_chn0;
-                    ts_snd_usec <= ts_snd_usec_chn0;
-                  end
-            2'h1: begin
-                    ts_snd_sec <=  ts_snd_sec_chn1;
-                    ts_snd_usec <= ts_snd_usec_chn1;
-                  end
-            2'h2: begin
-                    ts_snd_sec <=  ts_snd_sec_chn2;
-                    ts_snd_usec <= ts_snd_usec_chn2;
-                  end
-            2'h3: begin
-                    ts_snd_sec <=  ts_snd_sec_chn3;
-                    ts_snd_usec <= ts_snd_usec_chn3;
-                  end
-        endcase
-    end    
-    always @ (posedge pclk) begin
+        chn_en_pclk <= chn_en;
+        rep_en_pclk <= rep_en && en;
+        
+        if      (!en_pclk || start_pclk[2])    suppress_immediate <= 0;
+        else if (suppress_immediate_set_pclk)  suppress_immediate <= 1;
+    
        if (!input_use_intern || start_late) armed_internal_trigger <= 0;
        else if (start_pclk[2])              armed_internal_trigger <= 1;
-        
-        ts_snap_triggered <=  chn_en & ({4{(start_pclk[2] & ts_snd_en_pclk)}} | //strobe by internal generator if output timestamp is enabled
-                              (trig_r & ~{4{ts_external_pclk}}));  // get local timestamp of the trigger (ext/int)
-
+        // now only at frame sync, others are handled by master timestamp
+        ts_snap_triggered <=  chn_en_pclk & trig_r;  // get local timestamp of the trigger (ext/int). Non-trigger-mode will use frame sync instead
+                              
+// request master timestamp at start if it is sent out or at receive (if it is not).  ts_snd_en_pclk should be 0 if incoming sync does not have timestamps                              
+                              
+///        ts_master_snap_pclk <=  ts_snd_en_pclk? start_pclk[2]: rcv_done;
+        ts_master_snap_pclk <=  ts_snd_en_pclk? start_pclk2_masked: rcv_done;
+                            
        ts_snd_en_pclk<=ts_snd_en;
        input_use_intern <= pre_input_use_intern;
        ts_external_pclk<= ts_external; //  && !input_use_intern;
     
-        start_pclk[2:0] <= {(restart && rep_en) || 
-//                            (start_pclk[1] && !restart_cntr_run[1] && !restart_cntr_run[0] && !start_pclk[2]), // does not allow to restart
+        start_pclk[2:0] <= {(restart && rep_en_pclk) || 
                            (start_pclk[1]  && !start_pclk[2]), // allows to restart running or armed counter
                            start_pclk[0],
                            start_to_pclk && !start_pclk[0]};
                            
-//        restart_cntr_run[1:0] <= {restart_cntr_run[0],start_en && (start_pclk[2] || (restart_cntr_run[0] && (restart_cntr[31:2] !=0)))};
-//
-//        if (restart_cntr_run[0]) restart_cntr[31:0] <= restart_cntr[31:0] - 1;
-//        else                     restart_cntr[31:0] <= repeat_period[31:0];
-
        restart_cntr_run[1:0] <= {restart_cntr_run[0],start_en && (start_pclk[2] || (restart_cntr_run[0] && !ext_int_arm[1] && !start_pclk[0]))};
        
        if (restart_cntr_run[0]) begin
@@ -561,7 +600,7 @@ module camsync393       #(
    end
 
    always @ (posedge pclk) begin
-        if      (eprst)                 dly_cntr_run <= 0;
+        if      (eprst)                dly_cntr_run <= 0;
        else if (!triggered_mode_pclk) dly_cntr_run <= 0;
        else if (start_dly)            dly_cntr_run <= 4'hf;
        else                           dly_cntr_run <= dly_cntr_run &
@@ -632,6 +671,16 @@ module camsync393       #(
        start_dly <= input_use_intern ?
                      (start_late_first && start_en) : // only use armed_internal_trigger with timestamps
                      (rcv_run && !rcv_run_d);  // all start at the same time - master/others
+                      
+                      
+///        start_early <=input_use_intern ?
+///                      (start_pclk[2] && start_en) :
+///                      (rcv_run && !rcv_run_d);  // all start at the same time - master/others
+        start_early <=input_use_intern ?
+                      (start_pclk2_masked && start_en) :
+                      (rcv_run && !rcv_run_d);  // all start at the same time - master/others
+                      
+//                      
 // simulation problems w/o "start_en &&" ? 

        dly_cntr_run_d <= dly_cntr_run;
@@ -676,42 +725,106 @@ module camsync393       #(
      
        rcv_error <= pre_rcv_error;

+        ts_incoming <= ts_snd_en_pclk && !input_use_intern;
+        received_or_master <= ts_incoming ? rcv_done: master_got_pclk;
+        
+        
+        frsync_pend <=                chn_en_pclk & ({4{start_early}} | (frsync_pend & ~frsync_pclk));
+        received_or_master_pending <= en_pclk & (start_early | (received_or_master_pending & ~received_or_master));
+        pending_latest_d <=           pending_latest;                   // delayed version
+        ts_stb_pclk_r <=              (triggered_mode_pclk && ts_external_pclk)? (pending_latest_d & ~pending_latest): local_got_pclk ; // trailing edge or just local
+        
+        if (triggered_mode_pclk && ts_external_pclk) begin
+            if (received_or_master) begin
+                ts_rcv_sec_chn0  [31:0] <= ts_sec_received_or_master;
+                ts_rcv_usec_chn0 [19:0] <= ts_usec_received_or_master;
+                ts_rcv_sec_chn1  [31:0] <= ts_sec_received_or_master;
+                ts_rcv_usec_chn1 [19:0] <= ts_usec_received_or_master;
+                ts_rcv_sec_chn2  [31:0] <= ts_sec_received_or_master;
+                ts_rcv_usec_chn2 [19:0] <= ts_usec_received_or_master;
+                ts_rcv_sec_chn3  [31:0] <= ts_sec_received_or_master;
+                ts_rcv_usec_chn3 [19:0] <= ts_usec_received_or_master;
+            end
+        end else begin // use local timestamps
+            if (local_got_pclk[0]) begin
+                ts_rcv_sec_chn0[31:0] <=  ts_snd_sec_chn0 [31:0];
+                ts_rcv_usec_chn0[19:0] <=  ts_snd_usec_chn0[19:0];
+            end
+            if (local_got_pclk[1]) begin
+                ts_rcv_sec_chn1[31:0] <=  ts_snd_sec_chn1 [31:0];
+                ts_rcv_usec_chn1[19:0] <=  ts_snd_usec_chn1[19:0];
+            end
+            if (local_got_pclk[2]) begin
+                ts_rcv_sec_chn2[31:0] <=  ts_snd_sec_chn2 [31:0];
+                ts_rcv_usec_chn2[19:0] <=  ts_snd_usec_chn2[19:0];
+            end
+            if (local_got_pclk[3]) begin
+                ts_rcv_sec_chn3[31:0] <=  ts_snd_sec_chn3 [31:0];
+                ts_rcv_usec_chn3[19:0] <=  ts_snd_usec_chn3[19:0];
+            end
+        end
+
+
+/*
        if (rcv_done) begin
            ts_rcv_sec_chn0  [31:0] <= {sr_rcv_first[25:0],sr_rcv_second[31:26]};
            ts_rcv_usec_chn0 [19:0] <= rcv_error?20'hfffff:   sr_rcv_second[25:6];
+        end else if (master_got_pclk && ts_external_pclk) begin
+            ts_rcv_sec_chn0[31:0] <=   ts_snd_sec[31:0];
+            ts_rcv_usec_chn0[19:0] <=  ts_snd_usec[19:0];
        end else if (!triggered_mode_pclk || (!ts_external_pclk && local_got_pclk[0])) begin
            ts_rcv_sec_chn0[31:0] <=  ts_snd_sec_chn0 [31:0];
            ts_rcv_usec_chn0[19:0] <=  ts_snd_usec_chn0[19:0];
        end
-        
-        if (rcv_done) begin
-            ts_rcv_sec_chn1  [31:0] <= {sr_rcv_first[25:0],sr_rcv_second[31:26]};
-            ts_rcv_usec_chn1 [19:0] <= rcv_error?20'hfffff:   sr_rcv_second[25:6];
-        end else if (!triggered_mode_pclk || (!ts_external_pclk && local_got_pclk[1])) begin
-            ts_rcv_sec_chn1[31:0] <=  ts_snd_sec_chn1 [31:0];
-            ts_rcv_usec_chn1[19:0] <=  ts_snd_usec_chn1[19:0];
-        end
-        
-        if (rcv_done) begin
-            ts_rcv_sec_chn2  [31:0] <= {sr_rcv_first[25:0],sr_rcv_second[31:26]};
-            ts_rcv_usec_chn2 [19:0] <= rcv_error?20'hfffff:   sr_rcv_second[25:6];
-        end else if (!triggered_mode_pclk || (!ts_external_pclk && local_got_pclk[2])) begin
-            ts_rcv_sec_chn2[31:0] <=  ts_snd_sec_chn2 [31:0];
-            ts_rcv_usec_chn2[19:0] <=  ts_snd_usec_chn2[19:0];
-        end
-        
-        if (rcv_done) begin
-            ts_rcv_sec_chn3  [31:0] <= {sr_rcv_first[25:0],sr_rcv_second[31:26]};
-            ts_rcv_usec_chn3 [19:0] <= rcv_error?20'hfffff:   sr_rcv_second[25:6];
-        end else if (!triggered_mode_pclk || (!ts_external_pclk && local_got_pclk[3])) begin
-            ts_rcv_sec_chn3[31:0] <=  ts_snd_sec_chn3 [31:0];
-            ts_rcv_usec_chn3[19:0] <=  ts_snd_usec_chn3[19:0];
+
+
+        ts_incoming <= ts_snd_en_pclk && !input_use_intern;
+
+        if (triggered_mode_pclk && ts_external_pclk) begin
+            if (frsync_pclk[0]) begin
+                ts_rcv_sec_chn0  [31:0] <= ts_incoming? {sr_rcv_first[25:0],  sr_rcv_second[31:26]} : ts_snd_sec[31:0];
+                ts_rcv_usec_chn0 [19:0] <= ts_incoming? {rcv_error?20'hfffff:  sr_rcv_second[25:6]} : ts_snd_usec[19:0];
+            end
+            if (frsync_pclk[1]) begin
+                ts_rcv_sec_chn1  [31:0] <= ts_incoming? {sr_rcv_first[25:0],  sr_rcv_second[31:26]} : ts_snd_sec[31:0];
+                ts_rcv_usec_chn1 [19:0] <= ts_incoming? {rcv_error?20'hfffff:  sr_rcv_second[25:6]} : ts_snd_usec[19:0];
+            end
+            if (frsync_pclk[2]) begin
+                ts_rcv_sec_chn2  [31:0] <= ts_incoming? {sr_rcv_first[25:0],  sr_rcv_second[31:26]} : ts_snd_sec[31:0];
+                ts_rcv_usec_chn2 [19:0] <= ts_incoming? {rcv_error?20'hfffff:  sr_rcv_second[25:6]} : ts_snd_usec[19:0];
+            end
+            if (frsync_pclk[3]) begin
+                ts_rcv_sec_chn3  [31:0] <= ts_incoming? {sr_rcv_first[25:0],  sr_rcv_second[31:26]} : ts_snd_sec[31:0];
+                ts_rcv_usec_chn3 [19:0] <= ts_incoming? {rcv_error?20'hfffff:  sr_rcv_second[25:6]} : ts_snd_usec[19:0];
+            end
+        end else begin
+            if (local_got_pclk[0]) begin
+                ts_rcv_sec_chn0[31:0] <=  ts_snd_sec_chn0 [31:0];
+                ts_rcv_usec_chn0[19:0] <=  ts_snd_usec_chn0[19:0];
+            end
+            if (local_got_pclk[1]) begin
+                ts_rcv_sec_chn1[31:0] <=  ts_snd_sec_chn1 [31:0];
+                ts_rcv_usec_chn1[19:0] <=  ts_snd_usec_chn1[19:0];
+            end
+            if (local_got_pclk[2]) begin
+                ts_rcv_sec_chn2[31:0] <=  ts_snd_sec_chn2 [31:0];
+                ts_rcv_usec_chn2[19:0] <=  ts_snd_usec_chn2[19:0];
+            end
+            if (local_got_pclk[3]) begin
+                ts_rcv_sec_chn3[31:0] <=  ts_snd_sec_chn3 [31:0];
+                ts_rcv_usec_chn3[19:0] <=  ts_snd_usec_chn3[19:0];
+            end
        end
+*/        
    end

-    assign ts_stb = (!ts_external || pre_input_use_intern) ? local_got : {4{rcv_done_mclk}};
+//    assign ts_stb = (!ts_external || pre_input_use_intern) ? local_got : {4{rcv_done_mclk}};
+    
+//  rcv_done_mclk - make it either really received or from FPGA if internal?   
+    
    // Making delayed start that waits for timestamp use timestamp_got, otherwise - nothing to wait
-    assign start_late = ts_snd_en_pclk?local_got_pclk[master_chn] :  start_pclk[2];    
+///    assign start_late =    ts_snd_en_pclk?master_got_pclk :  start_pclk[2];   
+    assign start_late =       ts_snd_en_pclk?master_got_pclk :  start_pclk2_masked;   
    assign start_late_first = start_late && (armed_internal_trigger|| !ts_snd_en_pclk);
    
    cmd_deser #(
@@ -767,6 +880,17 @@ module camsync393       #(
        .done       (local_got[3])    // output
    );

+    timestamp_to_parallel timestamp_to_parallel_master_i (
+        .clk        (mclk),             // input
+        .pre_stb    (ts_master_stb),    // input
+        .tdata      (ts_master_data),   // input[7:0] 
+        .sec        (ts_snd_sec),       // output[31:0] reg 
+        .usec       (ts_snd_usec),      // output[19:0] reg 
+        .done       (master_got)        // output
+    );
+
+
+
    timestamp_to_serial timestamp_to_serial0_i (
        .clk        (mclk),             // input
        .stb        (ts_stb[0]),        // input
@@ -799,6 +923,8 @@ module camsync393       #(
        .tdata      (ts_rcv_data_chn3)  // output[7:0] reg 
    );

+
+
    level_cross_clocks #(
        .WIDTH(1),
        .REGISTER(2)
@@ -817,17 +943,34 @@ module camsync393       #(
    pulse_cross_clock i_ts_snap_mclk2 (.rst(eprst), .src_clk(pclk), .dst_clk(mclk), .in_pulse(ts_snap_triggered[2]), .out_pulse(ts_snap_triggered_mclk[2]),.busy());
    pulse_cross_clock i_ts_snap_mclk3 (.rst(eprst), .src_clk(pclk), .dst_clk(mclk), .in_pulse(ts_snap_triggered[3]), .out_pulse(ts_snap_triggered_mclk[3]),.busy());

-    pulse_cross_clock i_rcv_done_mclk (.rst(eprst), .src_clk(pclk), .dst_clk(mclk), .in_pulse(rcv_done), .out_pulse(rcv_done_mclk),.busy());
+    pulse_cross_clock i_ts_snap_master(.rst(eprst), .src_clk(pclk), .dst_clk(mclk), .in_pulse(ts_master_snap_pclk),  .out_pulse(ts_master_snap),.busy());
+
+///    pulse_cross_clock i_rcv_done_mclk (.rst(eprst), .src_clk(pclk), .dst_clk(mclk), .in_pulse(rcv_done), .out_pulse(rcv_done_mclk),.busy());

    pulse_cross_clock i_local_got_pclk0(.rst(mrst), .src_clk(mclk), .dst_clk(pclk), .in_pulse(local_got[0]), .out_pulse(local_got_pclk[0]),.busy());
    pulse_cross_clock i_local_got_pclk1(.rst(mrst), .src_clk(mclk), .dst_clk(pclk), .in_pulse(local_got[1]), .out_pulse(local_got_pclk[1]),.busy());
    pulse_cross_clock i_local_got_pclk2(.rst(mrst), .src_clk(mclk), .dst_clk(pclk), .in_pulse(local_got[2]), .out_pulse(local_got_pclk[2]),.busy());
    pulse_cross_clock i_local_got_pclk3(.rst(mrst), .src_clk(mclk), .dst_clk(pclk), .in_pulse(local_got[3]), .out_pulse(local_got_pclk[3]),.busy());
+    
+    pulse_cross_clock i_master_got_pclk(.rst(mrst), .src_clk(mclk), .dst_clk(pclk), .in_pulse(master_got),   .out_pulse(master_got_pclk),.busy());

    pulse_cross_clock i_trig_r_mclk0 (.rst(eprst), .src_clk(pclk), .dst_clk(mclk), .in_pulse(trig_r[0]), .out_pulse(trig_r_mclk[0]),.busy());
    pulse_cross_clock i_trig_r_mclk1 (.rst(eprst), .src_clk(pclk), .dst_clk(mclk), .in_pulse(trig_r[1]), .out_pulse(trig_r_mclk[1]),.busy());
    pulse_cross_clock i_trig_r_mclk2 (.rst(eprst), .src_clk(pclk), .dst_clk(mclk), .in_pulse(trig_r[2]), .out_pulse(trig_r_mclk[2]),.busy());
    pulse_cross_clock i_trig_r_mclk3 (.rst(eprst), .src_clk(pclk), .dst_clk(mclk), .in_pulse(trig_r[3]), .out_pulse(trig_r_mclk[3]),.busy());
    
+    pulse_cross_clock i_frsync_pclk0(.rst(!en),    .src_clk(mclk), .dst_clk(pclk), .in_pulse(frame_sync[0]), .out_pulse(frsync_pclk[0]),.busy());
+    pulse_cross_clock i_frsync_pclk1(.rst(!en),    .src_clk(mclk), .dst_clk(pclk), .in_pulse(frame_sync[1]), .out_pulse(frsync_pclk[1]),.busy());
+    pulse_cross_clock i_frsync_pclk2(.rst(!en),    .src_clk(mclk), .dst_clk(pclk), .in_pulse(frame_sync[2]), .out_pulse(frsync_pclk[2]),.busy());
+    pulse_cross_clock i_frsync_pclk3(.rst(!en),    .src_clk(mclk), .dst_clk(pclk), .in_pulse(frame_sync[3]), .out_pulse(frsync_pclk[3]),.busy());
+    
+    pulse_cross_clock i_ts_stb_mclk0 (.rst(eprst), .src_clk(pclk), .dst_clk(mclk), .in_pulse(ts_stb_pclk_r[0]), .out_pulse(ts_stb[0]),.busy());
+    pulse_cross_clock i_ts_stb_mclk1 (.rst(eprst), .src_clk(pclk), .dst_clk(mclk), .in_pulse(ts_stb_pclk_r[1]), .out_pulse(ts_stb[1]),.busy());
+    pulse_cross_clock i_ts_stb_mclk2 (.rst(eprst), .src_clk(pclk), .dst_clk(mclk), .in_pulse(ts_stb_pclk_r[2]), .out_pulse(ts_stb[2]),.busy());
+    pulse_cross_clock i_ts_stb_mclk3 (.rst(eprst), .src_clk(pclk), .dst_clk(mclk), .in_pulse(ts_stb_pclk_r[3]), .out_pulse(ts_stb[3]),.busy());
+
+    pulse_cross_clock i_suppress_immediate_set_pclk(.rst(!en),    .src_clk(mclk), .dst_clk(pclk), .in_pulse(suppress_immediate_set_mclk), .out_pulse(suppress_immediate_set_pclk),.busy());
+
+    
 endmodule

--- a/timing/timing393.v
+++ b/timing/timing393.v
@@ -140,6 +140,12 @@ module  timing393       #(
    wire   [3:0] ts_local_stb;   // 1 clk before ts_snd_data is valid
    wire  [31:0] ts_local_data;  // byte-wide serialized timestamp message  

+    wire         ts_master_snap; // ts_snap_mclk make a timestamp pulse  single @(posedge pclk)
+    wire         ts_master_stb;  // 1 clk before ts_snd_data is valid
+    wire   [7:0] ts_master_data; // byte-wide serialized timestamp message  
+
+
+
    wire   [3:0] ts_stb;        // 1 clk before ts_snd_data is valid
    wire  [31:0] ts_data;       // byte-wide serialized timestamp message (channels concatenated)
    
@@ -238,6 +244,18 @@ module  timing393       #(
        .ts_data               (ts_local_data[3 * 8 +: 8]) // output[7:0] reg 
    );

+    timestamp_snapshot timestamp_snapshot_master_i ( // timestamp to send over the sync network
+        .tclk                  (mclk),                     // input
+        .sec                   (live_sec),                 // input[31:0] 
+        .usec                  (live_usec),                // input[19:0] 
+        .sclk                  (mclk),                     // input
+        .srst                  (mrst),                     // input
+        .snap                  (ts_master_snap),           // input
+        .pre_stb               (ts_master_stb),            // output
+        .ts_data               (ts_master_data[7:0])       // output[7:0] reg 
+    );
+
+
    camsync393 #(
        .CAMSYNC_ADDR           (CAMSYNC_ADDR),
        .CAMSYNC_MASK           (CAMSYNC_MASK),
@@ -294,6 +312,9 @@ module  timing393       #(
        .ts_snap_mclk_chn3 (ts_local_snap[3]),          // output
        .ts_snd_stb_chn3   (ts_local_stb[3]),           // input
        .ts_snd_data_chn3  (ts_local_data[3 * 8 +: 8]), // input[7:0] 
+        .ts_master_snap    (ts_master_snap),            // output
+        .ts_master_stb     (ts_master_stb),             // input
+        .ts_master_data    (ts_master_data),            // input[7:0] 
        .ts_rcv_stb_chn0   (ts_stb[0]),                 // output
        .ts_rcv_data_chn0  (ts_data[0 * 8 +: 8]),       // output[7:0] 
        .ts_rcv_stb_chn1   (ts_stb[1]),                 // output

--- a/x393_parallel.bit
+++ b/x393_parallel.bit