Commit d2db8c14 authored by Andrey Filippov's avatar Andrey Filippov

more simulatin/bug fixing

parent 7614ead5
...@@ -33,6 +33,7 @@ endtask ...@@ -33,6 +33,7 @@ endtask
task wait_ps_pio_ready; // wait PS PIO module can accept comamnds (fifo half empty) task wait_ps_pio_ready; // wait PS PIO module can accept comamnds (fifo half empty)
input [1:0] mode; input [1:0] mode;
input sync_seq; // synchronize sequences
begin begin
wait_status_condition ( wait_status_condition (
MCNTRL_PS_STATUS_REG_ADDR, MCNTRL_PS_STATUS_REG_ADDR,
...@@ -40,11 +41,13 @@ task wait_ps_pio_ready; // wait PS PIO module can accept comamnds (fifo half emp ...@@ -40,11 +41,13 @@ task wait_ps_pio_ready; // wait PS PIO module can accept comamnds (fifo half emp
mode, mode,
0, 0,
2 << STATUS_2LSB_SHFT, 2 << STATUS_2LSB_SHFT,
0); 0,
sync_seq);
end end
endtask endtask
task wait_ps_pio_done; // wait PS PIO module has no pending/running memory transaction task wait_ps_pio_done; // wait PS PIO module has no pending/running memory transaction
input [1:0] mode; input [1:0] mode;
input sync_seq; // synchronize sequences
begin begin
wait_status_condition ( wait_status_condition (
MCNTRL_PS_STATUS_REG_ADDR, MCNTRL_PS_STATUS_REG_ADDR,
...@@ -52,8 +55,8 @@ task wait_ps_pio_done; // wait PS PIO module has no pending/running memory trans ...@@ -52,8 +55,8 @@ task wait_ps_pio_done; // wait PS PIO module has no pending/running memory trans
mode, mode,
0, 0,
3 << STATUS_2LSB_SHFT, 3 << STATUS_2LSB_SHFT,
0,
0); sync_seq);
end end
endtask endtask
...@@ -27,22 +27,43 @@ task wait_status_condition; ...@@ -27,22 +27,43 @@ task wait_status_condition;
input [25:0] pattern; // bits as in read registers input [25:0] pattern; // bits as in read registers
input [25:0] mask; // which bits to compare input [25:0] mask; // which bits to compare
input invert_match; // 0 - wait until match to pattern (all bits), 1 - wait until no match (any of bits differ) input invert_match; // 0 - wait until match to pattern (all bits), 1 - wait until no match (any of bits differ)
input wait_seq;
reg match; reg match;
reg [5:0] seq_num; reg [5:0] seq_num;
begin begin
WAITING_STATUS = 1; WAITING_STATUS = 1;
for (match=0; !match; match = invert_match ^ (((registered_rdata ^ {6'h0,pattern}) & {6'h0,mask})==0)) begin for (match=0; !match; match = invert_match ^ (((registered_rdata ^ {6'h0,pattern}) & {6'h0,mask})==0)) begin
read_and_wait_status(status_address); read_and_wait_status(status_address);
write_contol_register(status_control_address, {24'b0,status_mode,registered_rdata[STATUS_SEQ_SHFT+:6] ^ 6'h20}); if (wait_seq) begin
seq_num <= registered_rdata[STATUS_SEQ_SHFT+:6] ^ 6'h20; seq_num = (registered_rdata[STATUS_SEQ_SHFT+:6] ^ 6'h20)&'h30;
write_contol_register(status_control_address, {24'b0,status_mode,seq_num});
read_and_wait_status(status_address); read_and_wait_status(status_address);
while (((registered_rdata[STATUS_SEQ_SHFT+:6] ^ seq_num) & 6'h30)!=0) begin // match just 2 MSBs while (((registered_rdata[STATUS_SEQ_SHFT+:6] ^ seq_num) & 6'h30)!=0) begin // match just 2 MSBs
read_and_wait_status(status_address); read_and_wait_status(status_address);
end end
end end
end
WAITING_STATUS = 0;
end
endtask
/*
task wait_status_condition_auto; // assumes status is already updating
input [STATUS_DEPTH-1:0] status_address;
input [29:0] status_control_address;
input [1:0] status_mode;
input [25:0] pattern; // bits as in read registers
input [25:0] mask; // which bits to compare
input invert_match; // 0 - wait until match to pattern (all bits), 1 - wait until no match (any of bits differ)
reg match;
begin
WAITING_STATUS = 1;
for (match=0; !match; match = invert_match ^ (((registered_rdata ^ {6'h0,pattern}) & {6'h0,mask})==0)) begin
read_and_wait_status(status_address);
end
WAITING_STATUS = 0; WAITING_STATUS = 0;
end end
endtask endtask
*/
task wait_phase_shifter_ready; task wait_phase_shifter_ready;
begin begin
......
...@@ -233,7 +233,7 @@ module mcntrl_linear_rw #( ...@@ -233,7 +233,7 @@ module mcntrl_linear_rw #(
assign frame_done= frame_done_r; assign frame_done= frame_done_r;
assign frame_finished= frame_finished_r; assign frame_finished= frame_finished_r;
assign pre_want= chn_en && busy_r && !want_r && !xfer_start_r[0] && calc_valid && !last_block && !suspend; assign pre_want= chn_en && busy_r && !want_r && !xfer_start_r[0] && calc_valid && !last_block && !suspend && !frame_start;
// assign pre_want= chn_en && busy_r && !want_r && !xfer_start_r[0] && calc_valid && !no_more_needed && !suspend; // assign pre_want= chn_en && busy_r && !want_r && !xfer_start_r[0] && calc_valid && !no_more_needed && !suspend;
// //
assign last_in_row_w=(row_left=={{(FRAME_WIDTH_BITS-NUM_XFER_BITS){1'b0}},xfer_num128_r}); assign last_in_row_w=(row_left=={{(FRAME_WIDTH_BITS-NUM_XFER_BITS){1'b0}},xfer_num128_r});
...@@ -317,7 +317,7 @@ wire start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r; ...@@ -317,7 +317,7 @@ wire start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r;
// calculate number to read (min of row_left, maximal xfer and what is left in the DDR3 page // calculate number to read (min of row_left, maximal xfer and what is left in the DDR3 page
always @(posedge rst or posedge mclk) begin always @(posedge rst or posedge mclk) begin
if (rst) par_mod_r<=0; if (rst) par_mod_r<=0;
else if (pgm_param_w || xfer_start_r[0] || chn_rst) par_mod_r<=0; else if (pgm_param_w || xfer_start_r[0] || chn_rst || frame_start) par_mod_r<=0;
else par_mod_r <= {par_mod_r[PAR_MOD_LATENCY-2:0], 1'b1}; else par_mod_r <= {par_mod_r[PAR_MOD_LATENCY-2:0], 1'b1};
if (rst) chn_rst_d <= 0; if (rst) chn_rst_d <= 0;
...@@ -326,7 +326,8 @@ wire start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r; ...@@ -326,7 +326,8 @@ wire start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r;
if (rst) recalc_r<=0; if (rst) recalc_r<=0;
else if (chn_rst) recalc_r<=0; else if (chn_rst) recalc_r<=0;
// else recalc_r <= {recalc_r[PAR_MOD_LATENCY-2:0], (xfer_grant & ~chn_rst) | pgm_param_w | (chn_rst_d & ~chn_rst)}; // else recalc_r <= {recalc_r[PAR_MOD_LATENCY-2:0], (xfer_grant & ~chn_rst) | pgm_param_w | (chn_rst_d & ~chn_rst)};
else recalc_r <= {recalc_r[PAR_MOD_LATENCY-2:0], (xfer_start_r[0] & ~chn_rst) | pgm_param_w | (chn_rst_d & ~chn_rst)}; else recalc_r <= {recalc_r[PAR_MOD_LATENCY-2:0],
((xfer_start_r[0] | frame_start) & ~chn_rst) | pgm_param_w | (chn_rst_d & ~chn_rst)};
if (rst) busy_r <= 0; if (rst) busy_r <= 0;
else if (chn_rst) busy_r <= 0; else if (chn_rst) busy_r <= 0;
......
...@@ -257,7 +257,7 @@ module mcntrl_tiled_rw#( ...@@ -257,7 +257,7 @@ module mcntrl_tiled_rw#(
assign calc_valid= par_mod_r[PAR_MOD_LATENCY-1]; // MSB, longest 0 assign calc_valid= par_mod_r[PAR_MOD_LATENCY-1]; // MSB, longest 0
assign frame_done= frame_done_r; assign frame_done= frame_done_r;
assign frame_finished= frame_finished_r; assign frame_finished= frame_finished_r;
assign pre_want= chn_en && busy_r && !want_r && !xfer_start_r[0] && calc_valid && !last_block && !suspend; assign pre_want= chn_en && busy_r && !want_r && !xfer_start_r[0] && calc_valid && !last_block && !suspend && !frame_start;
assign last_in_row_w=(row_left=={{(FRAME_WIDTH_BITS-MAX_TILE_WIDTH){1'b0}},num_cols_r}); // what if it crosses page? OK, num_cols_r & row_left know that assign last_in_row_w=(row_left=={{(FRAME_WIDTH_BITS-MAX_TILE_WIDTH){1'b0}},num_cols_r}); // what if it crosses page? OK, num_cols_r & row_left know that
// assign last_row_w= next_y>=window_height; // (next_y==window_height) is faster, but will not forgive software errors // assign last_row_w= next_y>=window_height; // (next_y==window_height) is faster, but will not forgive software errors
// tiles must completely fit window // tiles must completely fit window
...@@ -351,7 +351,7 @@ module mcntrl_tiled_rw#( ...@@ -351,7 +351,7 @@ module mcntrl_tiled_rw#(
wire start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r; wire start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r;
always @(posedge rst or posedge mclk) begin always @(posedge rst or posedge mclk) begin
if (rst) par_mod_r<=0; if (rst) par_mod_r<=0;
else if (pgm_param_w || xfer_start_r[0] || chn_rst) par_mod_r<=0; else if (pgm_param_w || xfer_start_r[0] || chn_rst || frame_start) par_mod_r<=0;
else par_mod_r <= {par_mod_r[PAR_MOD_LATENCY-2:0], 1'b1}; else par_mod_r <= {par_mod_r[PAR_MOD_LATENCY-2:0], 1'b1};
if (rst) chn_rst_d <= 0; if (rst) chn_rst_d <= 0;
...@@ -360,7 +360,8 @@ wire start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r; ...@@ -360,7 +360,8 @@ wire start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r;
if (rst) recalc_r<=0; if (rst) recalc_r<=0;
else if (chn_rst) recalc_r<=0; else if (chn_rst) recalc_r<=0;
// else recalc_r <= {recalc_r[PAR_MOD_LATENCY-2:0], (xfer_grant & ~chn_rst) | pgm_param_w | (chn_rst_d & ~chn_rst)}; // else recalc_r <= {recalc_r[PAR_MOD_LATENCY-2:0], (xfer_grant & ~chn_rst) | pgm_param_w | (chn_rst_d & ~chn_rst)};
else recalc_r <= {recalc_r[PAR_MOD_LATENCY-2:0], (xfer_start_r[0] & ~chn_rst) | pgm_param_w | (chn_rst_d & ~chn_rst)}; else recalc_r <= {recalc_r[PAR_MOD_LATENCY-2:0],
((xfer_start_r[0] | frame_start) & ~chn_rst) | pgm_param_w | (chn_rst_d & ~chn_rst)};
if (rst) busy_r <= 0; if (rst) busy_r <= 0;
else if (chn_rst) busy_r <= 0; else if (chn_rst) busy_r <= 0;
......
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