testing read memory as rectangular tiles (cd7cb395) · Commits · Elphel / x393

includes/x393_parameters.vh

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	@@ -214,7 +214,7 @@
	// Start XY can be used when read command to start from the middle		// Start XY can be used when read command to start from the middle
	// TODO: Add number of blocks to R/W? (blocks can be different) - total length?		// TODO: Add number of blocks to R/W? (blocks can be different) - total length?
	// Read back current address (for debugging)?		// Read back current address (for debugging)?
	parameter MCNTRL_TILED_TILE_WH= 'h7, // low word - 6-bit tile width in 8-bursts, high - tile height (0 - > 64)		parameter MCNTRL_TILED_TILE_WHS= 'h7, // low word - 6-bit tile width in 8-bursts, high - tile height (0 - > 64)
	parameter MCNTRL_TILED_STATUS_REG_CHN4_ADDR= 'h6,		parameter MCNTRL_TILED_STATUS_REG_CHN4_ADDR= 'h6,
	parameter MCNTRL_TILED_PENDING_CNTR_BITS=2, // Number of bits to count pending trasfers, currently 2 is enough, but may increase		parameter MCNTRL_TILED_PENDING_CNTR_BITS=2, // Number of bits to count pending trasfers, currently 2 is enough, but may increase
	// if memory controller will allow programming several sequences in advance to		// if memory controller will allow programming several sequences in advance to

memctrl/cmd_encod_linear_rd.v

+1 −10

Original line number	Original line	Diff line number	Diff line
	@@ -20,16 +20,7 @@
	* along with this program. If not, see <http://www.gnu.org/licenses/> .		* along with this program. If not, see <http://www.gnu.org/licenses/> .
	*******************************************************************************/		*******************************************************************************/
	`timescale 1ns/1ps		`timescale 1ns/1ps
	/*
	Minimal ACTIVATE period =4 Tcm or 10ns, so maksimal no-miss rate is Tck=1.25 ns (800 MHz)
	Minimal window of 4 ACTIVATE pulses - 16 Tck or 40 (40 ns), so one ACTIVATE per 8 Tck is still OK down to 1.25 ns
	Reads are in 16-byte colums: 1 8-burst (16 bytes) in a row, then next row, bank inc first. Then (if needed) - next column
	Number of rows should be >=5 (4 now for tCK=2.5ns to meet tRP (precharge to activate) of the same bank (tRP=13ns)
	Can read less if just one column
	TODO: Maybe allow less rows with different sequence (no autoprecharge/no activate?) Will not work if row crosses page boundary


	*/
	module cmd_encod_linear_rd #(		module cmd_encod_linear_rd #(
	// parameter BASEADDR = 0,		// parameter BASEADDR = 0,
	parameter ADDRESS_NUMBER= 15,		parameter ADDRESS_NUMBER= 15,

memctrl/cmd_encod_tiled_rd.v

+86 −37

Original line number	Original line	Diff line number	Diff line
	@@ -27,6 +27,17 @@
	* along with this program. If not, see <http://www.gnu.org/licenses/> .		* along with this program. If not, see <http://www.gnu.org/licenses/> .
	*******************************************************************************/		*******************************************************************************/
	`timescale 1ns/1ps		`timescale 1ns/1ps
			/*
			Minimal ACTIVATE period =4 Tcm or 10ns, so maximal no-miss rate is Tck=1.25 ns (800 MHz)
			Minimal window of 4 ACTIVATE pulses - 16 Tck or 40 (40 ns), so one ACTIVATE per 8 Tck is still OK down to 1.25 ns
			Reads are in 16-byte colums: 1 8-burst (16 bytes) in a row, then next row, bank inc first. Then (if needed) - next column
			Number of rows should be >=5 (4 now for tCK=2.5ns to meet tRP (precharge to activate) of the same bank (tRP=13ns)
			Can read less if just one column
			TODO: Maybe allow less rows with different sequence (no autoprecharge/no activate?) Will not work if row crosses page boundary

			number fo rows>1!

			*/

	module cmd_encod_tiled_rd #(		module cmd_encod_tiled_rd #(
	// parameter BASEADDR = 0,		// parameter BASEADDR = 0,
	@@ -78,7 +89,7 @@ module cmd_encod_tiled_rd #(
	localparam LOOP_FIRST= 5; // address of the first word in a loop		localparam LOOP_FIRST= 5; // address of the first word in a loop
	localparam LOOP_LAST= 6; // address of the last word in a loop		localparam LOOP_LAST= 6; // address of the last word in a loop
	localparam CMD_NOP= 0; // 3-bit normal memory RCW commands (positive logic)		localparam CMD_NOP= 0; // 3-bit normal memory RCW commands (positive logic)
	localparam CMD_READ= 3;		localparam CMD_READ= 2;
	// localparam CMD_PRECHARGE=5;		// localparam CMD_PRECHARGE=5;
	localparam CMD_ACTIVATE= 4;		localparam CMD_ACTIVATE= 4;
	// localparam AUTOPRECHARGE_BIT=COLADDR_NUMBER;		// localparam AUTOPRECHARGE_BIT=COLADDR_NUMBER;
	@@ -94,7 +105,7 @@ module cmd_encod_tiled_rd #(
	reg keep_open;		reg keep_open;
	reg skip_next_page;		reg skip_next_page;
	reg gen_run;		reg gen_run;
	reg gen_run_d;		reg gen_run_d; // to output "done"?
	reg [ROM_DEPTH-1:0] gen_addr; // will overrun as stop comes from ROM		reg [ROM_DEPTH-1:0] gen_addr; // will overrun as stop comes from ROM

	reg [ROM_WIDTH-1:0] rom_r;		reg [ROM_WIDTH-1:0] rom_r;
	@@ -114,40 +125,52 @@ module cmd_encod_tiled_rd #(
	reg start_d; // start, delayed by 1 clocks		reg start_d; // start, delayed by 1 clocks
	wire last_row;		wire last_row;
	reg [FULL_ADDR_NUMBER-1:0] row_col_bank; // RA,CA, BA - valid @pre_act;		reg [FULL_ADDR_NUMBER-1:0] row_col_bank; // RA,CA, BA - valid @pre_act;
	reg [FULL_ADDR_NUMBER-1:0] row_col_bank_inc; // incremented RA,CA, BA - valid @pre_act_d;		/// reg [FULL_ADDR_NUMBER-1:0] row_col_bank_inc; // incremented RA,CA, BA - valid @pre_act_d;
	reg [COLADDR_NUMBER-1:0] col_bank;// CA, BA - valid @ pre_read;		// reg [COLADDR_NUMBER-1:0] col_bank;// CA, BA - valid @ pre_read;
			wire [COLADDR_NUMBER-1:0] col_bank;// CA, BA - valid @ pre_read;
			// reg [COLADDR_NUMBER-1:0] pre_col_bank;// CA, BA - valid @ pre_read;

	wire enable_act;		wire enable_act;
	// wire enable_autopre;		// wire enable_autopre;
	reg enable_autopre;		reg enable_autopre;

	reg pre_act_d;		// reg pre_act_d;
	reg other_row; // other than first row (valid/changed @pre_act)		// reg other_row; // other than first row (valid/changed @pre_act)
	wire [2:0] next_bank_w;		wire [2:0] next_bank_w;
	wire [ADDRESS_NUMBER+COLADDR_NUMBER-4:0] next_rowcol_w; // next row/col when bank rolls over (in 8-bursts)		wire [ADDRESS_NUMBER+COLADDR_NUMBER-4:0] next_rowcol_w; // next row/col when bank rolls over (in 8-bursts)

	reg loop_continue;		reg loop_continue;
	reg last_col_d; // delay by 1 pre_act cycles;		reg last_col_d; // delay by 1 pre_act cycles;

			wire [FULL_ADDR_NUMBER-1:0] row_col_bank_next_w; // RA,CA, BA - valid @pre_act;
			assign row_col_bank_next_w= last_row?
			{top_rc,bank}: // can not work if ACTIVATE is next after ACTIVATE in the last row (single-row tile)
			(&row_col_bank[2:0]? // bank==7
			{next_rowcol_w,3'b0}:
			{row_col_bank[FULL_ADDR_NUMBER-1:3],next_bank_w});


	assign pre_done=rom_r[ENC_PRE_DONE] && gen_run;		assign pre_done=rom_r[ENC_PRE_DONE] && gen_run;
	assign rom_cmd= rom_r[ENC_CMD_SHIFT+:2] & {enable_act,1'b0}; // disable bit 1 if activate is disabled (not the first column)		assign rom_cmd= rom_r[ENC_CMD_SHIFT+:2] & {enable_act,1'b1}; // disable bit 1 if activate is disabled (not the first column)
	assign rom_skip= rom_r[ENC_PAUSE_SHIFT+:2];		assign rom_skip= rom_r[ENC_PAUSE_SHIFT+:2];
	assign full_cmd= rom_cmd[1]?CMD_ACTIVATE:(rom_cmd[0]?CMD_READ:CMD_NOP);		assign full_cmd= rom_cmd[1]?CMD_ACTIVATE:(rom_cmd[0]?CMD_READ:CMD_NOP);

	assign last_row= (scan_row==num_rows_m1);		assign last_row= (scan_row==num_rows_m1);
	assign enable_act= first_col \|\| !keep_open; // TODO: do not forget to zero addresses too (or they will become pause/done)		assign enable_act= first_col \|\| !keep_open; // TODO: do not forget to zero addresses too (or they will become pause/done)
	assign next_bank_w= bank+1;		assign next_bank_w= row_col_bank[2:0]+1; //bank+1;
	assign next_rowcol_w=row_col_bank[FULL_ADDR_NUMBER-1:3]+rowcol_inc;		assign next_rowcol_w=row_col_bank[FULL_ADDR_NUMBER-1:3]+rowcol_inc;

	assign pre_act= rom_r[ENC_CMD_SHIFT+1]; //1 cycle before optional ACTIVATE		// assign pre_act= rom_r[ENC_CMD_SHIFT+1]; //1 cycle before optional ACTIVATE
			// assign pre_act= gen_run_d && rom_r[ENC_CMD_SHIFT+1]; //1 cycle before optional ACTIVATE
			assign pre_act= gen_run && rom_cmd[1]; //1 cycle before optional ACTIVATE
	assign pre_read= rom_r[ENC_CMD_SHIFT]; //1 cycle before READ command		assign pre_read= rom_r[ENC_CMD_SHIFT]; //1 cycle before READ command

	//TODO:Add AUTOPRECHARGE + ACTIVATE when column crossed - No, caller should make sure there is no row address change in the same line		//TODO:Add AUTOPRECHARGE + ACTIVATE when column crossed - No, caller should make sure there is no row address change in the same line

	always @ (posedge rst or posedge clk) begin		always @ (posedge rst or posedge clk) begin
	if (rst) gen_run <= 0;		if (rst) gen_run <= 0;
	else if (start) gen_run<= 1;		// else if (start) gen_run<= 1;
			else if (start_d) gen_run<= 1; // delaying
	else if (pre_done) gen_run<= 0;		else if (pre_done) gen_run<= 0;

	if (rst) gen_run_d <= 0;		if (rst) gen_run_d <= 0;
	@@ -162,25 +185,33 @@ module cmd_encod_tiled_rd #(
	else start_d <= start;		else start_d <= start;

	if (rst) top_rc <= 0;		if (rst) top_rc <= 0;
	else if (start_d) top_rc <= {row,col};		else if (start_d) top_rc <= {row,col}+1;
	else if (pre_act && last_row) top_rc <= top_rc+1; // may increment RA		else if (pre_act && last_row) top_rc <= top_rc+1; // may increment RA
			/*
	if (rst) pre_act_d <= 0;		if (rst) pre_act_d <= 0;
	else if (start_d) pre_act_d <= 0;		/// else if (start_d) pre_act_d <= 0;
	else pre_act_d <= pre_act;		else pre_act_d <= pre_act;

	if (rst) other_row <= 0;		if (rst) other_row <= 0;
	else if (pre_act) other_row <= ~last_row;		else if (pre_act) other_row <= ~last_row;
			*/
	if (rst) row_col_bank <= 0;		if (rst) row_col_bank <= 0;
	else if (start_d) row_col_bank <= {row,col,bank};		else if (start_d) row_col_bank <= {row,col,bank}; // TODO: Use start_col,... and start, not start_d?
	else if (pre_act_d && ~other_row) row_col_bank <= {top_rc,bank};		//TODO: maybe better to move 1 cicle later everything?
	else if (pre_act_d) row_col_bank <= row_col_bank_inc;		// else if (start) row_col_bank <= {start_row,start_col,start_bank}; // TODO: Use start_col,... and start, not start_d?
			// else if (pre_act_d && ~other_row) row_col_bank <= {top_rc,bank};
			// else if (pre_act_d && last_row) row_col_bank <= {top_rc,bank};
			// else if (pre_act_d) row_col_bank <= row_col_bank_inc;

			// else if (pre_act && last_row) row_col_bank <= {top_rc,bank};
			// else if (pre_act) row_col_bank <= row_col_bank_inc;

	if (rst) row_col_bank_inc<=0;		else if (pre_act) row_col_bank <= row_col_bank_next_w;
	else row_col_bank_inc<=(&row_col_bank_inc[2:0]!=0)?
	{row_col_bank_inc[FULL_ADDR_NUMBER-1:3],next_bank_w}:		/// if (rst) row_col_bank_inc<=0;
	{next_rowcol_w,row_col_bank_inc[2:0]};		/// else row_col_bank_inc<=(&row_col_bank_inc[2:0]!=0)?
			/// {row_col_bank_inc[FULL_ADDR_NUMBER-1:3],next_bank_w}:
			/// {next_rowcol_w,row_col_bank_inc[2:0]};

	if (rst) scan_row <= 0;		if (rst) scan_row <= 0;
	else if (start_d) scan_row <= 0;		else if (start_d) scan_row <= 0;
	@@ -206,15 +237,22 @@ module cmd_encod_tiled_rd #(
	else if (start_d) enable_autopre <= 0;		else if (start_d) enable_autopre <= 0;
	else if (pre_act) enable_autopre <= last_col_d \|\| !keep_open; // delayed by 2 pre_act tacts form last_col, OK with a single column		else if (pre_act) enable_autopre <= last_col_d \|\| !keep_open; // delayed by 2 pre_act tacts form last_col, OK with a single column

			//pre_col_bank
			/*
			if (rst) pre_col_bank<=0;
			else if (start_d) pre_col_bank<= {col,bank};
			else if (pre_act) pre_col_bank<= row_col_bank[COLADDR_NUMBER-1:0];

	if (rst) col_bank<=0;		if (rst) col_bank<=0;
	else if (start_d) col_bank<= {col,bank};		else if (start_d) col_bank<= {col,bank};
	else if (pre_read) col_bank<= row_col_bank[COLADDR_NUMBER-1:0];		else if (pre_read) col_bank<= pre_col_bank; //row_col_bank[COLADDR_NUMBER-1:0];
			*/
	if (rst) loop_continue<=0;		if (rst) loop_continue<=0;
	else loop_continue <= (scan_col==num_cols128_m1) && last_row;		else loop_continue <= (scan_col==num_cols128_m1) && last_row;

	if (rst) gen_addr <= 0;		if (rst) gen_addr <= 0;
	else if (!start && !gen_run) gen_addr <= 0;		// else if (!start && !gen_run) gen_addr <= 0;
			else if (!start_d && !gen_run) gen_addr <= 0;
	else if ((gen_addr==LOOP_LAST) && !loop_continue) gen_addr <= LOOP_FIRST; // skip loop alltogeter		else if ((gen_addr==LOOP_LAST) && !loop_continue) gen_addr <= LOOP_FIRST; // skip loop alltogeter
	else gen_addr <= gen_addr+1; // not in a loop		else gen_addr <= gen_addr+1; // not in a loop
	end		end
	@@ -256,7 +294,7 @@ module cmd_encod_tiled_rd #(
	else enc_wr <= gen_run \|\| gen_run_d;		else enc_wr <= gen_run \|\| gen_run_d;

	if (rst) enc_done <= 0;		if (rst) enc_done <= 0;
	else enc_done <= enc_wr \|\| !gen_run_d;		else enc_done <= enc_wr && !gen_run_d;

	if (rst) enc_cmd <= 0;		if (rst) enc_cmd <= 0;
	else if (rom_cmd==0) enc_cmd <= func_encode_skip ( // encode pause		else if (rom_cmd==0) enc_cmd <= func_encode_skip ( // encode pause
	@@ -282,7 +320,7 @@ module cmd_encod_tiled_rd #(
	3'b0}, // [14:0] addr; // 15-bit row/column adderss		3'b0}, // [14:0] addr; // 15-bit row/column adderss
	rom_cmd[1]?		rom_cmd[1]?
	row_col_bank[2:0]:		row_col_bank[2:0]:
	col_bank[2:0], // bank (here OK to be any)		col_bank[2:0], //
	full_cmd[2:0], // rcw; // RAS/CAS/WE, positive logic		full_cmd[2:0], // rcw; // RAS/CAS/WE, positive logic
	1'b0, // odt_en; // enable ODT		1'b0, // odt_en; // enable ODT
	1'b0, // cke; // disable CKE		1'b0, // cke; // disable CKE
	@@ -296,6 +334,17 @@ module cmd_encod_tiled_rd #(
	rom_r[ENC_NOP], // nop; // add NOP after the current command, keep other data		rom_r[ENC_NOP], // nop; // add NOP after the current command, keep other data
	rom_r[ENC_BUF_PGNEXT] && !skip_next_page); // buf_rst; // connect to external buffer (but only if not paused)		rom_r[ENC_BUF_PGNEXT] && !skip_next_page); // buf_rst; // connect to external buffer (but only if not paused)
	end		end
			fifo_2regs #(
			.WIDTH(COLADDR_NUMBER)
			) fifo_2regs_i (
			.rst (rst), // input
			.clk (clk), // input
			.din (row_col_bank[COLADDR_NUMBER-1:0]), // input[15:0]
			.wr(pre_act), // input
			.rd(pre_read), // input
			.srst(start_d), // input
			.dout(col_bank) // output[15:0]
			);

	// move to include?, Yes, after fixing problem with paths		// move to include?, Yes, after fixing problem with paths
	// move to include?		// move to include?

memctrl/mcntrl393.v

+3 −3

memctrl/mcntrl393_test01.v

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -142,7 +142,7 @@ module mcntrl393_test01#(

	if (rst) page_chn4 <= 0;		if (rst) page_chn4 <= 0;
	else if (frame_start_chn4_r) page_chn4 <= 0;		else if (frame_start_chn4_r) page_chn4 <= 0;
	else if (page_ready_chn4) page_chn4 <= page_chn2 + 1;		else if (page_ready_chn4) page_chn4 <= page_chn4 + 1;

	if (rst) suspend_chn2_r <= 0;		if (rst) suspend_chn2_r <= 0;
	else if (set_chh2_mode) suspend_chn2_r <= cmd_suspend_w;		else if (set_chh2_mode) suspend_chn2_r <= cmd_suspend_w;

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