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Commit cbbd4ed1 authored by Andrey Filippov's avatar Andrey Filippov
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split top level test fixture file into separate includes with tasks

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includes/x393_tasks01.vh
View file @ cbbd4ed1
......@@ -2,7 +2,7 @@
* File: x393_tasks01.vh
* Date:2015-02-07
* Author: andrey
* Description: Simulation tasks for the x393
* Description: Simulation tasks for the x393 (low level)
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* x393_tasks01.vh is free software; you can redistribute it and/or modify
......@@ -20,6 +20,14 @@
*******************************************************************************/
// Low-level tasks
// alternative way to check for empty read queue (without a separate counter)
task write_contol_register;
input [29:0] reg_addr;
input [31:0] data;
begin
axi_write_single_w(CONTROL_ADDR+reg_addr, data);
end
endtask
task wait_read_queue_empty;
begin
wait (~rvalid && rready && (rid==LAST_ARID)); // nothing left in read queue?
......
includes/x393_tasks_mcntrl_buffers.vh 0 → 100644
View file @ cbbd4ed1
/*******************************************************************************
* File: x393_tasks_mcntrl_buffers.vh
* Date:2015-02-07
* Author: andrey
* Description: Simulation tasks for software reading/writing (with test patterns)
* of the block buffers.
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* x393_tasks_mcntrl_buffers.vh is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* x393_tasks_mcntrl_buffers.vh is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
//MCONTR_BUF1_WR_ADDR
task write_block_buf_chn; // S uppressThisWarning VEditor : may be unused
input integer chn; // buffer channel
input [1:0] page;
input integer num_words; // number of words to write (will be rounded up to multiple of 16)
reg [29:0] start_addr;
begin
case (chn)
1: start_addr=MCONTR_BUF1_WR_ADDR + (page << 8);
3: start_addr=MCONTR_BUF3_WR_ADDR + (page << 8);
default: begin
$display("**** ERROR: Invalid channel for write buffer = %d @%t", chn, $time);
start_addr = MCONTR_BUF1_WR_ADDR+ (page << 8);
end
endcase
write_block_buf (start_addr, num_words);
end
endtask
task write_block_buf;
input [29:0] start_word_address;
input integer num_words; // number of words to write (will be rounded up to multiple of 16)
integer i, j;
begin
$display("**** write_block_buf @%t", $time);
for (i = 0; i < num_words; i = i + 16) begin
axi_write_addr_data(
i, // id
{start_word_address,2'b0}+( i << 2),
// (MCONTR_BUF1_WR_ADDR + (page <<8)+ i) << 2, // addr
i | (((i + 7) & 'hff) << 8) | (((i + 23) & 'hff) << 16) | (((i + 31) & 'hff) << 24),
4'hf, // len
1, // burst type - increment
1'b1, // data_en
4'hf, // wstrb
1'b0 // last
);
$display("+Write block data (addr:data): 0x%x:0x%08x @%t", i, i | (((i + 7) & 'hff) << 8) | (((i + 23) & 'hff) << 16) | (((i + 31) & 'hff) << 24), $time);
for (j = 1; j < 16; j = j + 1) begin
axi_write_data(
i, // id
(i + j) | ((((i + j) + 7) & 'hff) << 8) | ((((i + j) + 23) & 'hff) << 16) | ((((i + j) + 31) & 'hff) << 24),
4'hf, // wstrb
(1 == 15) ? 1 : 0 // last
);
$display(" Write block data (addr:data): 0x%08x:0x%x @%t", (i + j),
(i + j) | ((((i + j) + 7) & 'hff) << 8) | ((((i + j) + 23) & 'hff) << 16) | ((((i + j) + 31) & 'hff) << 24), $time);
end
end
end
endtask
// read memory
task read_block_buf_chn; // S uppressThisWarning VEditor : may be unused
input integer chn; // buffer channel
input [1:0] page;
input integer num_read; // number of words to read (will be rounded up to multiple of 16)
input wait_done;
reg [29:0] start_addr;
begin
case (chn)
0: start_addr=MCONTR_BUF0_RD_ADDR + (page << 8);
2: start_addr=MCONTR_BUF2_RD_ADDR + (page << 8);
4: start_addr=MCONTR_BUF4_RD_ADDR + (page << 8);
default: begin
$display("**** ERROR: Invalid channel for read buffer = %d @%t", chn, $time);
start_addr = 30'b0+ (page << 8);
end
endcase
read_block_buf (start_addr, num_read, wait_done);
end
endtask
task read_block_buf;
input [29:0] start_word_address;
input integer num_read; // number of words to read (will be rounded up to multiple of 16)
input wait_done;
integer i; //,j;
begin
wait (~rstb);
SIMUL_AXI_FULL<=1'b0;
$display("**** read_block_buf @%t", $time);
axi_set_rd_lag(0);
for (i = 0; i < num_read; i = i + 16) begin
wait(arready);
// $display ("read_block_buf (0x%x) @%t",i,$time);
axi_read_addr(
i, // id
{start_word_address,2'b0}+( i << 2), // addr
4'hf, // len
1 // burst type - increment
);
end
if (wait_done) begin
// wait (AXI_RD_EMPTY);
wait_read_queue_empty;
end
end
endtask
includes/x393_tasks_mcntrl_en_dis_priority.vh 0 → 100644
View file @ cbbd4ed1
/*******************************************************************************
* File: x393_tasks_mcntrl_en_dis_priority.vh
* Date:2015-02-07
* Author: andrey
* Description: Simulation tasks for software reading/writing (with test patterns)
* of the block buffers.
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* x393_tasks_mcntrl_en_dis_priority.vh is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* x393_tasks_mcntrl_en_dis_priority.vh is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
task enable_cmda;
input en;
begin
write_contol_register(MCONTR_PHY_0BIT_ADDR + MCONTR_PHY_0BIT_CMDA_EN + en, 0);
end
endtask
task enable_cke;
input en;
begin
write_contol_register(MCONTR_PHY_0BIT_ADDR + MCONTR_PHY_0BIT_CKE_EN + en, 0);
end
endtask
task activate_sdrst;
input en;
begin
write_contol_register(MCONTR_PHY_0BIT_ADDR + MCONTR_PHY_0BIT_SDRST_ACT + en, 0);
end
endtask
task enable_refresh;
input en;
begin
write_contol_register(MCONTR_TOP_0BIT_ADDR + MCONTR_TOP_0BIT_REFRESH_EN + en, 0);
end
endtask
task enable_memcntrl;
input en;
begin
write_contol_register(MCONTR_TOP_0BIT_ADDR + MCONTR_TOP_0BIT_MCONTR_EN + en, 0);
end
endtask
task enable_memcntrl_channels;
input [15:0] chnen; // bit-per-channel, 1 - enable;
begin
write_contol_register(MCONTR_TOP_16BIT_ADDR + MCONTR_TOP_16BIT_CHN_EN, {16'b0,chnen});
end
endtask
task configure_channel_priority;
input [ 3:0] chn;
input [15:0] priority; // (higher is more important)
begin
write_contol_register(MCONTR_ARBIT_ADDR + chn, {16'b0,priority});
end
endtask
includes/x393_tasks_mcntrl_timing.vh 0 → 100644
View file @ cbbd4ed1
/*******************************************************************************
* File: x393_tasks_mcntrl_timing.vh
* Date:2015-02-07
* Author: andrey
* Description: Simulation tasks for programming I/O delays and other timing
* parameters in the memory controller
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* x393_tasks_mcntrl_timing.vh is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* x393_tasks_mcntrl_timing.vh is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
task axi_set_same_delays; //SuppressThisWarning VEditor : may be unused
input [7:0] dq_idelay;
input [7:0] dq_odelay;
input [7:0] dqs_idelay;
input [7:0] dqs_odelay;
input [7:0] dm_odelay;
input [7:0] cmda_odelay;
begin
$display("SET DELAYS(0x%x,0x%x,0x%x,0x%x,0x%x,0x%x) @ %t",
dq_idelay,dq_odelay,dqs_idelay,dqs_odelay,dm_odelay,cmda_odelay,$time);
axi_set_dq_idelay(dq_idelay);
axi_set_dq_odelay(dq_odelay);
axi_set_dqs_idelay(dqs_idelay);
axi_set_dqs_odelay(dqs_odelay);
axi_set_dm_odelay(dm_odelay);
axi_set_cmda_odelay(cmda_odelay);
end
endtask
task axi_set_dqs_odelay_nominal; //SuppressThisWarning VEditor : may be unused
begin
// axi_set_dqs_idelay(
write_contol_register(LD_DLY_LANE0_ODELAY + 8, (DLY_LANE0_ODELAY >> (8<<3)) & 32'hff);
write_contol_register(LD_DLY_LANE1_ODELAY + 8, (DLY_LANE1_ODELAY >> (8<<3)) & 32'hff);
write_contol_register(DLY_SET,0);
end
endtask
task axi_set_dqs_idelay_nominal; //SuppressThisWarning VEditor : may be unused
begin
// axi_set_dqs_idelay(
write_contol_register(LD_DLY_LANE0_IDELAY + 8, (DLY_LANE0_IDELAY >> (8<<3)) & 32'hff);
write_contol_register(LD_DLY_LANE1_IDELAY + 8, (DLY_LANE1_IDELAY >> (8<<3)) & 32'hff);
write_contol_register(DLY_SET,0);
end
endtask
task axi_set_dqs_idelay_wlv; //SuppressThisWarning VEditor : may be unused
begin
write_contol_register(LD_DLY_LANE0_IDELAY + 8, DLY_LANE0_DQS_WLV_IDELAY);
write_contol_register(LD_DLY_LANE1_IDELAY + 8, DLY_LANE1_DQS_WLV_IDELAY);
write_contol_register(DLY_SET,0);
end
endtask
task axi_set_delays; // set all individual delays
integer i;
begin
for (i=0;i<10;i=i+1) begin
write_contol_register(LD_DLY_LANE0_ODELAY + i, (DLY_LANE0_ODELAY >> (i<<3)) & 32'hff);
end
for (i=0;i<9;i=i+1) begin
write_contol_register(LD_DLY_LANE0_IDELAY + i, (DLY_LANE0_IDELAY >> (i<<3)) & 32'hff);
end
for (i=0;i<10;i=i+1) begin
write_contol_register(LD_DLY_LANE1_ODELAY + i, (DLY_LANE1_ODELAY >> (i<<3)) & 32'hff);
end
for (i=0;i<9;i=i+1) begin
write_contol_register(LD_DLY_LANE1_IDELAY + i, (DLY_LANE1_IDELAY >> (i<<3)) & 32'hff);
end
for (i=0;i<32;i=i+1) begin
write_contol_register(LD_DLY_CMDA + i, (DLY_CMDA >> (i<<3)) & 32'hff);
end
// write_contol_register(DLY_SET,0);
axi_set_phase(DLY_PHASE); // also sets all delays
end
endtask
task axi_set_dq_idelay; // sets same delay to all dq idelay
input [7:0] delay;
begin
$display("SET DQ IDELAY=0x%x @ %t",delay,$time);
axi_set_multiple_delays(LD_DLY_LANE0_IDELAY, 8, delay);
axi_set_multiple_delays(LD_DLY_LANE1_IDELAY, 8, delay);
write_contol_register(DLY_SET,0); // set all delays
end
endtask
task axi_set_dq_odelay;
input [7:0] delay;
begin
$display("SET DQ ODELAY=0x%x @ %t",delay,$time);
axi_set_multiple_delays(LD_DLY_LANE0_ODELAY, 8, delay);
axi_set_multiple_delays(LD_DLY_LANE1_ODELAY, 8, delay);
write_contol_register(DLY_SET,0); // set all delays
end
endtask
task axi_set_dqs_idelay;
input [7:0] delay;
begin
$display("SET DQS IDELAY=0x%x @ %t",delay,$time);
axi_set_multiple_delays(LD_DLY_LANE0_IDELAY + 8, 1, delay);
axi_set_multiple_delays(LD_DLY_LANE1_IDELAY + 8, 1, delay);
write_contol_register(DLY_SET,0); // set all delays
end
endtask
task axi_set_dqs_odelay;
input [7:0] delay;
begin
$display("SET DQS ODELAY=0x%x @ %t",delay,$time);
axi_set_multiple_delays(LD_DLY_LANE0_ODELAY + 8, 1, delay);
axi_set_multiple_delays(LD_DLY_LANE1_ODELAY + 8, 1, delay);
write_contol_register(DLY_SET,0); // set all delays
end
endtask
task axi_set_dm_odelay;
input [7:0] delay;
begin
$display("SET DQM IDELAY=0x%x @ %t",delay,$time);
axi_set_multiple_delays(LD_DLY_LANE0_ODELAY + 9, 1, delay);
axi_set_multiple_delays(LD_DLY_LANE1_ODELAY + 9, 1, delay);
write_contol_register(DLY_SET,0); // set all delays
end
endtask
task axi_set_cmda_odelay;
input [7:0] delay;
begin
$display("SET COMMAND and ADDRESS ODELAY=0x%x @ %t",delay,$time);
axi_set_multiple_delays(LD_DLY_CMDA, 32, delay);
write_contol_register(DLY_SET,0); // set all delays
end
endtask
task axi_set_multiple_delays;
input [29:0] reg_addr;
input integer number;
input [7:0] delay;
integer i;
begin
for (i=0;i<number;i=i+1) begin
write_contol_register(reg_addr + i, {24'b0,delay}); // control regiter address
end
end
endtask
task axi_set_phase;
input [PHASE_WIDTH-1:0] phase;
begin
$display("SET CLOCK PHASE to 0x%x @ %t",phase,$time);
write_contol_register(LD_DLY_PHASE, {{(32-PHASE_WIDTH){1'b0}},phase}); // control regiter address
write_contol_register(DLY_SET,0);
target_phase <= phase;
end
endtask
task axi_set_wbuf_delay;
input [3:0] delay;
begin
$display("SET WBUF DELAY to 0x%x @ %t",delay,$time);
write_contol_register(MCONTR_PHY_16BIT_ADDR+MCONTR_PHY_16BIT_WBUF_DELAY, {28'h0, delay});
end
endtask
// set dq /dqs tristate on/off patterns
task axi_set_tristate_patterns;
begin
$display("SET TRISTATE PATTERNS @ %t",$time);
write_contol_register(MCONTR_PHY_16BIT_ADDR +MCONTR_PHY_16BIT_PATTERNS_TRI,
{16'h0, DQSTRI_LAST, DQSTRI_FIRST, DQTRI_LAST, DQTRI_FIRST});
end
endtask
task axi_set_dqs_dqm_patterns;
begin
$display("SET DQS+DQM PATTERNS @ %t",$time);
// set patterns for DM (always 0) and DQS - always the same (may try different for write lev.)
write_contol_register(MCONTR_PHY_16BIT_ADDR + MCONTR_PHY_16BIT_PATTERNS,
32'h0055);
end
endtask
includes/x393_tasks_pio_sequences.vh 0 → 100644
View file @ cbbd4ed1
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includes/x393_tasks_ps_pio.vh 0 → 100644
View file @ cbbd4ed1
/*******************************************************************************
* File: x393_tasks_ps_pio.vh
* Date:2015-02-07
* Author: andrey
* Description: Simulation tasks for mcntrl_ps_pio module (launching software
* - programmed memory transaction sequences)
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* x393_tasks_ps_pio.vh is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* x393_tasks_ps_pio.vh is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
task schedule_ps_pio; // shedule software-control memory operation (may need to check FIFO status first)
input [9:0] seq_addr; // sequence start address
input [1:0] page; // buffer page number
input urgent; // high priority request (only for competion wityh other channels, wiil not pass in this FIFO)
input chn; // channel buffer to use: 0 - memory read, 1 - memory write
input wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished
begin
// wait_ps_pio_ready(DEFAULT_STATUS_MODE); // wait FIFO not half full
write_contol_register(MCNTRL_PS_ADDR + MCNTRL_PS_CMD, {17'b0,wait_complete,chn,urgent,page,seq_addr});
end
endtask
task wait_ps_pio_ready; // wait PS PIO module can accept comamnds (fifo half empty)
input [1:0] mode;
begin
wait_status_condition (
MCNTRL_PS_STATUS_REG_ADDR,
MCNTRL_PS_ADDR+MCNTRL_PS_STATUS_CNTRL,
mode,
0,
2 << STATUS_2LSB_SHFT,
0);
end
endtask
task wait_ps_pio_done; // wait PS PIO module has no pending/running memory transaction
input [1:0] mode;
begin
wait_status_condition (
MCNTRL_PS_STATUS_REG_ADDR,
MCNTRL_PS_ADDR+MCNTRL_PS_STATUS_CNTRL,
mode,
0,
3 << STATUS_2LSB_SHFT,
0);
end
endtask
includes/x393_tasks_status.vh 0 → 100644
View file @ cbbd4ed1
/*******************************************************************************
* File: x393_status.vh
* Date:2015-02-07
* Author: andrey
* Description: Simulation tasks for the x393 related to status
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* x393_status.vh is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* x393_status.vh is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
task wait_status_condition;
input [STATUS_DEPTH-1:0] status_address;
input [29:0] status_control_address;
input [1:0] status_mode;
input [25:0] pattern; // bits as in read registers
input [25:0] mask; // which bits to compare
input invert_match; // 0 - wait until match to pattern (all bits), 1 - wait until no match (any of bits differ)
reg match;
reg [5:0] seq_num;
begin
WAITING_STATUS = 1;
for (match=0; !match; match = invert_match ^ (((registered_rdata ^ {6'h0,pattern}) & {6'h0,mask})==0)) begin
read_and_wait_status(status_address);
write_contol_register(status_control_address, {24'b0,status_mode,registered_rdata[STATUS_SEQ_SHFT+:6] ^ 6'h20});
seq_num <= registered_rdata[STATUS_SEQ_SHFT+:6] ^ 6'h20;
read_and_wait_status(status_address);
while (((registered_rdata[STATUS_SEQ_SHFT+:6] ^ seq_num) & 6'h30)!=0) begin // match just 2 MSBs
read_and_wait_status(status_address);
end
end
WAITING_STATUS = 0;
end
endtask
task wait_phase_shifter_ready;
begin
WAITING_STATUS = 1;
read_and_wait_status(MCONTR_PHY_STATUS_REG_ADDR);
while (((registered_rdata & STATUS_PSHIFTER_RDY_MASK) == 0) || (((registered_rdata ^ {24'h0,target_phase}) & 'hff) != 0)) begin
read_and_wait_status(MCONTR_PHY_STATUS_REG_ADDR); // exits after negedge CLK
end
WAITING_STATUS = 0;
end
endtask
task read_all_status;
begin
read_and_wait_status (MCONTR_PHY_STATUS_REG_ADDR);
read_and_wait_status (MCONTR_TOP_STATUS_REG_ADDR);
read_and_wait_status (MCNTRL_PS_STATUS_REG_ADDR);
read_and_wait_status (MCNTRL_SCANLINE_STATUS_REG_CHN2_ADDR);
read_and_wait_status (MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR);
read_and_wait_status (MCNTRL_TILED_STATUS_REG_CHN4_ADDR);
read_and_wait_status (MCNTRL_TEST01_STATUS_REG_CHN2_ADDR);
read_and_wait_status (MCNTRL_TEST01_STATUS_REG_CHN3_ADDR);
read_and_wait_status (MCNTRL_TEST01_STATUS_REG_CHN4_ADDR);
end
endtask
task read_and_wait_status;
input [STATUS_DEPTH-1:0] address;
begin
read_and_wait_w(STATUS_ADDR + address ); // Will set: registered_rdata <= rdata;
end
endtask
task program_status_all;
input [1:0] mode;
input [5:0] seq_num;
begin
program_status (MCONTR_PHY_16BIT_ADDR, MCONTR_PHY_STATUS_CNTRL, mode,seq_num); //MCONTR_PHY_STATUS_REG_ADDR= 'h0,
program_status (MCONTR_TOP_16BIT_ADDR, MCONTR_TOP_16BIT_STATUS_CNTRL, mode,seq_num); //MCONTR_TOP_STATUS_REG_ADDR= 'h1,
program_status (MCNTRL_PS_ADDR, MCNTRL_PS_STATUS_CNTRL, mode,seq_num); //MCNTRL_PS_STATUS_REG_ADDR= 'h2,
program_status (MCNTRL_SCANLINE_CHN2_ADDR, MCNTRL_SCANLINE_STATUS_CNTRL, mode,seq_num); //MCNTRL_SCANLINE_STATUS_REG_CHN2_ADDR='h4,
program_status (MCNTRL_SCANLINE_CHN3_ADDR, MCNTRL_SCANLINE_STATUS_CNTRL, mode,seq_num); //MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR='h5,
program_status (MCNTRL_TILED_CHN4_ADDR, MCNTRL_TILED_STATUS_CNTRL, mode,seq_num); //MCNTRL_TILED_STATUS_REG_CHN4_ADDR= 'h6,
program_status (MCNTRL_TEST01_ADDR, MCNTRL_TEST01_CHN2_STATUS_CNTRL,mode,seq_num); //MCNTRL_TEST01_STATUS_REG_CHN2_ADDR= 'h3c,
program_status (MCNTRL_TEST01_ADDR, MCNTRL_TEST01_CHN3_STATUS_CNTRL,mode,seq_num); //MCNTRL_TEST01_STATUS_REG_CHN3_ADDR= 'h3d,
program_status (MCNTRL_TEST01_ADDR, MCNTRL_TEST01_CHN4_STATUS_CNTRL,mode,seq_num); //MCNTRL_TEST01_STATUS_REG_CHN4_ADDR= 'h3e,
end
endtask
task program_status;
input [29:0] base_addr;
input [7:0] reg_addr;
input [1:0] mode;
// mode bits:
// 0 disable status generation,
// 1 single status request,
// 2 - auto status, keep specified seq number,
// 3 - auto, inc sequence number
input [5:0] seq_number;
begin
// axi_write_single_w(CONTROL_ADDR+base_addr+reg_addr, {24'b0,mode,seq_number});
write_contol_register(base_addr + reg_addr, {24'b0,mode,seq_number});
end
endtask
x393_testbench01.sav
View file @ cbbd4ed1
[*]
[*] GTKWave Analyzer v3.3.58 (w)1999-2014 BSI
[*] Fri Feb 13 18:38:10 2015
[*] Fri Feb 13 20:24:18 2015
[*]
[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench01-20150213111425884.lxt"
[dumpfile_mtime] "Fri Feb 13 18:19:38 2015"
[dumpfile_size] 232662775
[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench01-20150213113832125.lxt"
[dumpfile_mtime] "Fri Feb 13 18:43:22 2015"
[dumpfile_size] 233070602
[savefile] "/home/andrey/git/x393/x393_testbench01.sav"
[timestart] 138611000
[timestart] 97060000
[size] 1823 1173
[pos] 1922 0
*-20.698502 143181875 141406879 141780000 142422500 142495000 143137500 143495000 144137500 140756879 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
*-23.698502 146225000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] x393_testbench01.
[treeopen] x393_testbench01.x393_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.
......@@ -1455,6 +1455,8 @@ x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.rpage_in[1:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.rpage_set[0]
@1000200
-PS_PIO_CHN1
@c00201
-other_modules
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ext_buf_rrun[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ext_buf_wrun[0]
......@@ -1490,6 +1492,8 @@ x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.seq_done1[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.seq_done0[0]
@1001200
-group_end
@1401201
-other_modules
@200
-
@28
......
x393_testbench01.tf
View file @ cbbd4ed1
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