split top level test fixture file into separate includes with tasks (cbbd4ed1) · Commits · Elphel / x393

includes/x393_tasks01.vh

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	@@ -2,7 +2,7 @@
	* File: x393_tasks01.vh		* File: x393_tasks01.vh
	* Date:2015-02-07		* Date:2015-02-07
	* Author: andrey		* Author: andrey
	* Description: Simulation tasks for the x393		* Description: Simulation tasks for the x393 (low level)
	*		*
	* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .		* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
	* x393_tasks01.vh is free software; you can redistribute it and/or modify		* x393_tasks01.vh is free software; you can redistribute it and/or modify
	@@ -20,6 +20,14 @@
	*******************************************************************************/		*******************************************************************************/
	// Low-level tasks		// Low-level tasks
	// alternative way to check for empty read queue (without a separate counter)		// alternative way to check for empty read queue (without a separate counter)
			task write_contol_register;
			input [29:0] reg_addr;
			input [31:0] data;
			begin
			axi_write_single_w(CONTROL_ADDR+reg_addr, data);
			end
			endtask

	task wait_read_queue_empty;		task wait_read_queue_empty;
	begin		begin
	wait (~rvalid && rready && (rid==LAST_ARID)); // nothing left in read queue?		wait (~rvalid && rready && (rid==LAST_ARID)); // nothing left in read queue?

includes/x393_tasks_mcntrl_buffers.vh

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			/*******************************************************************************
			* File: x393_tasks_mcntrl_buffers.vh
			* Date:2015-02-07
			* Author: andrey
			* Description: Simulation tasks for software reading/writing (with test patterns)
			* of the block buffers.
			*
			* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
			* x393_tasks_mcntrl_buffers.vh is free software; you can redistribute it and/or modify
			* it under the terms of the GNU General Public License as published by
			* the Free Software Foundation, either version 3 of the License, or
			* (at your option) any later version.
			*
			* x393_tasks_mcntrl_buffers.vh is distributed in the hope that it will be useful,
			* but WITHOUT ANY WARRANTY; without even the implied warranty of
			* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
			* GNU General Public License for more details.
			*
			* You should have received a copy of the GNU General Public License
			* along with this program. If not, see <http://www.gnu.org/licenses/> .
			*******************************************************************************/
			//MCONTR_BUF1_WR_ADDR
			task write_block_buf_chn; // S uppressThisWarning VEditor : may be unused
			input integer chn; // buffer channel
			input [1:0] page;
			input integer num_words; // number of words to write (will be rounded up to multiple of 16)
			reg [29:0] start_addr;
			begin
			case (chn)
			1: start_addr=MCONTR_BUF1_WR_ADDR + (page << 8);
			3: start_addr=MCONTR_BUF3_WR_ADDR + (page << 8);
			default: begin
			$display("**** ERROR: Invalid channel for write buffer = %d @%t", chn, $time);
			start_addr = MCONTR_BUF1_WR_ADDR+ (page << 8);
			end
			endcase
			write_block_buf (start_addr, num_words);
			end
			endtask

			task write_block_buf;
			input [29:0] start_word_address;
			input integer num_words; // number of words to write (will be rounded up to multiple of 16)
			integer i, j;
			begin
			$display("**** write_block_buf @%t", $time);
			for (i = 0; i < num_words; i = i + 16) begin
			axi_write_addr_data(
			i, // id
			{start_word_address,2'b0}+( i << 2),
			// (MCONTR_BUF1_WR_ADDR + (page <<8)+ i) << 2, // addr
			i \| (((i + 7) & 'hff) << 8) \| (((i + 23) & 'hff) << 16) \| (((i + 31) & 'hff) << 24),
			4'hf, // len
			1, // burst type - increment
			1'b1, // data_en
			4'hf, // wstrb
			1'b0 // last
			);
			$display("+Write block data (addr:data): 0x%x:0x%08x @%t", i, i \| (((i + 7) & 'hff) << 8) \| (((i + 23) & 'hff) << 16) \| (((i + 31) & 'hff) << 24), $time);
			for (j = 1; j < 16; j = j + 1) begin
			axi_write_data(
			i, // id
			(i + j) \| ((((i + j) + 7) & 'hff) << 8) \| ((((i + j) + 23) & 'hff) << 16) \| ((((i + j) + 31) & 'hff) << 24),
			4'hf, // wstrb
			(1 == 15) ? 1 : 0 // last
			);
			$display(" Write block data (addr:data): 0x%08x:0x%x @%t", (i + j),
			(i + j) \| ((((i + j) + 7) & 'hff) << 8) \| ((((i + j) + 23) & 'hff) << 16) \| ((((i + j) + 31) & 'hff) << 24), $time);
			end
			end

			end
			endtask

			// read memory
			task read_block_buf_chn; // S uppressThisWarning VEditor : may be unused
			input integer chn; // buffer channel
			input [1:0] page;
			input integer num_read; // number of words to read (will be rounded up to multiple of 16)
			input wait_done;
			reg [29:0] start_addr;
			begin
			case (chn)
			0: start_addr=MCONTR_BUF0_RD_ADDR + (page << 8);
			2: start_addr=MCONTR_BUF2_RD_ADDR + (page << 8);
			4: start_addr=MCONTR_BUF4_RD_ADDR + (page << 8);
			default: begin
			$display("**** ERROR: Invalid channel for read buffer = %d @%t", chn, $time);
			start_addr = 30'b0+ (page << 8);
			end
			endcase
			read_block_buf (start_addr, num_read, wait_done);
			end
			endtask

			task read_block_buf;
			input [29:0] start_word_address;
			input integer num_read; // number of words to read (will be rounded up to multiple of 16)
			input wait_done;
			integer i; //,j;
			begin
			wait (~rstb);
			SIMUL_AXI_FULL<=1'b0;
			$display("**** read_block_buf @%t", $time);
			axi_set_rd_lag(0);
			for (i = 0; i < num_read; i = i + 16) begin
			wait(arready);
			// $display ("read_block_buf (0x%x) @%t",i,$time);
			axi_read_addr(
			i, // id
			{start_word_address,2'b0}+( i << 2), // addr
			4'hf, // len
			1 // burst type - increment
			);
			end
			if (wait_done) begin
			// wait (AXI_RD_EMPTY);
			wait_read_queue_empty;
			end
			end
			endtask

includes/x393_tasks_mcntrl_en_dis_priority.vh

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			/*******************************************************************************
			* File: x393_tasks_mcntrl_en_dis_priority.vh
			* Date:2015-02-07
			* Author: andrey
			* Description: Simulation tasks for software reading/writing (with test patterns)
			* of the block buffers.
			*
			* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
			* x393_tasks_mcntrl_en_dis_priority.vh is free software; you can redistribute it and/or modify
			* it under the terms of the GNU General Public License as published by
			* the Free Software Foundation, either version 3 of the License, or
			* (at your option) any later version.
			*
			* x393_tasks_mcntrl_en_dis_priority.vh is distributed in the hope that it will be useful,
			* but WITHOUT ANY WARRANTY; without even the implied warranty of
			* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
			* GNU General Public License for more details.
			*
			* You should have received a copy of the GNU General Public License
			* along with this program. If not, see <http://www.gnu.org/licenses/> .
			*******************************************************************************/
			task enable_cmda;
			input en;
			begin
			write_contol_register(MCONTR_PHY_0BIT_ADDR + MCONTR_PHY_0BIT_CMDA_EN + en, 0);
			end
			endtask

			task enable_cke;
			input en;
			begin
			write_contol_register(MCONTR_PHY_0BIT_ADDR + MCONTR_PHY_0BIT_CKE_EN + en, 0);
			end
			endtask

			task activate_sdrst;
			input en;
			begin
			write_contol_register(MCONTR_PHY_0BIT_ADDR + MCONTR_PHY_0BIT_SDRST_ACT + en, 0);
			end
			endtask

			task enable_refresh;
			input en;
			begin
			write_contol_register(MCONTR_TOP_0BIT_ADDR + MCONTR_TOP_0BIT_REFRESH_EN + en, 0);
			end
			endtask

			task enable_memcntrl;
			input en;
			begin
			write_contol_register(MCONTR_TOP_0BIT_ADDR + MCONTR_TOP_0BIT_MCONTR_EN + en, 0);
			end
			endtask

			task enable_memcntrl_channels;
			input [15:0] chnen; // bit-per-channel, 1 - enable;
			begin
			write_contol_register(MCONTR_TOP_16BIT_ADDR + MCONTR_TOP_16BIT_CHN_EN, {16'b0,chnen});
			end
			endtask

			task configure_channel_priority;
			input [ 3:0] chn;
			input [15:0] priority; // (higher is more important)
			begin
			write_contol_register(MCONTR_ARBIT_ADDR + chn, {16'b0,priority});
			end
			endtask

includes/x393_tasks_mcntrl_timing.vh

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			/*******************************************************************************
			* File: x393_tasks_mcntrl_timing.vh
			* Date:2015-02-07
			* Author: andrey
			* Description: Simulation tasks for programming I/O delays and other timing
			* parameters in the memory controller
			*
			* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
			* x393_tasks_mcntrl_timing.vh is free software; you can redistribute it and/or modify
			* it under the terms of the GNU General Public License as published by
			* the Free Software Foundation, either version 3 of the License, or
			* (at your option) any later version.
			*
			* x393_tasks_mcntrl_timing.vh is distributed in the hope that it will be useful,
			* but WITHOUT ANY WARRANTY; without even the implied warranty of
			* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
			* GNU General Public License for more details.
			*
			* You should have received a copy of the GNU General Public License
			* along with this program. If not, see <http://www.gnu.org/licenses/> .
			*******************************************************************************/

			task axi_set_same_delays; //SuppressThisWarning VEditor : may be unused
			input [7:0] dq_idelay;
			input [7:0] dq_odelay;
			input [7:0] dqs_idelay;
			input [7:0] dqs_odelay;
			input [7:0] dm_odelay;
			input [7:0] cmda_odelay;
			begin
			$display("SET DELAYS(0x%x,0x%x,0x%x,0x%x,0x%x,0x%x) @ %t",
			dq_idelay,dq_odelay,dqs_idelay,dqs_odelay,dm_odelay,cmda_odelay,$time);
			axi_set_dq_idelay(dq_idelay);
			axi_set_dq_odelay(dq_odelay);
			axi_set_dqs_idelay(dqs_idelay);
			axi_set_dqs_odelay(dqs_odelay);
			axi_set_dm_odelay(dm_odelay);
			axi_set_cmda_odelay(cmda_odelay);
			end
			endtask

			task axi_set_dqs_odelay_nominal; //SuppressThisWarning VEditor : may be unused
			begin
			// axi_set_dqs_idelay(
			write_contol_register(LD_DLY_LANE0_ODELAY + 8, (DLY_LANE0_ODELAY >> (8<<3)) & 32'hff);
			write_contol_register(LD_DLY_LANE1_ODELAY + 8, (DLY_LANE1_ODELAY >> (8<<3)) & 32'hff);
			write_contol_register(DLY_SET,0);
			end
			endtask

			task axi_set_dqs_idelay_nominal; //SuppressThisWarning VEditor : may be unused
			begin
			// axi_set_dqs_idelay(
			write_contol_register(LD_DLY_LANE0_IDELAY + 8, (DLY_LANE0_IDELAY >> (8<<3)) & 32'hff);
			write_contol_register(LD_DLY_LANE1_IDELAY + 8, (DLY_LANE1_IDELAY >> (8<<3)) & 32'hff);
			write_contol_register(DLY_SET,0);
			end
			endtask

			task axi_set_dqs_idelay_wlv; //SuppressThisWarning VEditor : may be unused
			begin
			write_contol_register(LD_DLY_LANE0_IDELAY + 8, DLY_LANE0_DQS_WLV_IDELAY);
			write_contol_register(LD_DLY_LANE1_IDELAY + 8, DLY_LANE1_DQS_WLV_IDELAY);
			write_contol_register(DLY_SET,0);
			end
			endtask

			task axi_set_delays; // set all individual delays
			integer i;
			begin
			for (i=0;i<10;i=i+1) begin
			write_contol_register(LD_DLY_LANE0_ODELAY + i, (DLY_LANE0_ODELAY >> (i<<3)) & 32'hff);
			end
			for (i=0;i<9;i=i+1) begin
			write_contol_register(LD_DLY_LANE0_IDELAY + i, (DLY_LANE0_IDELAY >> (i<<3)) & 32'hff);
			end
			for (i=0;i<10;i=i+1) begin
			write_contol_register(LD_DLY_LANE1_ODELAY + i, (DLY_LANE1_ODELAY >> (i<<3)) & 32'hff);
			end
			for (i=0;i<9;i=i+1) begin
			write_contol_register(LD_DLY_LANE1_IDELAY + i, (DLY_LANE1_IDELAY >> (i<<3)) & 32'hff);
			end
			for (i=0;i<32;i=i+1) begin
			write_contol_register(LD_DLY_CMDA + i, (DLY_CMDA >> (i<<3)) & 32'hff);
			end
			// write_contol_register(DLY_SET,0);
			axi_set_phase(DLY_PHASE); // also sets all delays
			end
			endtask


			task axi_set_dq_idelay; // sets same delay to all dq idelay
			input [7:0] delay;
			begin
			$display("SET DQ IDELAY=0x%x @ %t",delay,$time);
			axi_set_multiple_delays(LD_DLY_LANE0_IDELAY, 8, delay);
			axi_set_multiple_delays(LD_DLY_LANE1_IDELAY, 8, delay);
			write_contol_register(DLY_SET,0); // set all delays
			end
			endtask

			task axi_set_dq_odelay;
			input [7:0] delay;
			begin
			$display("SET DQ ODELAY=0x%x @ %t",delay,$time);
			axi_set_multiple_delays(LD_DLY_LANE0_ODELAY, 8, delay);
			axi_set_multiple_delays(LD_DLY_LANE1_ODELAY, 8, delay);
			write_contol_register(DLY_SET,0); // set all delays
			end
			endtask

			task axi_set_dqs_idelay;
			input [7:0] delay;
			begin
			$display("SET DQS IDELAY=0x%x @ %t",delay,$time);
			axi_set_multiple_delays(LD_DLY_LANE0_IDELAY + 8, 1, delay);
			axi_set_multiple_delays(LD_DLY_LANE1_IDELAY + 8, 1, delay);
			write_contol_register(DLY_SET,0); // set all delays
			end
			endtask

			task axi_set_dqs_odelay;
			input [7:0] delay;
			begin
			$display("SET DQS ODELAY=0x%x @ %t",delay,$time);
			axi_set_multiple_delays(LD_DLY_LANE0_ODELAY + 8, 1, delay);
			axi_set_multiple_delays(LD_DLY_LANE1_ODELAY + 8, 1, delay);
			write_contol_register(DLY_SET,0); // set all delays
			end
			endtask

			task axi_set_dm_odelay;
			input [7:0] delay;
			begin
			$display("SET DQM IDELAY=0x%x @ %t",delay,$time);
			axi_set_multiple_delays(LD_DLY_LANE0_ODELAY + 9, 1, delay);
			axi_set_multiple_delays(LD_DLY_LANE1_ODELAY + 9, 1, delay);
			write_contol_register(DLY_SET,0); // set all delays
			end
			endtask

			task axi_set_cmda_odelay;
			input [7:0] delay;
			begin
			$display("SET COMMAND and ADDRESS ODELAY=0x%x @ %t",delay,$time);
			axi_set_multiple_delays(LD_DLY_CMDA, 32, delay);
			write_contol_register(DLY_SET,0); // set all delays
			end
			endtask


			task axi_set_multiple_delays;
			input [29:0] reg_addr;
			input integer number;
			input [7:0] delay;
			integer i;
			begin
			for (i=0;i<number;i=i+1) begin
			write_contol_register(reg_addr + i, {24'b0,delay}); // control regiter address
			end
			end
			endtask

			task axi_set_phase;
			input [PHASE_WIDTH-1:0] phase;
			begin
			$display("SET CLOCK PHASE to 0x%x @ %t",phase,$time);
			write_contol_register(LD_DLY_PHASE, {{(32-PHASE_WIDTH){1'b0}},phase}); // control regiter address
			write_contol_register(DLY_SET,0);
			target_phase <= phase;
			end
			endtask

			task axi_set_wbuf_delay;
			input [3:0] delay;
			begin
			$display("SET WBUF DELAY to 0x%x @ %t",delay,$time);
			write_contol_register(MCONTR_PHY_16BIT_ADDR+MCONTR_PHY_16BIT_WBUF_DELAY, {28'h0, delay});
			end
			endtask


			// set dq /dqs tristate on/off patterns
			task axi_set_tristate_patterns;
			begin
			$display("SET TRISTATE PATTERNS @ %t",$time);
			write_contol_register(MCONTR_PHY_16BIT_ADDR +MCONTR_PHY_16BIT_PATTERNS_TRI,
			{16'h0, DQSTRI_LAST, DQSTRI_FIRST, DQTRI_LAST, DQTRI_FIRST});
			end
			endtask

			task axi_set_dqs_dqm_patterns;
			begin
			$display("SET DQS+DQM PATTERNS @ %t",$time);
			// set patterns for DM (always 0) and DQS - always the same (may try different for write lev.)
			write_contol_register(MCONTR_PHY_16BIT_ADDR + MCONTR_PHY_16BIT_PATTERNS,
			32'h0055);
			end
			endtask

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